Move QOM typedefs and add missing includesSome typedefs and macros are defined after the type check macros.This makes it difficult to automatically replace theirdefinitions with OBJECT_DECLARE_TY
Move QOM typedefs and add missing includesSome typedefs and macros are defined after the type check macros.This makes it difficult to automatically replace theirdefinitions with OBJECT_DECLARE_TYPE.Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')which will split "typdef struct { ... } TypedefName"declarations.Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]')which will:- move the typedefs and #defines above the type check macros- add missing #include "qom/object.h" lines if necessaryReviewed-by: Daniel P. Berrangé <berrange@redhat.com>Reviewed-by: Juan Quintela <quintela@redhat.com>Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>Reviewed-by: Juan Quintela <quintela@redhat.com>Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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nrf51: Fix last GPIO CNF addressNRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the lastvalid CNF register: it's referring to the last byte of the last validCNF register.This hasn
nrf51: Fix last GPIO CNF addressNRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the lastvalid CNF register: it's referring to the last byte of the last validCNF register.This hasn't been a problem up to now, as current implementation inmemory.c turns an unaligned 4-byte read from 0x77f to a single byte readand the qtest only looks at the least-significant byte of the register.But when running with patches which fix unaligned accesses in memory.c,the qtest breaks.Considering NRF51 doesn't support unaligned accesses, the simplest fixis to actually set NRF51_GPIO_REG_CNF_END to the start of the last validCNF register: 0x77c.Now, qtests work with or without the unaligned access patches.Reviewed-by: Cédric Le Goater <clg@kaod.org>Tested-by: Cédric Le Goater <clg@kaod.org>Reviewed-by: Joel Stanley <joel@jms.id.au>Signed-off-by: Cameron Esfahani <dirty@apple.com>Message-id: 51b427f06838622da783d38ba56e3630d6d85c60.1586925392.git.dirty@apple.comReviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC.(Note that the ast2400 controller only goes up to group AB).A se
hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC.(Note that the ast2400 controller only goes up to group AB).A set has four groups (except set AC which only has one) and isreferred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB).Each set is accessed and controlled by a bank of 14 registers.These registers operate on a per pin level where each bit in the registercorresponds to a pin, except for the command source registers. The commandsource registers operate on a per group level where bits 24, 16, 8 and 0correspond to each group in the set. eg. registers for set ABCD: |D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs |31...24|23...16|15....8|7.....0| <- bit positionNote that there are a couple of groups that only have 4 pins.There are two ways that this model deviates from the behaviour of theactual controller:(1) The only control source driving the GPIO pins in the model is the ARMmodel (as there currently aren't models for the LPC or Coprocessor).(2) None of the registers in the model are reset tolerant (needsintegration with the watchdog).Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>Tested-by: Andrew Jeffery <andrew@aj.id.au>Reviewed-by: Cédric Le Goater <clg@kaod.org>Signed-off-by: Cédric Le Goater <clg@kaod.org>Message-id: 20190904070506.1052-2-clg@kaod.org[clg: fixed missing header files made use of HWADDR_PRIx to fix compilation on windows ]Signed-off-by: Cédric Le Goater <clg@kaod.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
include: Make headers more self-containedBack in 2016, we discussed[1] rules for headers, and these weregenerally liked:1. Have a carefully curated header that's included everywhere first. We
include: Make headers more self-containedBack in 2016, we discussed[1] rules for headers, and these weregenerally liked:1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h.2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header.3. Cyclic inclusion is forbidden.This patch gets include/ closer to obeying 2.It's actually extracted from my "[RFC] Baby steps towards sanerheaders" series[2], which demonstrates a possible path towardschecking 2 automatically. It passes the RFC test there.[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com> https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.htmlSigned-off-by: Markus Armbruster <armbru@redhat.com>Reviewed-by: Alistair Francis <alistair.francis@wdc.com>Message-Id: <20190812052359.30071-2-armbru@redhat.com>Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheralThis adds a model of the nRF51 GPIO peripheral.Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdfThe nRF51 series microcontrol
hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheralThis adds a model of the nRF51 GPIO peripheral.Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdfThe nRF51 series microcontrollers support up to 32 GPIO pins in various configurations.The pins can be used as input pins with pull-ups or pull-down.Furthermore, three different output driver modes per level areavailable (disconnected, standard, high-current).The GPIO-Peripheral has a mechanism for detecting level changes which isnot featured in this model.Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de>Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>Message-id: 20190103091119.9367-6-stefanha@redhat.comSigned-off-by: Peter Maydell <peter.maydell@linaro.org>
bcm2835_gpio: add bcm2835 gpio controllerThis adds the BCM2835 GPIO controller.It currently implements:- The 54 GPIOs as outputs (qemu_irq)- The SD controller selection via alternate function o
bcm2835_gpio: add bcm2835 gpio controllerThis adds the BCM2835 GPIO controller.It currently implements:- The 54 GPIOs as outputs (qemu_irq)- The SD controller selection via alternate function of GPIOs 48-53Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.orgMessage-id: 20170224164021.9066-4-clement.deschamps@antfield.frReviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Clean up ill-advised or unusual header guardsCleaned up with scripts/clean-header-guards.pl.Signed-off-by: Markus Armbruster <armbru@redhat.com>Reviewed-by: Richard Henderson <rth@twiddle.net>
Use #include "..." for our own headers, <...> for othersTracked down with an ugly, brittle and probably buggy Perl script.Also move includes converted to <...> up so they get included beforeours
Use #include "..." for our own headers, <...> for othersTracked down with an ugly, brittle and probably buggy Perl script.Also move includes converted to <...> up so they get included beforeours where that's obviously okay.Signed-off-by: Markus Armbruster <armbru@redhat.com>Reviewed-by: Eric Blake <eblake@redhat.com>Tested-by: Eric Blake <eblake@redhat.com>Reviewed-by: Richard Henderson <rth@twiddle.net>
i.MX: add support for lower and upper interrupt in GPIO.The i.MX6 GPIO device supports 2 interrupts instead of one.* 1 for the lower 16 GPIOs.* 1 for the upper 16 GPIOs.i.MX31 and i.MX25 only
i.MX: add support for lower and upper interrupt in GPIO.The i.MX6 GPIO device supports 2 interrupts instead of one.* 1 for the lower 16 GPIOs.* 1 for the upper 16 GPIOs.i.MX31 and i.MX25 only support 1 interrupt for the 32 GPIOs.So we add a property to turn the behavior on when required.Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>Message-id: 1447497668-1603-1-git-send-email-jcd@tribudubois.netSigned-off-by: Peter Maydell <peter.maydell@linaro.org>
i.MX: Add GPIO deviceSigned-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>Message-id: 5ea3b0021e47cf7f7d883a7edbabee44980f3df7.14
i.MX: Add GPIO deviceSigned-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>Message-id: 5ea3b0021e47cf7f7d883a7edbabee44980f3df7.1441828793.git.jcd@tribudubois.netSigned-off-by: Peter Maydell <peter.maydell@linaro.org>
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