1 /* 2 * Texas Instruments OMAP processors. 3 * 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_OMAP_H 21 #define HW_ARM_OMAP_H 22 23 #include "exec/memory.h" 24 #include "hw/input/tsc2xxx.h" 25 #include "target/arm/cpu-qom.h" 26 #include "qemu/log.h" 27 #include "qom/object.h" 28 29 # define OMAP_EMIFS_BASE 0x00000000 30 # define OMAP2_Q0_BASE 0x00000000 31 # define OMAP_CS0_BASE 0x00000000 32 # define OMAP_CS1_BASE 0x04000000 33 # define OMAP_CS2_BASE 0x08000000 34 # define OMAP_CS3_BASE 0x0c000000 35 # define OMAP_EMIFF_BASE 0x10000000 36 # define OMAP_IMIF_BASE 0x20000000 37 # define OMAP_LOCALBUS_BASE 0x30000000 38 # define OMAP2_Q1_BASE 0x40000000 39 # define OMAP2_L4_BASE 0x48000000 40 # define OMAP2_SRAM_BASE 0x40200000 41 # define OMAP2_L3_BASE 0x68000000 42 # define OMAP2_Q2_BASE 0x80000000 43 # define OMAP2_Q3_BASE 0xc0000000 44 # define OMAP_MPUI_BASE 0xe1000000 45 46 # define OMAP730_SRAM_SIZE 0x00032000 47 # define OMAP15XX_SRAM_SIZE 0x00030000 48 # define OMAP16XX_SRAM_SIZE 0x00004000 49 # define OMAP1611_SRAM_SIZE 0x0003e800 50 # define OMAP242X_SRAM_SIZE 0x000a0000 51 # define OMAP243X_SRAM_SIZE 0x00010000 52 # define OMAP_CS0_SIZE 0x04000000 53 # define OMAP_CS1_SIZE 0x04000000 54 # define OMAP_CS2_SIZE 0x04000000 55 # define OMAP_CS3_SIZE 0x04000000 56 57 /* omap_clk.c */ 58 struct omap_mpu_state_s; 59 typedef struct clk *omap_clk; 60 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 61 void omap_clk_init(struct omap_mpu_state_s *mpu); 62 void omap_clk_adduser(struct clk *clk, qemu_irq user); 63 void omap_clk_get(omap_clk clk); 64 void omap_clk_put(omap_clk clk); 65 void omap_clk_onoff(omap_clk clk, int on); 66 void omap_clk_canidle(omap_clk clk, int can); 67 void omap_clk_setrate(omap_clk clk, int divide, int multiply); 68 int64_t omap_clk_getrate(omap_clk clk); 69 void omap_clk_reparent(omap_clk clk, omap_clk parent); 70 71 /* omap_intc.c */ 72 #define TYPE_OMAP_INTC "common-omap-intc" 73 typedef struct omap_intr_handler_s omap_intr_handler; 74 #define OMAP_INTC(obj) \ 75 OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC) 76 77 78 /* 79 * TODO: Ideally we should have a clock framework that 80 * let us wire these clocks up with QOM properties or links. 81 * 82 * qdev should support a generic means of defining a 'port' with 83 * an arbitrary interface for connecting two devices. Then we 84 * could reframe the omap clock API in terms of clock ports, 85 * and get some type safety. For now the best qdev provides is 86 * passing an arbitrary pointer. 87 * (It's not possible to pass in the string which is the clock 88 * name, because this device does not have the necessary information 89 * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 90 * translation.) 91 */ 92 void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); 93 void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); 94 95 /* omap_i2c.c */ 96 #define TYPE_OMAP_I2C "omap_i2c" 97 typedef struct OMAPI2CState OMAPI2CState; 98 #define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C) 99 100 101 /* TODO: clock framework (see above) */ 102 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 103 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 104 105 /* omap_gpio.c */ 106 #define TYPE_OMAP1_GPIO "omap-gpio" 107 #define OMAP1_GPIO(obj) \ 108 OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) 109 110 #define TYPE_OMAP2_GPIO "omap2-gpio" 111 #define OMAP2_GPIO(obj) \ 112 OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) 113 114 typedef struct omap_gpif_s omap_gpif; 115 typedef struct omap2_gpif_s omap2_gpif; 116 117 /* TODO: clock framework (see above) */ 118 void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk); 119 120 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk); 121 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk); 122 123 /* OMAP2 l4 Interconnect */ 124 struct omap_l4_s; 125 struct omap_l4_region_s { 126 hwaddr offset; 127 size_t size; 128 int access; 129 }; 130 struct omap_l4_agent_info_s { 131 int ta; 132 int region; 133 int regions; 134 int ta_region; 135 }; 136 struct omap_target_agent_s { 137 MemoryRegion iomem; 138 struct omap_l4_s *bus; 139 int regions; 140 const struct omap_l4_region_s *start; 141 hwaddr base; 142 uint32_t component; 143 uint32_t control; 144 uint32_t status; 145 }; 146 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 147 hwaddr base, int ta_num); 148 149 struct omap_target_agent_s; 150 struct omap_target_agent_s *omap_l4ta_get( 151 struct omap_l4_s *bus, 152 const struct omap_l4_region_s *regions, 153 const struct omap_l4_agent_info_s *agents, 154 int cs); 155 hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 156 int region, MemoryRegion *mr); 157 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 158 int region); 159 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 160 int region); 161 162 /* OMAP2 SDRAM controller */ 163 struct omap_sdrc_s; 164 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 165 hwaddr base); 166 void omap_sdrc_reset(struct omap_sdrc_s *s); 167 168 /* OMAP2 general purpose memory controller */ 169 struct omap_gpmc_s; 170 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 171 hwaddr base, 172 qemu_irq irq, qemu_irq drq); 173 void omap_gpmc_reset(struct omap_gpmc_s *s); 174 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 175 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 176 177 /* 178 * Common IRQ numbers for level 1 interrupt handler 179 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 180 */ 181 # define OMAP_INT_CAMERA 1 182 # define OMAP_INT_FIQ 3 183 # define OMAP_INT_RTDX 6 184 # define OMAP_INT_DSP_MMU_ABORT 7 185 # define OMAP_INT_HOST 8 186 # define OMAP_INT_ABORT 9 187 # define OMAP_INT_BRIDGE_PRIV 13 188 # define OMAP_INT_GPIO_BANK1 14 189 # define OMAP_INT_UART3 15 190 # define OMAP_INT_TIMER3 16 191 # define OMAP_INT_DMA_CH0_6 19 192 # define OMAP_INT_DMA_CH1_7 20 193 # define OMAP_INT_DMA_CH2_8 21 194 # define OMAP_INT_DMA_CH3 22 195 # define OMAP_INT_DMA_CH4 23 196 # define OMAP_INT_DMA_CH5 24 197 # define OMAP_INT_DMA_LCD 25 198 # define OMAP_INT_TIMER1 26 199 # define OMAP_INT_WD_TIMER 27 200 # define OMAP_INT_BRIDGE_PUB 28 201 # define OMAP_INT_TIMER2 30 202 # define OMAP_INT_LCD_CTRL 31 203 204 /* 205 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 206 */ 207 # define OMAP_INT_15XX_IH2_IRQ 0 208 # define OMAP_INT_15XX_LB_MMU 17 209 # define OMAP_INT_15XX_LOCAL_BUS 29 210 211 /* 212 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 213 */ 214 # define OMAP_INT_1510_SPI_TX 4 215 # define OMAP_INT_1510_SPI_RX 5 216 # define OMAP_INT_1510_DSP_MAILBOX1 10 217 # define OMAP_INT_1510_DSP_MAILBOX2 11 218 219 /* 220 * OMAP-310 specific IRQ numbers for level 1 interrupt handler 221 */ 222 # define OMAP_INT_310_McBSP2_TX 4 223 # define OMAP_INT_310_McBSP2_RX 5 224 # define OMAP_INT_310_HSB_MAILBOX1 12 225 # define OMAP_INT_310_HSAB_MMU 18 226 227 /* 228 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 229 */ 230 # define OMAP_INT_1610_IH2_IRQ 0 231 # define OMAP_INT_1610_IH2_FIQ 2 232 # define OMAP_INT_1610_McBSP2_TX 4 233 # define OMAP_INT_1610_McBSP2_RX 5 234 # define OMAP_INT_1610_DSP_MAILBOX1 10 235 # define OMAP_INT_1610_DSP_MAILBOX2 11 236 # define OMAP_INT_1610_LCD_LINE 12 237 # define OMAP_INT_1610_GPTIMER1 17 238 # define OMAP_INT_1610_GPTIMER2 18 239 # define OMAP_INT_1610_SSR_FIFO_0 29 240 241 /* 242 * OMAP-730 specific IRQ numbers for level 1 interrupt handler 243 */ 244 # define OMAP_INT_730_IH2_FIQ 0 245 # define OMAP_INT_730_IH2_IRQ 1 246 # define OMAP_INT_730_USB_NON_ISO 2 247 # define OMAP_INT_730_USB_ISO 3 248 # define OMAP_INT_730_ICR 4 249 # define OMAP_INT_730_EAC 5 250 # define OMAP_INT_730_GPIO_BANK1 6 251 # define OMAP_INT_730_GPIO_BANK2 7 252 # define OMAP_INT_730_GPIO_BANK3 8 253 # define OMAP_INT_730_McBSP2TX 10 254 # define OMAP_INT_730_McBSP2RX 11 255 # define OMAP_INT_730_McBSP2RX_OVF 12 256 # define OMAP_INT_730_LCD_LINE 14 257 # define OMAP_INT_730_GSM_PROTECT 15 258 # define OMAP_INT_730_TIMER3 16 259 # define OMAP_INT_730_GPIO_BANK5 17 260 # define OMAP_INT_730_GPIO_BANK6 18 261 # define OMAP_INT_730_SPGIO_WR 29 262 263 /* 264 * Common IRQ numbers for level 2 interrupt handler 265 */ 266 # define OMAP_INT_KEYBOARD 1 267 # define OMAP_INT_uWireTX 2 268 # define OMAP_INT_uWireRX 3 269 # define OMAP_INT_I2C 4 270 # define OMAP_INT_MPUIO 5 271 # define OMAP_INT_USB_HHC_1 6 272 # define OMAP_INT_McBSP3TX 10 273 # define OMAP_INT_McBSP3RX 11 274 # define OMAP_INT_McBSP1TX 12 275 # define OMAP_INT_McBSP1RX 13 276 # define OMAP_INT_UART1 14 277 # define OMAP_INT_UART2 15 278 # define OMAP_INT_USB_W2FC 20 279 # define OMAP_INT_1WIRE 21 280 # define OMAP_INT_OS_TIMER 22 281 # define OMAP_INT_OQN 23 282 # define OMAP_INT_GAUGE_32K 24 283 # define OMAP_INT_RTC_TIMER 25 284 # define OMAP_INT_RTC_ALARM 26 285 # define OMAP_INT_DSP_MMU 28 286 287 /* 288 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 289 */ 290 # define OMAP_INT_1510_BT_MCSI1TX 16 291 # define OMAP_INT_1510_BT_MCSI1RX 17 292 # define OMAP_INT_1510_SoSSI_MATCH 19 293 # define OMAP_INT_1510_MEM_STICK 27 294 # define OMAP_INT_1510_COM_SPI_RO 31 295 296 /* 297 * OMAP-310 specific IRQ numbers for level 2 interrupt handler 298 */ 299 # define OMAP_INT_310_FAC 0 300 # define OMAP_INT_310_USB_HHC_2 7 301 # define OMAP_INT_310_MCSI1_FE 16 302 # define OMAP_INT_310_MCSI2_FE 17 303 # define OMAP_INT_310_USB_W2FC_ISO 29 304 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 305 # define OMAP_INT_310_McBSP2RX_OF 31 306 307 /* 308 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 309 */ 310 # define OMAP_INT_1610_FAC 0 311 # define OMAP_INT_1610_USB_HHC_2 7 312 # define OMAP_INT_1610_USB_OTG 8 313 # define OMAP_INT_1610_SoSSI 9 314 # define OMAP_INT_1610_BT_MCSI1TX 16 315 # define OMAP_INT_1610_BT_MCSI1RX 17 316 # define OMAP_INT_1610_SoSSI_MATCH 19 317 # define OMAP_INT_1610_MEM_STICK 27 318 # define OMAP_INT_1610_McBSP2RX_OF 31 319 # define OMAP_INT_1610_STI 32 320 # define OMAP_INT_1610_STI_WAKEUP 33 321 # define OMAP_INT_1610_GPTIMER3 34 322 # define OMAP_INT_1610_GPTIMER4 35 323 # define OMAP_INT_1610_GPTIMER5 36 324 # define OMAP_INT_1610_GPTIMER6 37 325 # define OMAP_INT_1610_GPTIMER7 38 326 # define OMAP_INT_1610_GPTIMER8 39 327 # define OMAP_INT_1610_GPIO_BANK2 40 328 # define OMAP_INT_1610_GPIO_BANK3 41 329 # define OMAP_INT_1610_MMC2 42 330 # define OMAP_INT_1610_CF 43 331 # define OMAP_INT_1610_WAKE_UP_REQ 46 332 # define OMAP_INT_1610_GPIO_BANK4 48 333 # define OMAP_INT_1610_SPI 49 334 # define OMAP_INT_1610_DMA_CH6 53 335 # define OMAP_INT_1610_DMA_CH7 54 336 # define OMAP_INT_1610_DMA_CH8 55 337 # define OMAP_INT_1610_DMA_CH9 56 338 # define OMAP_INT_1610_DMA_CH10 57 339 # define OMAP_INT_1610_DMA_CH11 58 340 # define OMAP_INT_1610_DMA_CH12 59 341 # define OMAP_INT_1610_DMA_CH13 60 342 # define OMAP_INT_1610_DMA_CH14 61 343 # define OMAP_INT_1610_DMA_CH15 62 344 # define OMAP_INT_1610_NAND 63 345 346 /* 347 * OMAP-730 specific IRQ numbers for level 2 interrupt handler 348 */ 349 # define OMAP_INT_730_HW_ERRORS 0 350 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 351 # define OMAP_INT_730_CFCD 2 352 # define OMAP_INT_730_CFIREQ 3 353 # define OMAP_INT_730_I2C 4 354 # define OMAP_INT_730_PCC 5 355 # define OMAP_INT_730_MPU_EXT_NIRQ 6 356 # define OMAP_INT_730_SPI_100K_1 7 357 # define OMAP_INT_730_SYREN_SPI 8 358 # define OMAP_INT_730_VLYNQ 9 359 # define OMAP_INT_730_GPIO_BANK4 10 360 # define OMAP_INT_730_McBSP1TX 11 361 # define OMAP_INT_730_McBSP1RX 12 362 # define OMAP_INT_730_McBSP1RX_OF 13 363 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 364 # define OMAP_INT_730_UART_MODEM_1 15 365 # define OMAP_INT_730_MCSI 16 366 # define OMAP_INT_730_uWireTX 17 367 # define OMAP_INT_730_uWireRX 18 368 # define OMAP_INT_730_SMC_CD 19 369 # define OMAP_INT_730_SMC_IREQ 20 370 # define OMAP_INT_730_HDQ_1WIRE 21 371 # define OMAP_INT_730_TIMER32K 22 372 # define OMAP_INT_730_MMC_SDIO 23 373 # define OMAP_INT_730_UPLD 24 374 # define OMAP_INT_730_USB_HHC_1 27 375 # define OMAP_INT_730_USB_HHC_2 28 376 # define OMAP_INT_730_USB_GENI 29 377 # define OMAP_INT_730_USB_OTG 30 378 # define OMAP_INT_730_CAMERA_IF 31 379 # define OMAP_INT_730_RNG 32 380 # define OMAP_INT_730_DUAL_MODE_TIMER 33 381 # define OMAP_INT_730_DBB_RF_EN 34 382 # define OMAP_INT_730_MPUIO_KEYPAD 35 383 # define OMAP_INT_730_SHA1_MD5 36 384 # define OMAP_INT_730_SPI_100K_2 37 385 # define OMAP_INT_730_RNG_IDLE 38 386 # define OMAP_INT_730_MPUIO 39 387 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 388 # define OMAP_INT_730_LLPC_OE_FALLING 41 389 # define OMAP_INT_730_LLPC_OE_RISING 42 390 # define OMAP_INT_730_LLPC_VSYNC 43 391 # define OMAP_INT_730_WAKE_UP_REQ 46 392 # define OMAP_INT_730_DMA_CH6 53 393 # define OMAP_INT_730_DMA_CH7 54 394 # define OMAP_INT_730_DMA_CH8 55 395 # define OMAP_INT_730_DMA_CH9 56 396 # define OMAP_INT_730_DMA_CH10 57 397 # define OMAP_INT_730_DMA_CH11 58 398 # define OMAP_INT_730_DMA_CH12 59 399 # define OMAP_INT_730_DMA_CH13 60 400 # define OMAP_INT_730_DMA_CH14 61 401 # define OMAP_INT_730_DMA_CH15 62 402 # define OMAP_INT_730_NAND 63 403 404 /* 405 * OMAP-24xx common IRQ numbers 406 */ 407 # define OMAP_INT_24XX_STI 4 408 # define OMAP_INT_24XX_SYS_NIRQ 7 409 # define OMAP_INT_24XX_L3_IRQ 10 410 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 411 # define OMAP_INT_24XX_SDMA_IRQ0 12 412 # define OMAP_INT_24XX_SDMA_IRQ1 13 413 # define OMAP_INT_24XX_SDMA_IRQ2 14 414 # define OMAP_INT_24XX_SDMA_IRQ3 15 415 # define OMAP_INT_243X_MCBSP2_IRQ 16 416 # define OMAP_INT_243X_MCBSP3_IRQ 17 417 # define OMAP_INT_243X_MCBSP4_IRQ 18 418 # define OMAP_INT_243X_MCBSP5_IRQ 19 419 # define OMAP_INT_24XX_GPMC_IRQ 20 420 # define OMAP_INT_24XX_GUFFAW_IRQ 21 421 # define OMAP_INT_24XX_IVA_IRQ 22 422 # define OMAP_INT_24XX_EAC_IRQ 23 423 # define OMAP_INT_24XX_CAM_IRQ 24 424 # define OMAP_INT_24XX_DSS_IRQ 25 425 # define OMAP_INT_24XX_MAIL_U0_MPU 26 426 # define OMAP_INT_24XX_DSP_UMA 27 427 # define OMAP_INT_24XX_DSP_MMU 28 428 # define OMAP_INT_24XX_GPIO_BANK1 29 429 # define OMAP_INT_24XX_GPIO_BANK2 30 430 # define OMAP_INT_24XX_GPIO_BANK3 31 431 # define OMAP_INT_24XX_GPIO_BANK4 32 432 # define OMAP_INT_243X_GPIO_BANK5 33 433 # define OMAP_INT_24XX_MAIL_U3_MPU 34 434 # define OMAP_INT_24XX_WDT3 35 435 # define OMAP_INT_24XX_WDT4 36 436 # define OMAP_INT_24XX_GPTIMER1 37 437 # define OMAP_INT_24XX_GPTIMER2 38 438 # define OMAP_INT_24XX_GPTIMER3 39 439 # define OMAP_INT_24XX_GPTIMER4 40 440 # define OMAP_INT_24XX_GPTIMER5 41 441 # define OMAP_INT_24XX_GPTIMER6 42 442 # define OMAP_INT_24XX_GPTIMER7 43 443 # define OMAP_INT_24XX_GPTIMER8 44 444 # define OMAP_INT_24XX_GPTIMER9 45 445 # define OMAP_INT_24XX_GPTIMER10 46 446 # define OMAP_INT_24XX_GPTIMER11 47 447 # define OMAP_INT_24XX_GPTIMER12 48 448 # define OMAP_INT_24XX_PKA_IRQ 50 449 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 450 # define OMAP_INT_24XX_RNG_IRQ 52 451 # define OMAP_INT_24XX_MG_IRQ 53 452 # define OMAP_INT_24XX_I2C1_IRQ 56 453 # define OMAP_INT_24XX_I2C2_IRQ 57 454 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 455 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 456 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 457 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 458 # define OMAP_INT_243X_MCBSP1_IRQ 64 459 # define OMAP_INT_24XX_MCSPI1_IRQ 65 460 # define OMAP_INT_24XX_MCSPI2_IRQ 66 461 # define OMAP_INT_24XX_SSI1_IRQ0 67 462 # define OMAP_INT_24XX_SSI1_IRQ1 68 463 # define OMAP_INT_24XX_SSI2_IRQ0 69 464 # define OMAP_INT_24XX_SSI2_IRQ1 70 465 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 466 # define OMAP_INT_24XX_UART1_IRQ 72 467 # define OMAP_INT_24XX_UART2_IRQ 73 468 # define OMAP_INT_24XX_UART3_IRQ 74 469 # define OMAP_INT_24XX_USB_IRQ_GEN 75 470 # define OMAP_INT_24XX_USB_IRQ_NISO 76 471 # define OMAP_INT_24XX_USB_IRQ_ISO 77 472 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 473 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 474 # define OMAP_INT_24XX_USB_IRQ_OTG 80 475 # define OMAP_INT_24XX_VLYNQ_IRQ 81 476 # define OMAP_INT_24XX_MMC_IRQ 83 477 # define OMAP_INT_24XX_MS_IRQ 84 478 # define OMAP_INT_24XX_FAC_IRQ 85 479 # define OMAP_INT_24XX_MCSPI3_IRQ 91 480 # define OMAP_INT_243X_HS_USB_MC 92 481 # define OMAP_INT_243X_HS_USB_DMA 93 482 # define OMAP_INT_243X_CARKIT 94 483 # define OMAP_INT_34XX_GPTIMER12 95 484 485 /* omap_dma.c */ 486 enum omap_dma_model { 487 omap_dma_3_0, 488 omap_dma_3_1, 489 omap_dma_3_2, 490 omap_dma_4, 491 }; 492 493 struct soc_dma_s; 494 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 495 MemoryRegion *sysmem, 496 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 497 enum omap_dma_model model); 498 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 499 MemoryRegion *sysmem, 500 struct omap_mpu_state_s *mpu, int fifo, 501 int chans, omap_clk iclk, omap_clk fclk); 502 void omap_dma_reset(struct soc_dma_s *s); 503 504 struct dma_irq_map { 505 int ih; 506 int intr; 507 }; 508 509 /* Only used in OMAP DMA 3.x gigacells */ 510 enum omap_dma_port { 511 emiff = 0, 512 emifs, 513 imif, /* omap16xx: ocp_t1 */ 514 tipb, 515 local, /* omap16xx: ocp_t2 */ 516 tipb_mpui, 517 __omap_dma_port_last, 518 }; 519 520 typedef enum { 521 constant = 0, 522 post_incremented, 523 single_index, 524 double_index, 525 } omap_dma_addressing_t; 526 527 /* Only used in OMAP DMA 3.x gigacells */ 528 struct omap_dma_lcd_channel_s { 529 enum omap_dma_port src; 530 hwaddr src_f1_top; 531 hwaddr src_f1_bottom; 532 hwaddr src_f2_top; 533 hwaddr src_f2_bottom; 534 535 /* Used in OMAP DMA 3.2 gigacell */ 536 unsigned char brust_f1; 537 unsigned char pack_f1; 538 unsigned char data_type_f1; 539 unsigned char brust_f2; 540 unsigned char pack_f2; 541 unsigned char data_type_f2; 542 unsigned char end_prog; 543 unsigned char repeat; 544 unsigned char auto_init; 545 unsigned char priority; 546 unsigned char fs; 547 unsigned char running; 548 unsigned char bs; 549 unsigned char omap_3_1_compatible_disable; 550 unsigned char dst; 551 unsigned char lch_type; 552 int16_t element_index_f1; 553 int16_t element_index_f2; 554 int32_t frame_index_f1; 555 int32_t frame_index_f2; 556 uint16_t elements_f1; 557 uint16_t frames_f1; 558 uint16_t elements_f2; 559 uint16_t frames_f2; 560 omap_dma_addressing_t mode_f1; 561 omap_dma_addressing_t mode_f2; 562 563 /* Destination port is fixed. */ 564 int interrupts; 565 int condition; 566 int dual; 567 568 int current_frame; 569 hwaddr phys_framebuffer[2]; 570 qemu_irq irq; 571 struct omap_mpu_state_s *mpu; 572 } *omap_dma_get_lcdch(struct soc_dma_s *s); 573 574 /* 575 * DMA request numbers for OMAP1 576 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 577 */ 578 # define OMAP_DMA_NO_DEVICE 0 579 # define OMAP_DMA_MCSI1_TX 1 580 # define OMAP_DMA_MCSI1_RX 2 581 # define OMAP_DMA_I2C_RX 3 582 # define OMAP_DMA_I2C_TX 4 583 # define OMAP_DMA_EXT_NDMA_REQ0 5 584 # define OMAP_DMA_EXT_NDMA_REQ1 6 585 # define OMAP_DMA_UWIRE_TX 7 586 # define OMAP_DMA_MCBSP1_TX 8 587 # define OMAP_DMA_MCBSP1_RX 9 588 # define OMAP_DMA_MCBSP3_TX 10 589 # define OMAP_DMA_MCBSP3_RX 11 590 # define OMAP_DMA_UART1_TX 12 591 # define OMAP_DMA_UART1_RX 13 592 # define OMAP_DMA_UART2_TX 14 593 # define OMAP_DMA_UART2_RX 15 594 # define OMAP_DMA_MCBSP2_TX 16 595 # define OMAP_DMA_MCBSP2_RX 17 596 # define OMAP_DMA_UART3_TX 18 597 # define OMAP_DMA_UART3_RX 19 598 # define OMAP_DMA_CAMERA_IF_RX 20 599 # define OMAP_DMA_MMC_TX 21 600 # define OMAP_DMA_MMC_RX 22 601 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 602 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 603 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 604 # define OMAP_DMA_USB_W2FC_RX0 26 605 # define OMAP_DMA_USB_W2FC_RX1 27 606 # define OMAP_DMA_USB_W2FC_RX2 28 607 # define OMAP_DMA_USB_W2FC_TX0 29 608 # define OMAP_DMA_USB_W2FC_TX1 30 609 # define OMAP_DMA_USB_W2FC_TX2 31 610 611 /* These are only for 1610 */ 612 # define OMAP_DMA_CRYPTO_DES_IN 32 613 # define OMAP_DMA_SPI_TX 33 614 # define OMAP_DMA_SPI_RX 34 615 # define OMAP_DMA_CRYPTO_HASH 35 616 # define OMAP_DMA_CCP_ATTN 36 617 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 618 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 619 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 620 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 621 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 622 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 623 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 624 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 625 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 626 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 627 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 628 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 629 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 630 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 631 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 632 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 633 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 634 # define OMAP_DMA_MMC2_TX 54 635 # define OMAP_DMA_MMC2_RX 55 636 # define OMAP_DMA_CRYPTO_DES_OUT 56 637 638 /* 639 * DMA request numbers for the OMAP2 640 */ 641 # define OMAP24XX_DMA_NO_DEVICE 0 642 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 643 # define OMAP24XX_DMA_EXT_DMAREQ0 2 644 # define OMAP24XX_DMA_EXT_DMAREQ1 3 645 # define OMAP24XX_DMA_GPMC 4 646 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 647 # define OMAP24XX_DMA_DSS 6 648 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 649 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 650 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 651 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 652 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 653 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 654 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 655 # define OMAP24XX_DMA_EXT_DMAREQ2 14 656 # define OMAP24XX_DMA_EXT_DMAREQ3 15 657 # define OMAP24XX_DMA_EXT_DMAREQ4 16 658 # define OMAP24XX_DMA_EAC_AC_RD 17 659 # define OMAP24XX_DMA_EAC_AC_WR 18 660 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 661 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 662 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 663 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 664 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 665 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 666 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 667 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 668 # define OMAP24XX_DMA_I2C1_TX 27 669 # define OMAP24XX_DMA_I2C1_RX 28 670 # define OMAP24XX_DMA_I2C2_TX 29 671 # define OMAP24XX_DMA_I2C2_RX 30 672 # define OMAP24XX_DMA_MCBSP1_TX 31 673 # define OMAP24XX_DMA_MCBSP1_RX 32 674 # define OMAP24XX_DMA_MCBSP2_TX 33 675 # define OMAP24XX_DMA_MCBSP2_RX 34 676 # define OMAP24XX_DMA_SPI1_TX0 35 677 # define OMAP24XX_DMA_SPI1_RX0 36 678 # define OMAP24XX_DMA_SPI1_TX1 37 679 # define OMAP24XX_DMA_SPI1_RX1 38 680 # define OMAP24XX_DMA_SPI1_TX2 39 681 # define OMAP24XX_DMA_SPI1_RX2 40 682 # define OMAP24XX_DMA_SPI1_TX3 41 683 # define OMAP24XX_DMA_SPI1_RX3 42 684 # define OMAP24XX_DMA_SPI2_TX0 43 685 # define OMAP24XX_DMA_SPI2_RX0 44 686 # define OMAP24XX_DMA_SPI2_TX1 45 687 # define OMAP24XX_DMA_SPI2_RX1 46 688 689 # define OMAP24XX_DMA_UART1_TX 49 690 # define OMAP24XX_DMA_UART1_RX 50 691 # define OMAP24XX_DMA_UART2_TX 51 692 # define OMAP24XX_DMA_UART2_RX 52 693 # define OMAP24XX_DMA_UART3_TX 53 694 # define OMAP24XX_DMA_UART3_RX 54 695 # define OMAP24XX_DMA_USB_W2FC_TX0 55 696 # define OMAP24XX_DMA_USB_W2FC_RX0 56 697 # define OMAP24XX_DMA_USB_W2FC_TX1 57 698 # define OMAP24XX_DMA_USB_W2FC_RX1 58 699 # define OMAP24XX_DMA_USB_W2FC_TX2 59 700 # define OMAP24XX_DMA_USB_W2FC_RX2 60 701 # define OMAP24XX_DMA_MMC1_TX 61 702 # define OMAP24XX_DMA_MMC1_RX 62 703 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 704 # define OMAP24XX_DMA_EXT_DMAREQ5 64 705 706 /* omap[123].c */ 707 /* OMAP2 gp timer */ 708 struct omap_gp_timer_s; 709 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 710 qemu_irq irq, omap_clk fclk, omap_clk iclk); 711 void omap_gp_timer_reset(struct omap_gp_timer_s *s); 712 713 /* OMAP2 sysctimer */ 714 struct omap_synctimer_s; 715 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 716 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 717 void omap_synctimer_reset(struct omap_synctimer_s *s); 718 719 struct omap_uart_s; 720 struct omap_uart_s *omap_uart_init(hwaddr base, 721 qemu_irq irq, omap_clk fclk, omap_clk iclk, 722 qemu_irq txdma, qemu_irq rxdma, 723 const char *label, Chardev *chr); 724 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 725 struct omap_target_agent_s *ta, 726 qemu_irq irq, omap_clk fclk, omap_clk iclk, 727 qemu_irq txdma, qemu_irq rxdma, 728 const char *label, Chardev *chr); 729 void omap_uart_reset(struct omap_uart_s *s); 730 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); 731 732 struct omap_mpuio_s; 733 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 734 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 735 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 736 737 struct omap_uwire_s; 738 void omap_uwire_attach(struct omap_uwire_s *s, 739 uWireSlave *slave, int chipselect); 740 741 /* OMAP2 spi */ 742 struct omap_mcspi_s; 743 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 744 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 745 void omap_mcspi_attach(struct omap_mcspi_s *s, 746 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 747 int chipselect); 748 void omap_mcspi_reset(struct omap_mcspi_s *s); 749 750 struct I2SCodec { 751 void *opaque; 752 753 /* The CPU can call this if it is generating the clock signal on the 754 * i2s port. The CODEC can ignore it if it is set up as a clock 755 * master and generates its own clock. */ 756 void (*set_rate)(void *opaque, int in, int out); 757 758 void (*tx_swallow)(void *opaque); 759 qemu_irq rx_swallow; 760 qemu_irq tx_start; 761 762 int tx_rate; 763 int cts; 764 int rx_rate; 765 int rts; 766 767 struct i2s_fifo_s { 768 uint8_t *fifo; 769 int len; 770 int start; 771 int size; 772 } in, out; 773 }; 774 struct omap_mcbsp_s; 775 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 776 777 void omap_tap_init(struct omap_target_agent_s *ta, 778 struct omap_mpu_state_s *mpu); 779 780 /* omap_lcdc.c */ 781 struct omap_lcd_panel_s; 782 void omap_lcdc_reset(struct omap_lcd_panel_s *s); 783 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 784 hwaddr base, 785 qemu_irq irq, 786 struct omap_dma_lcd_channel_s *dma, 787 omap_clk clk); 788 789 /* omap_dss.c */ 790 struct rfbi_chip_s { 791 void *opaque; 792 void (*write)(void *opaque, int dc, uint16_t value); 793 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 794 uint16_t (*read)(void *opaque, int dc); 795 }; 796 struct omap_dss_s; 797 void omap_dss_reset(struct omap_dss_s *s); 798 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 799 MemoryRegion *sysmem, 800 hwaddr l3_base, 801 qemu_irq irq, qemu_irq drq, 802 omap_clk fck1, omap_clk fck2, omap_clk ck54m, 803 omap_clk ick1, omap_clk ick2); 804 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 805 806 /* omap_mmc.c */ 807 struct omap_mmc_s; 808 struct omap_mmc_s *omap_mmc_init(hwaddr base, 809 MemoryRegion *sysmem, 810 BlockBackend *blk, 811 qemu_irq irq, qemu_irq dma[], omap_clk clk); 812 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 813 BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 814 omap_clk fclk, omap_clk iclk); 815 void omap_mmc_reset(struct omap_mmc_s *s); 816 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 817 void omap_mmc_enable(struct omap_mmc_s *s, int enable); 818 819 /* omap_i2c.c */ 820 I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 821 822 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 823 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 824 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 825 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 826 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 827 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 828 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 829 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 830 # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 831 832 # define cpu_is_omap15xx(cpu) \ 833 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 834 # define cpu_is_omap16xx(cpu) \ 835 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 836 # define cpu_is_omap24xx(cpu) \ 837 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 838 839 # define cpu_class_omap1(cpu) \ 840 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 841 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 842 # define cpu_class_omap3(cpu) \ 843 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 844 845 struct omap_mpu_state_s { 846 enum omap_mpu_model { 847 omap310, 848 omap1510, 849 omap1610, 850 omap1710, 851 omap2410, 852 omap2420, 853 omap2422, 854 omap2423, 855 omap2430, 856 omap3430, 857 omap3630, 858 } mpu_model; 859 860 ARMCPU *cpu; 861 862 qemu_irq *drq; 863 864 qemu_irq wakeup; 865 866 MemoryRegion ulpd_pm_iomem; 867 MemoryRegion pin_cfg_iomem; 868 MemoryRegion id_iomem; 869 MemoryRegion id_iomem_e18; 870 MemoryRegion id_iomem_ed4; 871 MemoryRegion id_iomem_e20; 872 MemoryRegion mpui_iomem; 873 MemoryRegion tcmi_iomem; 874 MemoryRegion clkm_iomem; 875 MemoryRegion clkdsp_iomem; 876 MemoryRegion mpui_io_iomem; 877 MemoryRegion tap_iomem; 878 MemoryRegion imif_ram; 879 MemoryRegion sram; 880 881 struct omap_dma_port_if_s { 882 uint32_t (*read[3])(struct omap_mpu_state_s *s, 883 hwaddr offset); 884 void (*write[3])(struct omap_mpu_state_s *s, 885 hwaddr offset, uint32_t value); 886 int (*addr_valid)(struct omap_mpu_state_s *s, 887 hwaddr addr); 888 } port[__omap_dma_port_last]; 889 890 uint64_t sdram_size; 891 unsigned long sram_size; 892 893 /* MPUI-TIPB peripherals */ 894 struct omap_uart_s *uart[3]; 895 896 DeviceState *gpio; 897 898 struct omap_mcbsp_s *mcbsp1; 899 struct omap_mcbsp_s *mcbsp3; 900 901 /* MPU public TIPB peripherals */ 902 struct omap_32khz_timer_s *os_timer; 903 904 struct omap_mmc_s *mmc; 905 906 struct omap_mpuio_s *mpuio; 907 908 struct omap_uwire_s *microwire; 909 910 struct omap_pwl_s *pwl; 911 struct omap_pwt_s *pwt; 912 DeviceState *i2c[2]; 913 914 struct omap_rtc_s *rtc; 915 916 struct omap_mcbsp_s *mcbsp2; 917 918 struct omap_lpg_s *led[2]; 919 920 /* MPU private TIPB peripherals */ 921 DeviceState *ih[2]; 922 923 struct soc_dma_s *dma; 924 925 struct omap_mpu_timer_s *timer[3]; 926 struct omap_watchdog_timer_s *wdt; 927 928 struct omap_lcd_panel_s *lcd; 929 930 uint32_t ulpd_pm_regs[21]; 931 int64_t ulpd_gauge_start; 932 933 uint32_t func_mux_ctrl[14]; 934 uint32_t comp_mode_ctrl[1]; 935 uint32_t pull_dwn_ctrl[4]; 936 uint32_t gate_inh_ctrl[1]; 937 uint32_t voltage_ctrl[1]; 938 uint32_t test_dbg_ctrl[1]; 939 uint32_t mod_conf_ctrl[1]; 940 int compat1509; 941 942 uint32_t mpui_ctrl; 943 944 struct omap_tipb_bridge_s *private_tipb; 945 struct omap_tipb_bridge_s *public_tipb; 946 947 uint32_t tcmi_regs[17]; 948 949 struct dpll_ctl_s *dpll[3]; 950 951 omap_clk clks; 952 struct { 953 int cold_start; 954 int clocking_scheme; 955 uint16_t arm_ckctl; 956 uint16_t arm_idlect1; 957 uint16_t arm_idlect2; 958 uint16_t arm_ewupct; 959 uint16_t arm_rstct1; 960 uint16_t arm_rstct2; 961 uint16_t arm_ckout1; 962 int dpll1_mode; 963 uint16_t dsp_idlect1; 964 uint16_t dsp_idlect2; 965 uint16_t dsp_rstct2; 966 } clkm; 967 968 /* OMAP2-only peripherals */ 969 struct omap_l4_s *l4; 970 971 struct omap_gp_timer_s *gptimer[12]; 972 struct omap_synctimer_s *synctimer; 973 974 struct omap_prcm_s *prcm; 975 struct omap_sdrc_s *sdrc; 976 struct omap_gpmc_s *gpmc; 977 struct omap_sysctl_s *sysc; 978 979 struct omap_mcspi_s *mcspi[2]; 980 981 struct omap_dss_s *dss; 982 983 struct omap_eac_s *eac; 984 }; 985 986 /* omap1.c */ 987 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 988 const char *core); 989 990 /* omap2.c */ 991 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 992 const char *core); 993 994 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 995 void omap_badwidth_write8(void *opaque, hwaddr addr, 996 uint32_t value); 997 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 998 void omap_badwidth_write16(void *opaque, hwaddr addr, 999 uint32_t value); 1000 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 1001 void omap_badwidth_write32(void *opaque, hwaddr addr, 1002 uint32_t value); 1003 1004 void omap_mpu_wakeup(void *opaque, int irq, int req); 1005 1006 # define OMAP_BAD_REG(paddr) \ 1007 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 1008 __func__, paddr) 1009 # define OMAP_RO_REG(paddr) \ 1010 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 1011 HWADDR_PRIx "\n", \ 1012 __func__, paddr) 1013 1014 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 1015 (Board-specifc tags are not here) */ 1016 #define OMAP_TAG_CLOCK 0x4f01 1017 #define OMAP_TAG_MMC 0x4f02 1018 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 1019 #define OMAP_TAG_USB 0x4f04 1020 #define OMAP_TAG_LCD 0x4f05 1021 #define OMAP_TAG_GPIO_SWITCH 0x4f06 1022 #define OMAP_TAG_UART 0x4f07 1023 #define OMAP_TAG_FBMEM 0x4f08 1024 #define OMAP_TAG_STI_CONSOLE 0x4f09 1025 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 1026 #define OMAP_TAG_PARTITION 0x4f0b 1027 #define OMAP_TAG_TEA5761 0x4f10 1028 #define OMAP_TAG_TMP105 0x4f11 1029 #define OMAP_TAG_BOOT_REASON 0x4f80 1030 #define OMAP_TAG_FLASH_PART_STR 0x4f81 1031 #define OMAP_TAG_VERSION_STR 0x4f82 1032 1033 enum { 1034 OMAP_GPIOSW_TYPE_COVER = 0 << 4, 1035 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 1036 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 1037 }; 1038 1039 #define OMAP_GPIOSW_INVERTED 0x0001 1040 #define OMAP_GPIOSW_OUTPUT 0x0002 1041 1042 # define OMAP_MPUI_REG_MASK 0x000007ff 1043 1044 #endif 1045