1 /* 2 * i.MX FEC/ENET Ethernet Controller emulation. 3 * 4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> 5 * 6 * Based on Coldfire Fast Ethernet Controller emulation. 7 * 8 * Copyright (c) 2007 CodeSourcery. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef IMX_FEC_H 25 #define IMX_FEC_H 26 #include "qom/object.h" 27 28 #define TYPE_IMX_FEC "imx.fec" 29 typedef struct IMXFECState IMXFECState; 30 #define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC) 31 32 #define TYPE_IMX_ENET "imx.enet" 33 34 #include "hw/sysbus.h" 35 #include "net/net.h" 36 37 #define ENET_EIR 1 38 #define ENET_EIMR 2 39 #define ENET_RDAR 4 40 #define ENET_TDAR 5 41 #define ENET_ECR 9 42 #define ENET_MMFR 16 43 #define ENET_MSCR 17 44 #define ENET_MIBC 25 45 #define ENET_RCR 33 46 #define ENET_TCR 49 47 #define ENET_PALR 57 48 #define ENET_PAUR 58 49 #define ENET_OPD 59 50 #define ENET_IAUR 70 51 #define ENET_IALR 71 52 #define ENET_GAUR 72 53 #define ENET_GALR 73 54 #define ENET_TFWR 81 55 #define ENET_FRBR 83 56 #define ENET_FRSR 84 57 #define ENET_TDSR1 89 58 #define ENET_TDSR2 92 59 #define ENET_RDSR 96 60 #define ENET_TDSR 97 61 #define ENET_MRBR 98 62 #define ENET_RSFL 100 63 #define ENET_RSEM 101 64 #define ENET_RAEM 102 65 #define ENET_RAFL 103 66 #define ENET_TSEM 104 67 #define ENET_TAEM 105 68 #define ENET_TAFL 106 69 #define ENET_TIPG 107 70 #define ENET_FTRL 108 71 #define ENET_TACC 112 72 #define ENET_RACC 113 73 #define ENET_TDAR1 121 74 #define ENET_TDAR2 123 75 #define ENET_MIIGSK_CFGR 192 76 #define ENET_MIIGSK_ENR 194 77 #define ENET_ATCR 256 78 #define ENET_ATVR 257 79 #define ENET_ATOFF 258 80 #define ENET_ATPER 259 81 #define ENET_ATCOR 260 82 #define ENET_ATINC 261 83 #define ENET_ATSTMP 262 84 #define ENET_TGSR 385 85 #define ENET_TCSR0 386 86 #define ENET_TCCR0 387 87 #define ENET_TCSR1 388 88 #define ENET_TCCR1 389 89 #define ENET_TCSR2 390 90 #define ENET_TCCR2 391 91 #define ENET_TCSR3 392 92 #define ENET_TCCR3 393 93 #define ENET_MAX 400 94 95 96 /* EIR and EIMR */ 97 #define ENET_INT_HB (1 << 31) 98 #define ENET_INT_BABR (1 << 30) 99 #define ENET_INT_BABT (1 << 29) 100 #define ENET_INT_GRA (1 << 28) 101 #define ENET_INT_TXF (1 << 27) 102 #define ENET_INT_TXB (1 << 26) 103 #define ENET_INT_RXF (1 << 25) 104 #define ENET_INT_RXB (1 << 24) 105 #define ENET_INT_MII (1 << 23) 106 #define ENET_INT_EBERR (1 << 22) 107 #define ENET_INT_LC (1 << 21) 108 #define ENET_INT_RL (1 << 20) 109 #define ENET_INT_UN (1 << 19) 110 #define ENET_INT_PLR (1 << 18) 111 #define ENET_INT_WAKEUP (1 << 17) 112 #define ENET_INT_TS_AVAIL (1 << 16) 113 #define ENET_INT_TS_TIMER (1 << 15) 114 #define ENET_INT_TXF2 (1 << 7) 115 #define ENET_INT_TXB2 (1 << 6) 116 #define ENET_INT_TXF1 (1 << 3) 117 #define ENET_INT_TXB1 (1 << 2) 118 119 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \ 120 ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \ 121 ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \ 122 ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \ 123 ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \ 124 ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \ 125 ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2) 126 127 /* RDAR */ 128 #define ENET_RDAR_RDAR (1 << 24) 129 130 /* TDAR */ 131 #define ENET_TDAR_TDAR (1 << 24) 132 133 /* ECR */ 134 #define ENET_ECR_RESET (1 << 0) 135 #define ENET_ECR_ETHEREN (1 << 1) 136 #define ENET_ECR_MAGICEN (1 << 2) 137 #define ENET_ECR_SLEEP (1 << 3) 138 #define ENET_ECR_EN1588 (1 << 4) 139 #define ENET_ECR_SPEED (1 << 5) 140 #define ENET_ECR_DBGEN (1 << 6) 141 #define ENET_ECR_STOPEN (1 << 7) 142 #define ENET_ECR_DSBWP (1 << 8) 143 144 /* MIBC */ 145 #define ENET_MIBC_MIB_DIS (1 << 31) 146 #define ENET_MIBC_MIB_IDLE (1 << 30) 147 #define ENET_MIBC_MIB_CLEAR (1 << 29) 148 149 /* RCR */ 150 #define ENET_RCR_LOOP (1 << 0) 151 #define ENET_RCR_DRT (1 << 1) 152 #define ENET_RCR_MII_MODE (1 << 2) 153 #define ENET_RCR_PROM (1 << 3) 154 #define ENET_RCR_BC_REJ (1 << 4) 155 #define ENET_RCR_FCE (1 << 5) 156 #define ENET_RCR_RGMII_EN (1 << 6) 157 #define ENET_RCR_RMII_MODE (1 << 8) 158 #define ENET_RCR_RMII_10T (1 << 9) 159 #define ENET_RCR_PADEN (1 << 12) 160 #define ENET_RCR_PAUFWD (1 << 13) 161 #define ENET_RCR_CRCFWD (1 << 14) 162 #define ENET_RCR_CFEN (1 << 15) 163 #define ENET_RCR_MAX_FL_SHIFT (16) 164 #define ENET_RCR_MAX_FL_LENGTH (14) 165 #define ENET_RCR_NLC (1 << 30) 166 #define ENET_RCR_GRS (1 << 31) 167 168 #define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH) 169 170 /* TCR */ 171 #define ENET_TCR_GTS (1 << 0) 172 #define ENET_TCR_FDEN (1 << 2) 173 #define ENET_TCR_TFC_PAUSE (1 << 3) 174 #define ENET_TCR_RFC_PAUSE (1 << 4) 175 #define ENET_TCR_ADDSEL_SHIFT (5) 176 #define ENET_TCR_ADDSEL_LENGTH (3) 177 #define ENET_TCR_CRCFWD (1 << 9) 178 179 /* RDSR */ 180 #define ENET_TWFR_TFWR_SHIFT (0) 181 #define ENET_TWFR_TFWR_LENGTH (6) 182 #define ENET_TWFR_STRFWD (1 << 8) 183 184 #define ENET_RACC_SHIFT16 BIT(7) 185 186 /* Buffer Descriptor. */ 187 typedef struct { 188 uint16_t length; 189 uint16_t flags; 190 uint32_t data; 191 } IMXFECBufDesc; 192 193 #define ENET_BD_R (1 << 15) 194 #define ENET_BD_E (1 << 15) 195 #define ENET_BD_O1 (1 << 14) 196 #define ENET_BD_W (1 << 13) 197 #define ENET_BD_O2 (1 << 12) 198 #define ENET_BD_L (1 << 11) 199 #define ENET_BD_TC (1 << 10) 200 #define ENET_BD_ABC (1 << 9) 201 #define ENET_BD_M (1 << 8) 202 #define ENET_BD_BC (1 << 7) 203 #define ENET_BD_MC (1 << 6) 204 #define ENET_BD_LG (1 << 5) 205 #define ENET_BD_NO (1 << 4) 206 #define ENET_BD_CR (1 << 2) 207 #define ENET_BD_OV (1 << 1) 208 #define ENET_BD_TR (1 << 0) 209 210 typedef struct { 211 uint16_t length; 212 uint16_t flags; 213 uint32_t data; 214 uint16_t status; 215 uint16_t option; 216 uint16_t checksum; 217 uint16_t head_proto; 218 uint32_t last_buffer; 219 uint32_t timestamp; 220 uint32_t reserved[2]; 221 } IMXENETBufDesc; 222 223 #define ENET_BD_ME (1 << 15) 224 #define ENET_BD_TX_INT (1 << 14) 225 #define ENET_BD_TS (1 << 13) 226 #define ENET_BD_PINS (1 << 12) 227 #define ENET_BD_IINS (1 << 11) 228 #define ENET_BD_PE (1 << 10) 229 #define ENET_BD_CE (1 << 9) 230 #define ENET_BD_UC (1 << 8) 231 #define ENET_BD_RX_INT (1 << 7) 232 233 #define ENET_BD_TXE (1 << 15) 234 #define ENET_BD_UE (1 << 13) 235 #define ENET_BD_EE (1 << 12) 236 #define ENET_BD_FE (1 << 11) 237 #define ENET_BD_LCE (1 << 10) 238 #define ENET_BD_OE (1 << 9) 239 #define ENET_BD_TSE (1 << 8) 240 #define ENET_BD_ICE (1 << 5) 241 #define ENET_BD_PCR (1 << 4) 242 #define ENET_BD_VLAN (1 << 2) 243 #define ENET_BD_IPV6 (1 << 1) 244 #define ENET_BD_FRAG (1 << 0) 245 246 #define ENET_BD_BDU (1 << 31) 247 248 #define ENET_TX_RING_NUM 3 249 250 #define FSL_IMX25_FEC_SIZE 0x4000 251 252 struct IMXFECState { 253 /*< private >*/ 254 SysBusDevice parent_obj; 255 256 /*< public >*/ 257 NICState *nic; 258 NICConf conf; 259 qemu_irq irq[2]; 260 MemoryRegion iomem; 261 262 uint32_t regs[ENET_MAX]; 263 uint32_t rx_descriptor; 264 265 uint32_t tx_descriptor[ENET_TX_RING_NUM]; 266 uint32_t tx_ring_num; 267 268 uint32_t phy_status; 269 uint32_t phy_control; 270 uint32_t phy_advertise; 271 uint32_t phy_int; 272 uint32_t phy_int_mask; 273 uint32_t phy_num; 274 275 bool is_fec; 276 277 /* Buffer used to assemble a Tx frame */ 278 uint8_t frame[ENET_MAX_FRAME_SIZE]; 279 }; 280 281 #endif 282