1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #ifndef XICS_H 29 #define XICS_H 30 31 #include "exec/memory.h" 32 #include "hw/qdev-core.h" 33 #include "qom/object.h" 34 35 #define XICS_IPI 0x2 36 #define XICS_BUID 0x1 37 #define XICS_IRQ_BASE (XICS_BUID << 12) 38 39 /* 40 * We currently only support one BUID which is our interrupt base 41 * (the kernel implementation supports more but we don't exploit 42 * that yet) 43 */ 44 typedef struct ICPStateClass ICPStateClass; 45 typedef struct ICPState ICPState; 46 typedef struct PnvICPState PnvICPState; 47 typedef struct ICSStateClass ICSStateClass; 48 typedef struct ICSState ICSState; 49 typedef struct ICSIRQState ICSIRQState; 50 typedef struct XICSFabric XICSFabric; 51 52 #define TYPE_ICP "icp" 53 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 54 55 #define TYPE_PNV_ICP "pnv-icp" 56 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP) 57 58 #define ICP_CLASS(klass) \ 59 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 60 #define ICP_GET_CLASS(obj) \ 61 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 62 63 struct ICPStateClass { 64 DeviceClass parent_class; 65 66 DeviceRealize parent_realize; 67 }; 68 69 struct ICPState { 70 /*< private >*/ 71 DeviceState parent_obj; 72 /*< public >*/ 73 CPUState *cs; 74 ICSState *xirr_owner; 75 uint32_t xirr; 76 uint8_t pending_priority; 77 uint8_t mfrr; 78 qemu_irq output; 79 80 XICSFabric *xics; 81 }; 82 83 #define ICP_PROP_XICS "xics" 84 #define ICP_PROP_CPU "cpu" 85 86 struct PnvICPState { 87 ICPState parent_obj; 88 89 MemoryRegion mmio; 90 uint32_t links[3]; 91 }; 92 93 #define TYPE_ICS "ics" 94 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) 95 96 #define ICS_CLASS(klass) \ 97 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) 98 #define ICS_GET_CLASS(obj) \ 99 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) 100 101 struct ICSStateClass { 102 DeviceClass parent_class; 103 104 DeviceRealize parent_realize; 105 DeviceReset parent_reset; 106 107 void (*reject)(ICSState *s, uint32_t irq); 108 void (*resend)(ICSState *s); 109 }; 110 111 struct ICSState { 112 /*< private >*/ 113 DeviceState parent_obj; 114 /*< public >*/ 115 uint32_t nr_irqs; 116 uint32_t offset; 117 ICSIRQState *irqs; 118 XICSFabric *xics; 119 }; 120 121 #define ICS_PROP_XICS "xics" 122 123 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) 124 { 125 return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs)); 126 } 127 128 struct ICSIRQState { 129 uint32_t server; 130 uint8_t priority; 131 uint8_t saved_priority; 132 #define XICS_STATUS_ASSERTED 0x1 133 #define XICS_STATUS_SENT 0x2 134 #define XICS_STATUS_REJECTED 0x4 135 #define XICS_STATUS_MASKED_PENDING 0x8 136 #define XICS_STATUS_PRESENTED 0x10 137 #define XICS_STATUS_QUEUED 0x20 138 uint8_t status; 139 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ 140 #define XICS_FLAGS_IRQ_LSI 0x1 141 #define XICS_FLAGS_IRQ_MSI 0x2 142 #define XICS_FLAGS_IRQ_MASK 0x3 143 uint8_t flags; 144 }; 145 146 #define TYPE_XICS_FABRIC "xics-fabric" 147 #define XICS_FABRIC(obj) \ 148 INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) 149 typedef struct XICSFabricClass XICSFabricClass; 150 #define XICS_FABRIC_CLASS(klass) \ 151 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC) 152 #define XICS_FABRIC_GET_CLASS(obj) \ 153 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC) 154 155 struct XICSFabricClass { 156 InterfaceClass parent; 157 ICSState *(*ics_get)(XICSFabric *xi, int irq); 158 void (*ics_resend)(XICSFabric *xi); 159 ICPState *(*icp_get)(XICSFabric *xi, int server); 160 }; 161 162 ICPState *xics_icp_get(XICSFabric *xi, int server); 163 164 /* Internal XICS interfaces */ 165 void icp_set_cppr(ICPState *icp, uint8_t cppr); 166 void icp_set_mfrr(ICPState *icp, uint8_t mfrr); 167 uint32_t icp_accept(ICPState *ss); 168 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); 169 void icp_eoi(ICPState *icp, uint32_t xirr); 170 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority); 171 void icp_reset(ICPState *icp); 172 173 void ics_write_xive(ICSState *ics, int nr, int server, 174 uint8_t priority, uint8_t saved_priority); 175 void ics_set_irq(void *opaque, int srcno, int val); 176 177 static inline bool ics_irq_free(ICSState *ics, uint32_t srcno) 178 { 179 return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK); 180 } 181 182 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); 183 void icp_pic_print_info(ICPState *icp, Monitor *mon); 184 void ics_pic_print_info(ICSState *ics, Monitor *mon); 185 186 void ics_resend(ICSState *ics); 187 void icp_resend(ICPState *ss); 188 189 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, 190 Error **errp); 191 void icp_destroy(ICPState *icp); 192 193 /* KVM */ 194 void icp_get_kvm_state(ICPState *icp); 195 int icp_set_kvm_state(ICPState *icp, Error **errp); 196 void icp_synchronize_state(ICPState *icp); 197 void icp_kvm_realize(DeviceState *dev, Error **errp); 198 199 void ics_get_kvm_state(ICSState *ics); 200 int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp); 201 int ics_set_kvm_state(ICSState *ics, Error **errp); 202 void ics_synchronize_state(ICSState *ics); 203 void ics_kvm_set_irq(ICSState *ics, int srcno, int val); 204 205 #endif /* XICS_H */ 206