1 /* 2 * QEMU VMWARE VMXNET3 paravirtual NIC 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Authors: 9 * Dmitry Fleytman <dmitry@daynix.com> 10 * Tamir Shomer <tamirs@daynix.com> 11 * Yan Vugenfirer <yan@daynix.com> 12 * 13 * This work is licensed under the terms of the GNU GPL, version 2. 14 * See the COPYING file in the top-level directory. 15 * 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/hw.h" 20 #include "hw/pci/pci.h" 21 #include "hw/qdev-properties.h" 22 #include "net/tap.h" 23 #include "net/checksum.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu/bswap.h" 26 #include "qemu/module.h" 27 #include "hw/pci/msix.h" 28 #include "hw/pci/msi.h" 29 #include "migration/register.h" 30 #include "migration/vmstate.h" 31 32 #include "vmxnet3.h" 33 #include "vmxnet3_defs.h" 34 #include "vmxnet_debug.h" 35 #include "vmware_utils.h" 36 #include "net_tx_pkt.h" 37 #include "net_rx_pkt.h" 38 #include "qom/object.h" 39 40 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1 41 #define VMXNET3_MSIX_BAR_SIZE 0x2000 42 #define MIN_BUF_SIZE 60 43 44 /* Compatibility flags for migration */ 45 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0 46 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \ 47 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT) 48 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1 49 #define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \ 50 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT) 51 52 #define VMXNET3_EXP_EP_OFFSET (0x48) 53 #define VMXNET3_MSI_OFFSET(s) \ 54 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84) 55 #define VMXNET3_MSIX_OFFSET(s) \ 56 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c) 57 #define VMXNET3_DSN_OFFSET (0x100) 58 59 #define VMXNET3_BAR0_IDX (0) 60 #define VMXNET3_BAR1_IDX (1) 61 #define VMXNET3_MSIX_BAR_IDX (2) 62 63 #define VMXNET3_OFF_MSIX_TABLE (0x000) 64 #define VMXNET3_OFF_MSIX_PBA(s) \ 65 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000) 66 67 /* Link speed in Mbps should be shifted by 16 */ 68 #define VMXNET3_LINK_SPEED (1000 << 16) 69 70 /* Link status: 1 - up, 0 - down. */ 71 #define VMXNET3_LINK_STATUS_UP 0x1 72 73 /* Least significant bit should be set for revision and version */ 74 #define VMXNET3_UPT_REVISION 0x1 75 #define VMXNET3_DEVICE_REVISION 0x1 76 77 /* Number of interrupt vectors for non-MSIx modes */ 78 #define VMXNET3_MAX_NMSIX_INTRS (1) 79 80 /* Macros for rings descriptors access */ 81 #define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \ 82 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 83 84 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \ 85 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value))) 86 87 #define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \ 88 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 89 90 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \ 91 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 92 93 #define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \ 94 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field))) 95 96 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \ 97 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value)) 98 99 #define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \ 100 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 101 102 #define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \ 103 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field))) 104 105 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \ 106 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 107 108 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \ 109 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value)) 110 111 /* Macros for guest driver shared area access */ 112 #define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \ 113 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 114 115 #define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \ 116 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 117 118 #define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \ 119 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val)) 120 121 #define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \ 122 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 123 124 #define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \ 125 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field))) 126 127 #define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \ 128 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l)) 129 130 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag)) 131 132 struct VMXNET3Class { 133 PCIDeviceClass parent_class; 134 DeviceRealize parent_dc_realize; 135 }; 136 typedef struct VMXNET3Class VMXNET3Class; 137 138 #define VMXNET3_DEVICE_CLASS(klass) \ 139 OBJECT_CLASS_CHECK(VMXNET3Class, (klass), TYPE_VMXNET3) 140 #define VMXNET3_DEVICE_GET_CLASS(obj) \ 141 OBJECT_GET_CLASS(VMXNET3Class, (obj), TYPE_VMXNET3) 142 143 static inline void vmxnet3_ring_init(PCIDevice *d, 144 Vmxnet3Ring *ring, 145 hwaddr pa, 146 uint32_t size, 147 uint32_t cell_size, 148 bool zero_region) 149 { 150 ring->pa = pa; 151 ring->size = size; 152 ring->cell_size = cell_size; 153 ring->gen = VMXNET3_INIT_GEN; 154 ring->next = 0; 155 156 if (zero_region) { 157 vmw_shmem_set(d, pa, 0, size * cell_size); 158 } 159 } 160 161 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \ 162 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \ 163 (ring_name), (ridx), \ 164 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next) 165 166 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring) 167 { 168 if (++ring->next >= ring->size) { 169 ring->next = 0; 170 ring->gen ^= 1; 171 } 172 } 173 174 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring) 175 { 176 if (ring->next-- == 0) { 177 ring->next = ring->size - 1; 178 ring->gen ^= 1; 179 } 180 } 181 182 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring) 183 { 184 return ring->pa + ring->next * ring->cell_size; 185 } 186 187 static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 188 void *buff) 189 { 190 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 191 } 192 193 static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring, 194 void *buff) 195 { 196 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size); 197 } 198 199 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring) 200 { 201 return ring->next; 202 } 203 204 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring) 205 { 206 return ring->gen; 207 } 208 209 /* Debug trace-related functions */ 210 static inline void 211 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr) 212 { 213 VMW_PKPRN("TX DESCR: " 214 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 215 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, " 216 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d", 217 descr->addr, descr->len, descr->gen, descr->rsvd, 218 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om, 219 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci); 220 } 221 222 static inline void 223 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr) 224 { 225 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, " 226 "csum_start: %d, csum_offset: %d", 227 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size, 228 vhdr->csum_start, vhdr->csum_offset); 229 } 230 231 static inline void 232 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr) 233 { 234 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, " 235 "dtype: %d, ext1: %d, btype: %d", 236 descr->addr, descr->len, descr->gen, 237 descr->rsvd, descr->dtype, descr->ext1, descr->btype); 238 } 239 240 /* Interrupt management */ 241 242 /* 243 * This function returns sign whether interrupt line is in asserted state 244 * This depends on the type of interrupt used. For INTX interrupt line will 245 * be asserted until explicit deassertion, for MSI(X) interrupt line will 246 * be deasserted automatically due to notification semantics of the MSI(X) 247 * interrupts 248 */ 249 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) 250 { 251 PCIDevice *d = PCI_DEVICE(s); 252 253 if (s->msix_used && msix_enabled(d)) { 254 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx); 255 msix_notify(d, int_idx); 256 return false; 257 } 258 if (msi_enabled(d)) { 259 VMW_IRPRN("Sending MSI notification for vector %u", int_idx); 260 msi_notify(d, int_idx); 261 return false; 262 } 263 264 VMW_IRPRN("Asserting line for interrupt %u", int_idx); 265 pci_irq_assert(d); 266 return true; 267 } 268 269 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) 270 { 271 PCIDevice *d = PCI_DEVICE(s); 272 273 /* 274 * This function should never be called for MSI(X) interrupts 275 * because deassertion never required for message interrupts 276 */ 277 assert(!s->msix_used || !msix_enabled(d)); 278 /* 279 * This function should never be called for MSI(X) interrupts 280 * because deassertion never required for message interrupts 281 */ 282 assert(!msi_enabled(d)); 283 284 VMW_IRPRN("Deasserting line for interrupt %u", lidx); 285 pci_irq_deassert(d); 286 } 287 288 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) 289 { 290 if (!s->interrupt_states[lidx].is_pending && 291 s->interrupt_states[lidx].is_asserted) { 292 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx); 293 _vmxnet3_deassert_interrupt_line(s, lidx); 294 s->interrupt_states[lidx].is_asserted = false; 295 return; 296 } 297 298 if (s->interrupt_states[lidx].is_pending && 299 !s->interrupt_states[lidx].is_masked && 300 !s->interrupt_states[lidx].is_asserted) { 301 VMW_IRPRN("New interrupt line state for index %d is UP", lidx); 302 s->interrupt_states[lidx].is_asserted = 303 _vmxnet3_assert_interrupt_line(s, lidx); 304 s->interrupt_states[lidx].is_pending = false; 305 return; 306 } 307 } 308 309 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx) 310 { 311 PCIDevice *d = PCI_DEVICE(s); 312 s->interrupt_states[lidx].is_pending = true; 313 vmxnet3_update_interrupt_line_state(s, lidx); 314 315 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) { 316 goto do_automask; 317 } 318 319 if (msi_enabled(d) && s->auto_int_masking) { 320 goto do_automask; 321 } 322 323 return; 324 325 do_automask: 326 s->interrupt_states[lidx].is_masked = true; 327 vmxnet3_update_interrupt_line_state(s, lidx); 328 } 329 330 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx) 331 { 332 return s->interrupt_states[lidx].is_asserted; 333 } 334 335 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx) 336 { 337 s->interrupt_states[int_idx].is_pending = false; 338 if (s->auto_int_masking) { 339 s->interrupt_states[int_idx].is_masked = true; 340 } 341 vmxnet3_update_interrupt_line_state(s, int_idx); 342 } 343 344 static void 345 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked) 346 { 347 s->interrupt_states[lidx].is_masked = is_masked; 348 vmxnet3_update_interrupt_line_state(s, lidx); 349 } 350 351 static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem) 352 { 353 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC); 354 } 355 356 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF) 357 #define VMXNET3_MAKE_BYTE(byte_num, val) \ 358 (((uint32_t)((val) & 0xFF)) << (byte_num)*8) 359 360 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l) 361 { 362 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0); 363 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1); 364 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2); 365 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3); 366 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0); 367 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1); 368 369 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 370 371 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 372 } 373 374 static uint64_t vmxnet3_get_mac_low(MACAddr *addr) 375 { 376 return VMXNET3_MAKE_BYTE(0, addr->a[0]) | 377 VMXNET3_MAKE_BYTE(1, addr->a[1]) | 378 VMXNET3_MAKE_BYTE(2, addr->a[2]) | 379 VMXNET3_MAKE_BYTE(3, addr->a[3]); 380 } 381 382 static uint64_t vmxnet3_get_mac_high(MACAddr *addr) 383 { 384 return VMXNET3_MAKE_BYTE(0, addr->a[4]) | 385 VMXNET3_MAKE_BYTE(1, addr->a[5]); 386 } 387 388 static void 389 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx) 390 { 391 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring); 392 } 393 394 static inline void 395 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx) 396 { 397 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]); 398 } 399 400 static inline void 401 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx) 402 { 403 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring); 404 } 405 406 static void 407 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx) 408 { 409 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring); 410 } 411 412 static void 413 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx) 414 { 415 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring); 416 } 417 418 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx) 419 { 420 struct Vmxnet3_TxCompDesc txcq_descr; 421 PCIDevice *d = PCI_DEVICE(s); 422 423 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring); 424 425 memset(&txcq_descr, 0, sizeof(txcq_descr)); 426 txcq_descr.txdIdx = tx_ridx; 427 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring); 428 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1); 429 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2); 430 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr); 431 432 /* Flush changes in TX descriptor before changing the counter value */ 433 smp_wmb(); 434 435 vmxnet3_inc_tx_completion_counter(s, qidx); 436 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx); 437 } 438 439 static bool 440 vmxnet3_setup_tx_offloads(VMXNET3State *s) 441 { 442 switch (s->offload_mode) { 443 case VMXNET3_OM_NONE: 444 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0); 445 break; 446 447 case VMXNET3_OM_CSUM: 448 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0); 449 VMW_PKPRN("L4 CSO requested\n"); 450 break; 451 452 case VMXNET3_OM_TSO: 453 net_tx_pkt_build_vheader(s->tx_pkt, true, true, 454 s->cso_or_gso_size); 455 net_tx_pkt_update_ip_checksums(s->tx_pkt); 456 VMW_PKPRN("GSO offload requested."); 457 break; 458 459 default: 460 g_assert_not_reached(); 461 return false; 462 } 463 464 return true; 465 } 466 467 static void 468 vmxnet3_tx_retrieve_metadata(VMXNET3State *s, 469 const struct Vmxnet3_TxDesc *txd) 470 { 471 s->offload_mode = txd->om; 472 s->cso_or_gso_size = txd->msscof; 473 s->tci = txd->tci; 474 s->needs_vlan = txd->ti; 475 } 476 477 typedef enum { 478 VMXNET3_PKT_STATUS_OK, 479 VMXNET3_PKT_STATUS_ERROR, 480 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */ 481 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */ 482 } Vmxnet3PktStatus; 483 484 static void 485 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx, 486 Vmxnet3PktStatus status) 487 { 488 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt); 489 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats; 490 491 switch (status) { 492 case VMXNET3_PKT_STATUS_OK: 493 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) { 494 case ETH_PKT_BCAST: 495 stats->bcastPktsTxOK++; 496 stats->bcastBytesTxOK += tot_len; 497 break; 498 case ETH_PKT_MCAST: 499 stats->mcastPktsTxOK++; 500 stats->mcastBytesTxOK += tot_len; 501 break; 502 case ETH_PKT_UCAST: 503 stats->ucastPktsTxOK++; 504 stats->ucastBytesTxOK += tot_len; 505 break; 506 default: 507 g_assert_not_reached(); 508 } 509 510 if (s->offload_mode == VMXNET3_OM_TSO) { 511 /* 512 * According to VMWARE headers this statistic is a number 513 * of packets after segmentation but since we don't have 514 * this information in QEMU model, the best we can do is to 515 * provide number of non-segmented packets 516 */ 517 stats->TSOPktsTxOK++; 518 stats->TSOBytesTxOK += tot_len; 519 } 520 break; 521 522 case VMXNET3_PKT_STATUS_DISCARD: 523 stats->pktsTxDiscard++; 524 break; 525 526 case VMXNET3_PKT_STATUS_ERROR: 527 stats->pktsTxError++; 528 break; 529 530 default: 531 g_assert_not_reached(); 532 } 533 } 534 535 static void 536 vmxnet3_on_rx_done_update_stats(VMXNET3State *s, 537 int qidx, 538 Vmxnet3PktStatus status) 539 { 540 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats; 541 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt); 542 543 switch (status) { 544 case VMXNET3_PKT_STATUS_OUT_OF_BUF: 545 stats->pktsRxOutOfBuf++; 546 break; 547 548 case VMXNET3_PKT_STATUS_ERROR: 549 stats->pktsRxError++; 550 break; 551 case VMXNET3_PKT_STATUS_OK: 552 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 553 case ETH_PKT_BCAST: 554 stats->bcastPktsRxOK++; 555 stats->bcastBytesRxOK += tot_len; 556 break; 557 case ETH_PKT_MCAST: 558 stats->mcastPktsRxOK++; 559 stats->mcastBytesRxOK += tot_len; 560 break; 561 case ETH_PKT_UCAST: 562 stats->ucastPktsRxOK++; 563 stats->ucastBytesRxOK += tot_len; 564 break; 565 default: 566 g_assert_not_reached(); 567 } 568 569 if (tot_len > s->mtu) { 570 stats->LROPktsRxOK++; 571 stats->LROBytesRxOK += tot_len; 572 } 573 break; 574 default: 575 g_assert_not_reached(); 576 } 577 } 578 579 static inline void 580 vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring, 581 struct Vmxnet3_TxDesc *txd) 582 { 583 vmxnet3_ring_read_curr_cell(pcidev, ring, txd); 584 txd->addr = le64_to_cpu(txd->addr); 585 txd->val1 = le32_to_cpu(txd->val1); 586 txd->val2 = le32_to_cpu(txd->val2); 587 } 588 589 static inline bool 590 vmxnet3_pop_next_tx_descr(VMXNET3State *s, 591 int qidx, 592 struct Vmxnet3_TxDesc *txd, 593 uint32_t *descr_idx) 594 { 595 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring; 596 PCIDevice *d = PCI_DEVICE(s); 597 598 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 599 if (txd->gen == vmxnet3_ring_curr_gen(ring)) { 600 /* Only read after generation field verification */ 601 smp_rmb(); 602 /* Re-read to be sure we got the latest version */ 603 vmxnet3_ring_read_curr_txdesc(d, ring, txd); 604 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring); 605 *descr_idx = vmxnet3_ring_curr_cell_idx(ring); 606 vmxnet3_inc_tx_consumption_counter(s, qidx); 607 return true; 608 } 609 610 return false; 611 } 612 613 static bool 614 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx) 615 { 616 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK; 617 618 if (!vmxnet3_setup_tx_offloads(s)) { 619 status = VMXNET3_PKT_STATUS_ERROR; 620 goto func_exit; 621 } 622 623 /* debug prints */ 624 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt)); 625 net_tx_pkt_dump(s->tx_pkt); 626 627 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) { 628 status = VMXNET3_PKT_STATUS_DISCARD; 629 goto func_exit; 630 } 631 632 func_exit: 633 vmxnet3_on_tx_done_update_stats(s, qidx, status); 634 return (status == VMXNET3_PKT_STATUS_OK); 635 } 636 637 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx) 638 { 639 struct Vmxnet3_TxDesc txd; 640 uint32_t txd_idx; 641 uint32_t data_len; 642 hwaddr data_pa; 643 644 for (;;) { 645 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) { 646 break; 647 } 648 649 vmxnet3_dump_tx_descr(&txd); 650 651 if (!s->skip_current_tx_pkt) { 652 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE; 653 data_pa = txd.addr; 654 655 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt, 656 data_pa, 657 data_len)) { 658 s->skip_current_tx_pkt = true; 659 } 660 } 661 662 if (s->tx_sop) { 663 vmxnet3_tx_retrieve_metadata(s, &txd); 664 s->tx_sop = false; 665 } 666 667 if (txd.eop) { 668 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) { 669 if (s->needs_vlan) { 670 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci); 671 } 672 673 vmxnet3_send_packet(s, qidx); 674 } else { 675 vmxnet3_on_tx_done_update_stats(s, qidx, 676 VMXNET3_PKT_STATUS_ERROR); 677 } 678 679 vmxnet3_complete_packet(s, qidx, txd_idx); 680 s->tx_sop = true; 681 s->skip_current_tx_pkt = false; 682 net_tx_pkt_reset(s->tx_pkt); 683 } 684 } 685 } 686 687 static inline void 688 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx, 689 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx) 690 { 691 PCIDevice *d = PCI_DEVICE(s); 692 693 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx]; 694 *didx = vmxnet3_ring_curr_cell_idx(ring); 695 vmxnet3_ring_read_curr_cell(d, ring, dbuf); 696 dbuf->addr = le64_to_cpu(dbuf->addr); 697 dbuf->val1 = le32_to_cpu(dbuf->val1); 698 dbuf->ext1 = le32_to_cpu(dbuf->ext1); 699 } 700 701 static inline uint8_t 702 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx) 703 { 704 return s->rxq_descr[qidx].rx_ring[ridx].gen; 705 } 706 707 static inline hwaddr 708 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen) 709 { 710 uint8_t ring_gen; 711 struct Vmxnet3_RxCompDesc rxcd; 712 713 hwaddr daddr = 714 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring); 715 716 pci_dma_read(PCI_DEVICE(s), 717 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc)); 718 rxcd.val1 = le32_to_cpu(rxcd.val1); 719 rxcd.val2 = le32_to_cpu(rxcd.val2); 720 rxcd.val3 = le32_to_cpu(rxcd.val3); 721 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring); 722 723 if (rxcd.gen != ring_gen) { 724 *descr_gen = ring_gen; 725 vmxnet3_inc_rx_completion_counter(s, qidx); 726 return daddr; 727 } 728 729 return 0; 730 } 731 732 static inline void 733 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx) 734 { 735 vmxnet3_dec_rx_completion_counter(s, qidx); 736 } 737 738 #define RXQ_IDX (0) 739 #define RX_HEAD_BODY_RING (0) 740 #define RX_BODY_ONLY_RING (1) 741 742 static bool 743 vmxnet3_get_next_head_rx_descr(VMXNET3State *s, 744 struct Vmxnet3_RxDesc *descr_buf, 745 uint32_t *descr_idx, 746 uint32_t *ridx) 747 { 748 for (;;) { 749 uint32_t ring_gen; 750 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 751 descr_buf, descr_idx); 752 753 /* If no more free descriptors - return */ 754 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING); 755 if (descr_buf->gen != ring_gen) { 756 return false; 757 } 758 759 /* Only read after generation field verification */ 760 smp_rmb(); 761 /* Re-read to be sure we got the latest version */ 762 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, 763 descr_buf, descr_idx); 764 765 /* Mark current descriptor as used/skipped */ 766 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 767 768 /* If this is what we are looking for - return */ 769 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) { 770 *ridx = RX_HEAD_BODY_RING; 771 return true; 772 } 773 } 774 } 775 776 static bool 777 vmxnet3_get_next_body_rx_descr(VMXNET3State *s, 778 struct Vmxnet3_RxDesc *d, 779 uint32_t *didx, 780 uint32_t *ridx) 781 { 782 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 783 784 /* Try to find corresponding descriptor in head/body ring */ 785 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) { 786 /* Only read after generation field verification */ 787 smp_rmb(); 788 /* Re-read to be sure we got the latest version */ 789 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx); 790 if (d->btype == VMXNET3_RXD_BTYPE_BODY) { 791 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING); 792 *ridx = RX_HEAD_BODY_RING; 793 return true; 794 } 795 } 796 797 /* 798 * If there is no free descriptors on head/body ring or next free 799 * descriptor is a head descriptor switch to body only ring 800 */ 801 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 802 803 /* If no more free descriptors - return */ 804 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) { 805 /* Only read after generation field verification */ 806 smp_rmb(); 807 /* Re-read to be sure we got the latest version */ 808 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx); 809 assert(d->btype == VMXNET3_RXD_BTYPE_BODY); 810 *ridx = RX_BODY_ONLY_RING; 811 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING); 812 return true; 813 } 814 815 return false; 816 } 817 818 static inline bool 819 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head, 820 struct Vmxnet3_RxDesc *descr_buf, 821 uint32_t *descr_idx, 822 uint32_t *ridx) 823 { 824 if (is_head || !s->rx_packets_compound) { 825 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx); 826 } else { 827 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx); 828 } 829 } 830 831 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID), 832 * the implementation always passes an RxCompDesc with a "Checksum 833 * calculated and found correct" to the OS (cnc=0 and tuc=1, see 834 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior. 835 * 836 * Therefore, if packet has the NEEDS_CSUM set, we must calculate 837 * and place a fully computed checksum into the tcp/udp header. 838 * Otherwise, the OS driver will receive a checksum-correct indication 839 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field 840 * having just the pseudo header csum value. 841 * 842 * While this is not a problem if packet is destined for local delivery, 843 * in the case the host OS performs forwarding, it will forward an 844 * incorrectly checksummed packet. 845 */ 846 static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt, 847 const void *pkt_data, 848 size_t pkt_len) 849 { 850 struct virtio_net_hdr *vhdr; 851 bool isip4, isip6, istcp, isudp; 852 uint8_t *data; 853 int len; 854 855 if (!net_rx_pkt_has_virt_hdr(pkt)) { 856 return; 857 } 858 859 vhdr = net_rx_pkt_get_vhdr(pkt); 860 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 861 return; 862 } 863 864 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 865 if (!(isip4 || isip6) || !(istcp || isudp)) { 866 return; 867 } 868 869 vmxnet3_dump_virt_hdr(vhdr); 870 871 /* Validate packet len: csum_start + scum_offset + length of csum field */ 872 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) { 873 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, " 874 "cannot calculate checksum", 875 pkt_len, vhdr->csum_start, vhdr->csum_offset); 876 return; 877 } 878 879 data = (uint8_t *)pkt_data + vhdr->csum_start; 880 len = pkt_len - vhdr->csum_start; 881 /* Put the checksum obtained into the packet */ 882 stw_be_p(data + vhdr->csum_offset, 883 net_checksum_finish_nozero(net_checksum_add(len, data))); 884 885 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM; 886 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID; 887 } 888 889 static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt, 890 struct Vmxnet3_RxCompDesc *rxcd) 891 { 892 int csum_ok, is_gso; 893 bool isip4, isip6, istcp, isudp; 894 struct virtio_net_hdr *vhdr; 895 uint8_t offload_type; 896 897 if (net_rx_pkt_is_vlan_stripped(pkt)) { 898 rxcd->ts = 1; 899 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt); 900 } 901 902 if (!net_rx_pkt_has_virt_hdr(pkt)) { 903 goto nocsum; 904 } 905 906 vhdr = net_rx_pkt_get_vhdr(pkt); 907 /* 908 * Checksum is valid when lower level tell so or when lower level 909 * requires checksum offload telling that packet produced/bridged 910 * locally and did travel over network after last checksum calculation 911 * or production 912 */ 913 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) || 914 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM); 915 916 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN; 917 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0; 918 919 if (!csum_ok && !is_gso) { 920 goto nocsum; 921 } 922 923 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 924 if ((!istcp && !isudp) || (!isip4 && !isip6)) { 925 goto nocsum; 926 } 927 928 rxcd->cnc = 0; 929 rxcd->v4 = isip4 ? 1 : 0; 930 rxcd->v6 = isip6 ? 1 : 0; 931 rxcd->tcp = istcp ? 1 : 0; 932 rxcd->udp = isudp ? 1 : 0; 933 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1; 934 return; 935 936 nocsum: 937 rxcd->cnc = 1; 938 return; 939 } 940 941 static void 942 vmxnet3_pci_dma_writev(PCIDevice *pci_dev, 943 const struct iovec *iov, 944 size_t start_iov_off, 945 hwaddr target_addr, 946 size_t bytes_to_copy) 947 { 948 size_t curr_off = 0; 949 size_t copied = 0; 950 951 while (bytes_to_copy) { 952 if (start_iov_off < (curr_off + iov->iov_len)) { 953 size_t chunk_len = 954 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy); 955 956 pci_dma_write(pci_dev, target_addr + copied, 957 iov->iov_base + start_iov_off - curr_off, 958 chunk_len); 959 960 copied += chunk_len; 961 start_iov_off += chunk_len; 962 curr_off = start_iov_off; 963 bytes_to_copy -= chunk_len; 964 } else { 965 curr_off += iov->iov_len; 966 } 967 iov++; 968 } 969 } 970 971 static void 972 vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa, 973 struct Vmxnet3_RxCompDesc *rxcd) 974 { 975 rxcd->val1 = cpu_to_le32(rxcd->val1); 976 rxcd->val2 = cpu_to_le32(rxcd->val2); 977 rxcd->val3 = cpu_to_le32(rxcd->val3); 978 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd)); 979 } 980 981 static bool 982 vmxnet3_indicate_packet(VMXNET3State *s) 983 { 984 struct Vmxnet3_RxDesc rxd; 985 PCIDevice *d = PCI_DEVICE(s); 986 bool is_head = true; 987 uint32_t rxd_idx; 988 uint32_t rx_ridx = 0; 989 990 struct Vmxnet3_RxCompDesc rxcd; 991 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN; 992 hwaddr new_rxcd_pa = 0; 993 hwaddr ready_rxcd_pa = 0; 994 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt); 995 size_t bytes_copied = 0; 996 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt); 997 uint16_t num_frags = 0; 998 size_t chunk_size; 999 1000 net_rx_pkt_dump(s->rx_pkt); 1001 1002 while (bytes_left > 0) { 1003 1004 /* cannot add more frags to packet */ 1005 if (num_frags == s->max_rx_frags) { 1006 break; 1007 } 1008 1009 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen); 1010 if (!new_rxcd_pa) { 1011 break; 1012 } 1013 1014 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) { 1015 break; 1016 } 1017 1018 chunk_size = MIN(bytes_left, rxd.len); 1019 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size); 1020 bytes_copied += chunk_size; 1021 bytes_left -= chunk_size; 1022 1023 vmxnet3_dump_rx_descr(&rxd); 1024 1025 if (ready_rxcd_pa != 0) { 1026 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1027 } 1028 1029 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc)); 1030 rxcd.rxdIdx = rxd_idx; 1031 rxcd.len = chunk_size; 1032 rxcd.sop = is_head; 1033 rxcd.gen = new_rxcd_gen; 1034 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num; 1035 1036 if (bytes_left == 0) { 1037 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd); 1038 } 1039 1040 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu " 1041 "sop %d csum_correct %lu", 1042 (unsigned long) rx_ridx, 1043 (unsigned long) rxcd.rxdIdx, 1044 (unsigned long) rxcd.len, 1045 (int) rxcd.sop, 1046 (unsigned long) rxcd.tuc); 1047 1048 is_head = false; 1049 ready_rxcd_pa = new_rxcd_pa; 1050 new_rxcd_pa = 0; 1051 num_frags++; 1052 } 1053 1054 if (ready_rxcd_pa != 0) { 1055 rxcd.eop = 1; 1056 rxcd.err = (bytes_left != 0); 1057 1058 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd); 1059 1060 /* Flush RX descriptor changes */ 1061 smp_wmb(); 1062 } 1063 1064 if (new_rxcd_pa != 0) { 1065 vmxnet3_revert_rxc_descr(s, RXQ_IDX); 1066 } 1067 1068 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx); 1069 1070 if (bytes_left == 0) { 1071 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK); 1072 return true; 1073 } else if (num_frags == s->max_rx_frags) { 1074 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR); 1075 return false; 1076 } else { 1077 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, 1078 VMXNET3_PKT_STATUS_OUT_OF_BUF); 1079 return false; 1080 } 1081 } 1082 1083 static void 1084 vmxnet3_io_bar0_write(void *opaque, hwaddr addr, 1085 uint64_t val, unsigned size) 1086 { 1087 VMXNET3State *s = opaque; 1088 1089 if (!s->device_active) { 1090 return; 1091 } 1092 1093 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD, 1094 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) { 1095 int tx_queue_idx = 1096 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD, 1097 VMXNET3_REG_ALIGN); 1098 assert(tx_queue_idx <= s->txq_num); 1099 vmxnet3_process_tx_queue(s, tx_queue_idx); 1100 return; 1101 } 1102 1103 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1104 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1105 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1106 VMXNET3_REG_ALIGN); 1107 1108 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val); 1109 1110 vmxnet3_on_interrupt_mask_changed(s, l, val); 1111 return; 1112 } 1113 1114 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD, 1115 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) || 1116 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2, 1117 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) { 1118 return; 1119 } 1120 1121 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d", 1122 (uint64_t) addr, val, size); 1123 } 1124 1125 static uint64_t 1126 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) 1127 { 1128 VMXNET3State *s = opaque; 1129 1130 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, 1131 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { 1132 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR, 1133 VMXNET3_REG_ALIGN); 1134 return s->interrupt_states[l].is_masked; 1135 } 1136 1137 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); 1138 return 0; 1139 } 1140 1141 static void vmxnet3_reset_interrupt_states(VMXNET3State *s) 1142 { 1143 int i; 1144 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) { 1145 s->interrupt_states[i].is_asserted = false; 1146 s->interrupt_states[i].is_pending = false; 1147 s->interrupt_states[i].is_masked = true; 1148 } 1149 } 1150 1151 static void vmxnet3_reset_mac(VMXNET3State *s) 1152 { 1153 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a)); 1154 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a)); 1155 } 1156 1157 static void vmxnet3_deactivate_device(VMXNET3State *s) 1158 { 1159 if (s->device_active) { 1160 VMW_CBPRN("Deactivating vmxnet3..."); 1161 net_tx_pkt_reset(s->tx_pkt); 1162 net_tx_pkt_uninit(s->tx_pkt); 1163 net_rx_pkt_uninit(s->rx_pkt); 1164 s->device_active = false; 1165 } 1166 } 1167 1168 static void vmxnet3_reset(VMXNET3State *s) 1169 { 1170 VMW_CBPRN("Resetting vmxnet3..."); 1171 1172 vmxnet3_deactivate_device(s); 1173 vmxnet3_reset_interrupt_states(s); 1174 s->drv_shmem = 0; 1175 s->tx_sop = true; 1176 s->skip_current_tx_pkt = false; 1177 } 1178 1179 static void vmxnet3_update_rx_mode(VMXNET3State *s) 1180 { 1181 PCIDevice *d = PCI_DEVICE(s); 1182 1183 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1184 devRead.rxFilterConf.rxMode); 1185 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode); 1186 } 1187 1188 static void vmxnet3_update_vlan_filters(VMXNET3State *s) 1189 { 1190 int i; 1191 PCIDevice *d = PCI_DEVICE(s); 1192 1193 /* Copy configuration from shared memory */ 1194 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, 1195 devRead.rxFilterConf.vfTable, 1196 s->vlan_table, 1197 sizeof(s->vlan_table)); 1198 1199 /* Invert byte order when needed */ 1200 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) { 1201 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]); 1202 } 1203 1204 /* Dump configuration for debugging purposes */ 1205 VMW_CFPRN("Configured VLANs:"); 1206 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) { 1207 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) { 1208 VMW_CFPRN("\tVLAN %d is present", i); 1209 } 1210 } 1211 } 1212 1213 static void vmxnet3_update_mcast_filters(VMXNET3State *s) 1214 { 1215 PCIDevice *d = PCI_DEVICE(s); 1216 1217 uint16_t list_bytes = 1218 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, 1219 devRead.rxFilterConf.mfTableLen); 1220 1221 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]); 1222 1223 s->mcast_list = g_realloc(s->mcast_list, list_bytes); 1224 if (!s->mcast_list) { 1225 if (s->mcast_list_len == 0) { 1226 VMW_CFPRN("Current multicast list is empty"); 1227 } else { 1228 VMW_ERPRN("Failed to allocate multicast list of %d elements", 1229 s->mcast_list_len); 1230 } 1231 s->mcast_list_len = 0; 1232 } else { 1233 int i; 1234 hwaddr mcast_list_pa = 1235 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, 1236 devRead.rxFilterConf.mfTablePA); 1237 1238 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes); 1239 1240 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len); 1241 for (i = 0; i < s->mcast_list_len; i++) { 1242 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a)); 1243 } 1244 } 1245 } 1246 1247 static void vmxnet3_setup_rx_filtering(VMXNET3State *s) 1248 { 1249 vmxnet3_update_rx_mode(s); 1250 vmxnet3_update_vlan_filters(s); 1251 vmxnet3_update_mcast_filters(s); 1252 } 1253 1254 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s) 1255 { 1256 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2); 1257 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode); 1258 return interrupt_mode; 1259 } 1260 1261 static void vmxnet3_fill_stats(VMXNET3State *s) 1262 { 1263 int i; 1264 PCIDevice *d = PCI_DEVICE(s); 1265 1266 if (!s->device_active) 1267 return; 1268 1269 for (i = 0; i < s->txq_num; i++) { 1270 pci_dma_write(d, 1271 s->txq_descr[i].tx_stats_pa, 1272 &s->txq_descr[i].txq_stats, 1273 sizeof(s->txq_descr[i].txq_stats)); 1274 } 1275 1276 for (i = 0; i < s->rxq_num; i++) { 1277 pci_dma_write(d, 1278 s->rxq_descr[i].rx_stats_pa, 1279 &s->rxq_descr[i].rxq_stats, 1280 sizeof(s->rxq_descr[i].rxq_stats)); 1281 } 1282 } 1283 1284 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s) 1285 { 1286 struct Vmxnet3_GOSInfo gos; 1287 PCIDevice *d = PCI_DEVICE(s); 1288 1289 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos, 1290 &gos, sizeof(gos)); 1291 s->rx_packets_compound = 1292 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true; 1293 1294 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound); 1295 } 1296 1297 static void 1298 vmxnet3_dump_conf_descr(const char *name, 1299 struct Vmxnet3_VariableLenConfDesc *pm_descr) 1300 { 1301 VMW_CFPRN("%s descriptor dump: Version %u, Length %u", 1302 name, pm_descr->confVer, pm_descr->confLen); 1303 1304 }; 1305 1306 static void vmxnet3_update_pm_state(VMXNET3State *s) 1307 { 1308 struct Vmxnet3_VariableLenConfDesc pm_descr; 1309 PCIDevice *d = PCI_DEVICE(s); 1310 1311 pm_descr.confLen = 1312 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen); 1313 pm_descr.confVer = 1314 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer); 1315 pm_descr.confPA = 1316 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA); 1317 1318 vmxnet3_dump_conf_descr("PM State", &pm_descr); 1319 } 1320 1321 static void vmxnet3_update_features(VMXNET3State *s) 1322 { 1323 uint32_t guest_features; 1324 int rxcso_supported; 1325 PCIDevice *d = PCI_DEVICE(s); 1326 1327 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, 1328 devRead.misc.uptFeatures); 1329 1330 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM); 1331 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN); 1332 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO); 1333 1334 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d", 1335 s->lro_supported, rxcso_supported, 1336 s->rx_vlan_stripping); 1337 if (s->peer_has_vhdr) { 1338 qemu_set_offload(qemu_get_queue(s->nic)->peer, 1339 rxcso_supported, 1340 s->lro_supported, 1341 s->lro_supported, 1342 0, 1343 0); 1344 } 1345 } 1346 1347 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) 1348 { 1349 return s->msix_used || msi_enabled(PCI_DEVICE(s)) 1350 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1; 1351 } 1352 1353 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx) 1354 { 1355 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS; 1356 if (idx >= max_ints) { 1357 hw_error("Bad interrupt index: %d\n", idx); 1358 } 1359 } 1360 1361 static void vmxnet3_validate_interrupts(VMXNET3State *s) 1362 { 1363 int i; 1364 1365 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx); 1366 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx); 1367 1368 for (i = 0; i < s->txq_num; i++) { 1369 int idx = s->txq_descr[i].intr_idx; 1370 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx); 1371 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1372 } 1373 1374 for (i = 0; i < s->rxq_num; i++) { 1375 int idx = s->rxq_descr[i].intr_idx; 1376 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx); 1377 vmxnet3_validate_interrupt_idx(s->msix_used, idx); 1378 } 1379 } 1380 1381 static void vmxnet3_validate_queues(VMXNET3State *s) 1382 { 1383 /* 1384 * txq_num and rxq_num are total number of queues 1385 * configured by guest. These numbers must not 1386 * exceed corresponding maximal values. 1387 */ 1388 1389 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) { 1390 hw_error("Bad TX queues number: %d\n", s->txq_num); 1391 } 1392 1393 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) { 1394 hw_error("Bad RX queues number: %d\n", s->rxq_num); 1395 } 1396 } 1397 1398 static void vmxnet3_activate_device(VMXNET3State *s) 1399 { 1400 int i; 1401 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1; 1402 PCIDevice *d = PCI_DEVICE(s); 1403 hwaddr qdescr_table_pa; 1404 uint64_t pa; 1405 uint32_t size; 1406 1407 /* Verify configuration consistency */ 1408 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) { 1409 VMW_ERPRN("Device configuration received from driver is invalid"); 1410 return; 1411 } 1412 1413 /* Verify if device is active */ 1414 if (s->device_active) { 1415 VMW_CFPRN("Vmxnet3 device is active"); 1416 return; 1417 } 1418 1419 vmxnet3_adjust_by_guest_type(s); 1420 vmxnet3_update_features(s); 1421 vmxnet3_update_pm_state(s); 1422 vmxnet3_setup_rx_filtering(s); 1423 /* Cache fields from shared memory */ 1424 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu); 1425 VMW_CFPRN("MTU is %u", s->mtu); 1426 1427 s->max_rx_frags = 1428 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG); 1429 1430 if (s->max_rx_frags == 0) { 1431 s->max_rx_frags = 1; 1432 } 1433 1434 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags); 1435 1436 s->event_int_idx = 1437 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx); 1438 assert(vmxnet3_verify_intx(s, s->event_int_idx)); 1439 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); 1440 1441 s->auto_int_masking = 1442 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask); 1443 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking); 1444 1445 s->txq_num = 1446 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues); 1447 s->rxq_num = 1448 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues); 1449 1450 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num); 1451 vmxnet3_validate_queues(s); 1452 1453 qdescr_table_pa = 1454 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA); 1455 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa); 1456 1457 /* 1458 * Worst-case scenario is a packet that holds all TX rings space so 1459 * we calculate total size of all TX rings for max TX fragments number 1460 */ 1461 s->max_tx_frags = 0; 1462 1463 /* TX queues */ 1464 for (i = 0; i < s->txq_num; i++) { 1465 hwaddr qdescr_pa = 1466 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc); 1467 1468 /* Read interrupt number for this TX queue */ 1469 s->txq_descr[i].intr_idx = 1470 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx); 1471 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); 1472 1473 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); 1474 1475 /* Read rings memory locations for TX queues */ 1476 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA); 1477 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize); 1478 1479 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size, 1480 sizeof(struct Vmxnet3_TxDesc), false); 1481 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring); 1482 1483 s->max_tx_frags += size; 1484 1485 /* TXC ring */ 1486 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA); 1487 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize); 1488 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size, 1489 sizeof(struct Vmxnet3_TxCompDesc), true); 1490 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring); 1491 1492 s->txq_descr[i].tx_stats_pa = 1493 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats); 1494 1495 memset(&s->txq_descr[i].txq_stats, 0, 1496 sizeof(s->txq_descr[i].txq_stats)); 1497 1498 /* Fill device-managed parameters for queues */ 1499 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa, 1500 ctrl.txThreshold, 1501 VMXNET3_DEF_TX_THRESHOLD); 1502 } 1503 1504 /* Preallocate TX packet wrapper */ 1505 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags); 1506 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 1507 s->max_tx_frags, s->peer_has_vhdr); 1508 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 1509 1510 /* Read rings memory locations for RX queues */ 1511 for (i = 0; i < s->rxq_num; i++) { 1512 int j; 1513 hwaddr qd_pa = 1514 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) + 1515 i * sizeof(struct Vmxnet3_RxQueueDesc); 1516 1517 /* Read interrupt number for this RX queue */ 1518 s->rxq_descr[i].intr_idx = 1519 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx); 1520 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); 1521 1522 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); 1523 1524 /* Read rings memory locations */ 1525 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) { 1526 /* RX rings */ 1527 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]); 1528 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]); 1529 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size, 1530 sizeof(struct Vmxnet3_RxDesc), false); 1531 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d", 1532 i, j, pa, size); 1533 } 1534 1535 /* RXC ring */ 1536 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA); 1537 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize); 1538 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size, 1539 sizeof(struct Vmxnet3_RxCompDesc), true); 1540 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size); 1541 1542 s->rxq_descr[i].rx_stats_pa = 1543 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats); 1544 memset(&s->rxq_descr[i].rxq_stats, 0, 1545 sizeof(s->rxq_descr[i].rxq_stats)); 1546 } 1547 1548 vmxnet3_validate_interrupts(s); 1549 1550 /* Make sure everything is in place before device activation */ 1551 smp_wmb(); 1552 1553 vmxnet3_reset_mac(s); 1554 1555 s->device_active = true; 1556 } 1557 1558 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd) 1559 { 1560 s->last_command = cmd; 1561 1562 switch (cmd) { 1563 case VMXNET3_CMD_GET_PERM_MAC_HI: 1564 VMW_CBPRN("Set: Get upper part of permanent MAC"); 1565 break; 1566 1567 case VMXNET3_CMD_GET_PERM_MAC_LO: 1568 VMW_CBPRN("Set: Get lower part of permanent MAC"); 1569 break; 1570 1571 case VMXNET3_CMD_GET_STATS: 1572 VMW_CBPRN("Set: Get device statistics"); 1573 vmxnet3_fill_stats(s); 1574 break; 1575 1576 case VMXNET3_CMD_ACTIVATE_DEV: 1577 VMW_CBPRN("Set: Activating vmxnet3 device"); 1578 vmxnet3_activate_device(s); 1579 break; 1580 1581 case VMXNET3_CMD_UPDATE_RX_MODE: 1582 VMW_CBPRN("Set: Update rx mode"); 1583 vmxnet3_update_rx_mode(s); 1584 break; 1585 1586 case VMXNET3_CMD_UPDATE_VLAN_FILTERS: 1587 VMW_CBPRN("Set: Update VLAN filters"); 1588 vmxnet3_update_vlan_filters(s); 1589 break; 1590 1591 case VMXNET3_CMD_UPDATE_MAC_FILTERS: 1592 VMW_CBPRN("Set: Update MAC filters"); 1593 vmxnet3_update_mcast_filters(s); 1594 break; 1595 1596 case VMXNET3_CMD_UPDATE_FEATURE: 1597 VMW_CBPRN("Set: Update features"); 1598 vmxnet3_update_features(s); 1599 break; 1600 1601 case VMXNET3_CMD_UPDATE_PMCFG: 1602 VMW_CBPRN("Set: Update power management config"); 1603 vmxnet3_update_pm_state(s); 1604 break; 1605 1606 case VMXNET3_CMD_GET_LINK: 1607 VMW_CBPRN("Set: Get link"); 1608 break; 1609 1610 case VMXNET3_CMD_RESET_DEV: 1611 VMW_CBPRN("Set: Reset device"); 1612 vmxnet3_reset(s); 1613 break; 1614 1615 case VMXNET3_CMD_QUIESCE_DEV: 1616 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device"); 1617 vmxnet3_deactivate_device(s); 1618 break; 1619 1620 case VMXNET3_CMD_GET_CONF_INTR: 1621 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration"); 1622 break; 1623 1624 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1625 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - " 1626 "adaptive ring info flags"); 1627 break; 1628 1629 case VMXNET3_CMD_GET_DID_LO: 1630 VMW_CBPRN("Set: Get lower part of device ID"); 1631 break; 1632 1633 case VMXNET3_CMD_GET_DID_HI: 1634 VMW_CBPRN("Set: Get upper part of device ID"); 1635 break; 1636 1637 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1638 VMW_CBPRN("Set: Get device extra info"); 1639 break; 1640 1641 default: 1642 VMW_CBPRN("Received unknown command: %" PRIx64, cmd); 1643 break; 1644 } 1645 } 1646 1647 static uint64_t vmxnet3_get_command_status(VMXNET3State *s) 1648 { 1649 uint64_t ret; 1650 1651 switch (s->last_command) { 1652 case VMXNET3_CMD_ACTIVATE_DEV: 1653 ret = (s->device_active) ? 0 : 1; 1654 VMW_CFPRN("Device active: %" PRIx64, ret); 1655 break; 1656 1657 case VMXNET3_CMD_RESET_DEV: 1658 case VMXNET3_CMD_QUIESCE_DEV: 1659 case VMXNET3_CMD_GET_QUEUE_STATUS: 1660 case VMXNET3_CMD_GET_DEV_EXTRA_INFO: 1661 ret = 0; 1662 break; 1663 1664 case VMXNET3_CMD_GET_LINK: 1665 ret = s->link_status_and_speed; 1666 VMW_CFPRN("Link and speed: %" PRIx64, ret); 1667 break; 1668 1669 case VMXNET3_CMD_GET_PERM_MAC_LO: 1670 ret = vmxnet3_get_mac_low(&s->perm_mac); 1671 break; 1672 1673 case VMXNET3_CMD_GET_PERM_MAC_HI: 1674 ret = vmxnet3_get_mac_high(&s->perm_mac); 1675 break; 1676 1677 case VMXNET3_CMD_GET_CONF_INTR: 1678 ret = vmxnet3_get_interrupt_config(s); 1679 break; 1680 1681 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO: 1682 ret = VMXNET3_DISABLE_ADAPTIVE_RING; 1683 break; 1684 1685 case VMXNET3_CMD_GET_DID_LO: 1686 ret = PCI_DEVICE_ID_VMWARE_VMXNET3; 1687 break; 1688 1689 case VMXNET3_CMD_GET_DID_HI: 1690 ret = VMXNET3_DEVICE_REVISION; 1691 break; 1692 1693 default: 1694 VMW_WRPRN("Received request for unknown command: %x", s->last_command); 1695 ret = 0; 1696 break; 1697 } 1698 1699 return ret; 1700 } 1701 1702 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val) 1703 { 1704 uint32_t events; 1705 PCIDevice *d = PCI_DEVICE(s); 1706 1707 VMW_CBPRN("Setting events: 0x%x", val); 1708 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val; 1709 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1710 } 1711 1712 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val) 1713 { 1714 PCIDevice *d = PCI_DEVICE(s); 1715 uint32_t events; 1716 1717 VMW_CBPRN("Clearing events: 0x%x", val); 1718 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val; 1719 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events); 1720 } 1721 1722 static void 1723 vmxnet3_io_bar1_write(void *opaque, 1724 hwaddr addr, 1725 uint64_t val, 1726 unsigned size) 1727 { 1728 VMXNET3State *s = opaque; 1729 1730 switch (addr) { 1731 /* Vmxnet3 Revision Report Selection */ 1732 case VMXNET3_REG_VRRS: 1733 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d", 1734 val, size); 1735 break; 1736 1737 /* UPT Version Report Selection */ 1738 case VMXNET3_REG_UVRS: 1739 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d", 1740 val, size); 1741 break; 1742 1743 /* Driver Shared Address Low */ 1744 case VMXNET3_REG_DSAL: 1745 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d", 1746 val, size); 1747 /* 1748 * Guest driver will first write the low part of the shared 1749 * memory address. We save it to temp variable and set the 1750 * shared address only after we get the high part 1751 */ 1752 if (val == 0) { 1753 vmxnet3_deactivate_device(s); 1754 } 1755 s->temp_shared_guest_driver_memory = val; 1756 s->drv_shmem = 0; 1757 break; 1758 1759 /* Driver Shared Address High */ 1760 case VMXNET3_REG_DSAH: 1761 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d", 1762 val, size); 1763 /* 1764 * Set the shared memory between guest driver and device. 1765 * We already should have low address part. 1766 */ 1767 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32); 1768 break; 1769 1770 /* Command */ 1771 case VMXNET3_REG_CMD: 1772 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d", 1773 val, size); 1774 vmxnet3_handle_command(s, val); 1775 break; 1776 1777 /* MAC Address Low */ 1778 case VMXNET3_REG_MACL: 1779 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d", 1780 val, size); 1781 s->temp_mac = val; 1782 break; 1783 1784 /* MAC Address High */ 1785 case VMXNET3_REG_MACH: 1786 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d", 1787 val, size); 1788 vmxnet3_set_variable_mac(s, val, s->temp_mac); 1789 break; 1790 1791 /* Interrupt Cause Register */ 1792 case VMXNET3_REG_ICR: 1793 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d", 1794 val, size); 1795 g_assert_not_reached(); 1796 break; 1797 1798 /* Event Cause Register */ 1799 case VMXNET3_REG_ECR: 1800 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d", 1801 val, size); 1802 vmxnet3_ack_events(s, val); 1803 break; 1804 1805 default: 1806 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d", 1807 addr, val, size); 1808 break; 1809 } 1810 } 1811 1812 static uint64_t 1813 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size) 1814 { 1815 VMXNET3State *s = opaque; 1816 uint64_t ret = 0; 1817 1818 switch (addr) { 1819 /* Vmxnet3 Revision Report Selection */ 1820 case VMXNET3_REG_VRRS: 1821 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size); 1822 ret = VMXNET3_DEVICE_REVISION; 1823 break; 1824 1825 /* UPT Version Report Selection */ 1826 case VMXNET3_REG_UVRS: 1827 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size); 1828 ret = VMXNET3_UPT_REVISION; 1829 break; 1830 1831 /* Command */ 1832 case VMXNET3_REG_CMD: 1833 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size); 1834 ret = vmxnet3_get_command_status(s); 1835 break; 1836 1837 /* MAC Address Low */ 1838 case VMXNET3_REG_MACL: 1839 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size); 1840 ret = vmxnet3_get_mac_low(&s->conf.macaddr); 1841 break; 1842 1843 /* MAC Address High */ 1844 case VMXNET3_REG_MACH: 1845 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size); 1846 ret = vmxnet3_get_mac_high(&s->conf.macaddr); 1847 break; 1848 1849 /* 1850 * Interrupt Cause Register 1851 * Used for legacy interrupts only so interrupt index always 0 1852 */ 1853 case VMXNET3_REG_ICR: 1854 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size); 1855 if (vmxnet3_interrupt_asserted(s, 0)) { 1856 vmxnet3_clear_interrupt(s, 0); 1857 ret = true; 1858 } else { 1859 ret = false; 1860 } 1861 break; 1862 1863 default: 1864 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size); 1865 break; 1866 } 1867 1868 return ret; 1869 } 1870 1871 static int 1872 vmxnet3_can_receive(NetClientState *nc) 1873 { 1874 VMXNET3State *s = qemu_get_nic_opaque(nc); 1875 return s->device_active && 1876 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP); 1877 } 1878 1879 static inline bool 1880 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data) 1881 { 1882 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK; 1883 if (IS_SPECIAL_VLAN_ID(vlan_tag)) { 1884 return true; 1885 } 1886 1887 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag); 1888 } 1889 1890 static bool 1891 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac) 1892 { 1893 int i; 1894 for (i = 0; i < s->mcast_list_len; i++) { 1895 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) { 1896 return true; 1897 } 1898 } 1899 return false; 1900 } 1901 1902 static bool 1903 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data, 1904 size_t size) 1905 { 1906 struct eth_header *ehdr = PKT_GET_ETH_HDR(data); 1907 1908 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) { 1909 return true; 1910 } 1911 1912 if (!vmxnet3_is_registered_vlan(s, data)) { 1913 return false; 1914 } 1915 1916 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) { 1917 case ETH_PKT_UCAST: 1918 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) { 1919 return false; 1920 } 1921 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) { 1922 return false; 1923 } 1924 break; 1925 1926 case ETH_PKT_BCAST: 1927 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) { 1928 return false; 1929 } 1930 break; 1931 1932 case ETH_PKT_MCAST: 1933 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) { 1934 return true; 1935 } 1936 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) { 1937 return false; 1938 } 1939 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) { 1940 return false; 1941 } 1942 break; 1943 1944 default: 1945 g_assert_not_reached(); 1946 } 1947 1948 return true; 1949 } 1950 1951 static ssize_t 1952 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1953 { 1954 VMXNET3State *s = qemu_get_nic_opaque(nc); 1955 size_t bytes_indicated; 1956 uint8_t min_buf[MIN_BUF_SIZE]; 1957 1958 if (!vmxnet3_can_receive(nc)) { 1959 VMW_PKPRN("Cannot receive now"); 1960 return -1; 1961 } 1962 1963 if (s->peer_has_vhdr) { 1964 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf); 1965 buf += sizeof(struct virtio_net_hdr); 1966 size -= sizeof(struct virtio_net_hdr); 1967 } 1968 1969 /* Pad to minimum Ethernet frame length */ 1970 if (size < sizeof(min_buf)) { 1971 memcpy(min_buf, buf, size); 1972 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1973 buf = min_buf; 1974 size = sizeof(min_buf); 1975 } 1976 1977 net_rx_pkt_set_packet_type(s->rx_pkt, 1978 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1979 1980 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) { 1981 net_rx_pkt_set_protocols(s->rx_pkt, buf, size); 1982 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size); 1983 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping); 1984 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1; 1985 if (bytes_indicated < size) { 1986 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size); 1987 } 1988 } else { 1989 VMW_PKPRN("Packet dropped by RX filter"); 1990 bytes_indicated = size; 1991 } 1992 1993 assert(size > 0); 1994 assert(bytes_indicated != 0); 1995 return bytes_indicated; 1996 } 1997 1998 static void vmxnet3_set_link_status(NetClientState *nc) 1999 { 2000 VMXNET3State *s = qemu_get_nic_opaque(nc); 2001 2002 if (nc->link_down) { 2003 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP; 2004 } else { 2005 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP; 2006 } 2007 2008 vmxnet3_set_events(s, VMXNET3_ECR_LINK); 2009 vmxnet3_trigger_interrupt(s, s->event_int_idx); 2010 } 2011 2012 static NetClientInfo net_vmxnet3_info = { 2013 .type = NET_CLIENT_DRIVER_NIC, 2014 .size = sizeof(NICState), 2015 .receive = vmxnet3_receive, 2016 .link_status_changed = vmxnet3_set_link_status, 2017 }; 2018 2019 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s) 2020 { 2021 NetClientState *nc = qemu_get_queue(s->nic); 2022 2023 if (qemu_has_vnet_hdr(nc->peer)) { 2024 return true; 2025 } 2026 2027 return false; 2028 } 2029 2030 static void vmxnet3_net_uninit(VMXNET3State *s) 2031 { 2032 g_free(s->mcast_list); 2033 vmxnet3_deactivate_device(s); 2034 qemu_del_nic(s->nic); 2035 } 2036 2037 static void vmxnet3_net_init(VMXNET3State *s) 2038 { 2039 DeviceState *d = DEVICE(s); 2040 2041 VMW_CBPRN("vmxnet3_net_init called..."); 2042 2043 qemu_macaddr_default_if_unset(&s->conf.macaddr); 2044 2045 /* Windows guest will query the address that was set on init */ 2046 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a)); 2047 2048 s->mcast_list = NULL; 2049 s->mcast_list_len = 0; 2050 2051 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP; 2052 2053 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a)); 2054 2055 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf, 2056 object_get_typename(OBJECT(s)), 2057 d->id, s); 2058 2059 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s); 2060 s->tx_sop = true; 2061 s->skip_current_tx_pkt = false; 2062 s->tx_pkt = NULL; 2063 s->rx_pkt = NULL; 2064 s->rx_vlan_stripping = false; 2065 s->lro_supported = false; 2066 2067 if (s->peer_has_vhdr) { 2068 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer, 2069 sizeof(struct virtio_net_hdr)); 2070 2071 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1); 2072 } 2073 2074 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 2075 } 2076 2077 static void 2078 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors) 2079 { 2080 PCIDevice *d = PCI_DEVICE(s); 2081 int i; 2082 for (i = 0; i < num_vectors; i++) { 2083 msix_vector_unuse(d, i); 2084 } 2085 } 2086 2087 static bool 2088 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors) 2089 { 2090 PCIDevice *d = PCI_DEVICE(s); 2091 int i; 2092 for (i = 0; i < num_vectors; i++) { 2093 int res = msix_vector_use(d, i); 2094 if (0 > res) { 2095 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res); 2096 vmxnet3_unuse_msix_vectors(s, i); 2097 return false; 2098 } 2099 } 2100 return true; 2101 } 2102 2103 static bool 2104 vmxnet3_init_msix(VMXNET3State *s) 2105 { 2106 PCIDevice *d = PCI_DEVICE(s); 2107 int res = msix_init(d, VMXNET3_MAX_INTRS, 2108 &s->msix_bar, 2109 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE, 2110 &s->msix_bar, 2111 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s), 2112 VMXNET3_MSIX_OFFSET(s), NULL); 2113 2114 if (0 > res) { 2115 VMW_WRPRN("Failed to initialize MSI-X, error %d", res); 2116 s->msix_used = false; 2117 } else { 2118 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2119 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res); 2120 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2121 s->msix_used = false; 2122 } else { 2123 s->msix_used = true; 2124 } 2125 } 2126 return s->msix_used; 2127 } 2128 2129 static void 2130 vmxnet3_cleanup_msix(VMXNET3State *s) 2131 { 2132 PCIDevice *d = PCI_DEVICE(s); 2133 2134 if (s->msix_used) { 2135 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS); 2136 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2137 } 2138 } 2139 2140 static void 2141 vmxnet3_cleanup_msi(VMXNET3State *s) 2142 { 2143 PCIDevice *d = PCI_DEVICE(s); 2144 2145 msi_uninit(d); 2146 } 2147 2148 static const MemoryRegionOps b0_ops = { 2149 .read = vmxnet3_io_bar0_read, 2150 .write = vmxnet3_io_bar0_write, 2151 .endianness = DEVICE_LITTLE_ENDIAN, 2152 .impl = { 2153 .min_access_size = 4, 2154 .max_access_size = 4, 2155 }, 2156 }; 2157 2158 static const MemoryRegionOps b1_ops = { 2159 .read = vmxnet3_io_bar1_read, 2160 .write = vmxnet3_io_bar1_write, 2161 .endianness = DEVICE_LITTLE_ENDIAN, 2162 .impl = { 2163 .min_access_size = 4, 2164 .max_access_size = 4, 2165 }, 2166 }; 2167 2168 static uint64_t vmxnet3_device_serial_num(VMXNET3State *s) 2169 { 2170 uint64_t dsn_payload; 2171 uint8_t *dsnp = (uint8_t *)&dsn_payload; 2172 2173 dsnp[0] = 0xfe; 2174 dsnp[1] = s->conf.macaddr.a[3]; 2175 dsnp[2] = s->conf.macaddr.a[4]; 2176 dsnp[3] = s->conf.macaddr.a[5]; 2177 dsnp[4] = s->conf.macaddr.a[0]; 2178 dsnp[5] = s->conf.macaddr.a[1]; 2179 dsnp[6] = s->conf.macaddr.a[2]; 2180 dsnp[7] = 0xff; 2181 return dsn_payload; 2182 } 2183 2184 2185 #define VMXNET3_USE_64BIT (true) 2186 #define VMXNET3_PER_VECTOR_MASK (false) 2187 2188 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp) 2189 { 2190 VMXNET3State *s = VMXNET3(pci_dev); 2191 int ret; 2192 2193 VMW_CBPRN("Starting init..."); 2194 2195 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, 2196 "vmxnet3-b0", VMXNET3_PT_REG_SIZE); 2197 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX, 2198 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 2199 2200 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s, 2201 "vmxnet3-b1", VMXNET3_VD_REG_SIZE); 2202 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX, 2203 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); 2204 2205 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar", 2206 VMXNET3_MSIX_BAR_SIZE); 2207 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX, 2208 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar); 2209 2210 vmxnet3_reset_interrupt_states(s); 2211 2212 /* Interrupt pin A */ 2213 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01; 2214 2215 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS, 2216 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL); 2217 /* Any error other than -ENOTSUP(board's MSI support is broken) 2218 * is a programming error. Fall back to INTx silently on -ENOTSUP */ 2219 assert(!ret || ret == -ENOTSUP); 2220 2221 if (!vmxnet3_init_msix(s)) { 2222 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent."); 2223 } 2224 2225 vmxnet3_net_init(s); 2226 2227 if (pci_is_express(pci_dev)) { 2228 if (pci_bus_is_express(pci_get_bus(pci_dev))) { 2229 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET); 2230 } 2231 2232 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET, 2233 vmxnet3_device_serial_num(s)); 2234 } 2235 } 2236 2237 static void vmxnet3_instance_init(Object *obj) 2238 { 2239 VMXNET3State *s = VMXNET3(obj); 2240 device_add_bootindex_property(obj, &s->conf.bootindex, 2241 "bootindex", "/ethernet-phy@0", 2242 DEVICE(obj)); 2243 } 2244 2245 static void vmxnet3_pci_uninit(PCIDevice *pci_dev) 2246 { 2247 VMXNET3State *s = VMXNET3(pci_dev); 2248 2249 VMW_CBPRN("Starting uninit..."); 2250 2251 vmxnet3_net_uninit(s); 2252 2253 vmxnet3_cleanup_msix(s); 2254 2255 vmxnet3_cleanup_msi(s); 2256 } 2257 2258 static void vmxnet3_qdev_reset(DeviceState *dev) 2259 { 2260 PCIDevice *d = PCI_DEVICE(dev); 2261 VMXNET3State *s = VMXNET3(d); 2262 2263 VMW_CBPRN("Starting QDEV reset..."); 2264 vmxnet3_reset(s); 2265 } 2266 2267 static bool vmxnet3_mc_list_needed(void *opaque) 2268 { 2269 return true; 2270 } 2271 2272 static int vmxnet3_mcast_list_pre_load(void *opaque) 2273 { 2274 VMXNET3State *s = opaque; 2275 2276 s->mcast_list = g_malloc(s->mcast_list_buff_size); 2277 2278 return 0; 2279 } 2280 2281 2282 static int vmxnet3_pre_save(void *opaque) 2283 { 2284 VMXNET3State *s = opaque; 2285 2286 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr); 2287 2288 return 0; 2289 } 2290 2291 static const VMStateDescription vmxstate_vmxnet3_mcast_list = { 2292 .name = "vmxnet3/mcast_list", 2293 .version_id = 1, 2294 .minimum_version_id = 1, 2295 .pre_load = vmxnet3_mcast_list_pre_load, 2296 .needed = vmxnet3_mc_list_needed, 2297 .fields = (VMStateField[]) { 2298 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 2299 mcast_list_buff_size), 2300 VMSTATE_END_OF_LIST() 2301 } 2302 }; 2303 2304 static const VMStateDescription vmstate_vmxnet3_ring = { 2305 .name = "vmxnet3-ring", 2306 .version_id = 0, 2307 .fields = (VMStateField[]) { 2308 VMSTATE_UINT64(pa, Vmxnet3Ring), 2309 VMSTATE_UINT32(size, Vmxnet3Ring), 2310 VMSTATE_UINT32(cell_size, Vmxnet3Ring), 2311 VMSTATE_UINT32(next, Vmxnet3Ring), 2312 VMSTATE_UINT8(gen, Vmxnet3Ring), 2313 VMSTATE_END_OF_LIST() 2314 } 2315 }; 2316 2317 static const VMStateDescription vmstate_vmxnet3_tx_stats = { 2318 .name = "vmxnet3-tx-stats", 2319 .version_id = 0, 2320 .fields = (VMStateField[]) { 2321 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats), 2322 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats), 2323 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats), 2324 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats), 2325 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats), 2326 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats), 2327 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats), 2328 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats), 2329 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats), 2330 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats), 2331 VMSTATE_END_OF_LIST() 2332 } 2333 }; 2334 2335 static const VMStateDescription vmstate_vmxnet3_txq_descr = { 2336 .name = "vmxnet3-txq-descr", 2337 .version_id = 0, 2338 .fields = (VMStateField[]) { 2339 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2340 Vmxnet3Ring), 2341 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring, 2342 Vmxnet3Ring), 2343 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr), 2344 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr), 2345 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats, 2346 struct UPT1_TxStats), 2347 VMSTATE_END_OF_LIST() 2348 } 2349 }; 2350 2351 static const VMStateDescription vmstate_vmxnet3_rx_stats = { 2352 .name = "vmxnet3-rx-stats", 2353 .version_id = 0, 2354 .fields = (VMStateField[]) { 2355 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats), 2356 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats), 2357 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats), 2358 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats), 2359 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats), 2360 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats), 2361 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats), 2362 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats), 2363 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats), 2364 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats), 2365 VMSTATE_END_OF_LIST() 2366 } 2367 }; 2368 2369 static const VMStateDescription vmstate_vmxnet3_rxq_descr = { 2370 .name = "vmxnet3-rxq-descr", 2371 .version_id = 0, 2372 .fields = (VMStateField[]) { 2373 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr, 2374 VMXNET3_RX_RINGS_PER_QUEUE, 0, 2375 vmstate_vmxnet3_ring, Vmxnet3Ring), 2376 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring, 2377 Vmxnet3Ring), 2378 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr), 2379 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr), 2380 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats, 2381 struct UPT1_RxStats), 2382 VMSTATE_END_OF_LIST() 2383 } 2384 }; 2385 2386 static int vmxnet3_post_load(void *opaque, int version_id) 2387 { 2388 VMXNET3State *s = opaque; 2389 PCIDevice *d = PCI_DEVICE(s); 2390 2391 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s), 2392 s->max_tx_frags, s->peer_has_vhdr); 2393 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr); 2394 2395 if (s->msix_used) { 2396 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) { 2397 VMW_WRPRN("Failed to re-use MSI-X vectors"); 2398 msix_uninit(d, &s->msix_bar, &s->msix_bar); 2399 s->msix_used = false; 2400 return -1; 2401 } 2402 } 2403 2404 vmxnet3_validate_queues(s); 2405 vmxnet3_validate_interrupts(s); 2406 2407 return 0; 2408 } 2409 2410 static const VMStateDescription vmstate_vmxnet3_int_state = { 2411 .name = "vmxnet3-int-state", 2412 .version_id = 0, 2413 .fields = (VMStateField[]) { 2414 VMSTATE_BOOL(is_masked, Vmxnet3IntState), 2415 VMSTATE_BOOL(is_pending, Vmxnet3IntState), 2416 VMSTATE_BOOL(is_asserted, Vmxnet3IntState), 2417 VMSTATE_END_OF_LIST() 2418 } 2419 }; 2420 2421 static const VMStateDescription vmstate_vmxnet3 = { 2422 .name = "vmxnet3", 2423 .version_id = 1, 2424 .minimum_version_id = 1, 2425 .pre_save = vmxnet3_pre_save, 2426 .post_load = vmxnet3_post_load, 2427 .fields = (VMStateField[]) { 2428 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State), 2429 VMSTATE_MSIX(parent_obj, VMXNET3State), 2430 VMSTATE_BOOL(rx_packets_compound, VMXNET3State), 2431 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State), 2432 VMSTATE_BOOL(lro_supported, VMXNET3State), 2433 VMSTATE_UINT32(rx_mode, VMXNET3State), 2434 VMSTATE_UINT32(mcast_list_len, VMXNET3State), 2435 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State), 2436 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE), 2437 VMSTATE_UINT32(mtu, VMXNET3State), 2438 VMSTATE_UINT16(max_rx_frags, VMXNET3State), 2439 VMSTATE_UINT32(max_tx_frags, VMXNET3State), 2440 VMSTATE_UINT8(event_int_idx, VMXNET3State), 2441 VMSTATE_BOOL(auto_int_masking, VMXNET3State), 2442 VMSTATE_UINT8(txq_num, VMXNET3State), 2443 VMSTATE_UINT8(rxq_num, VMXNET3State), 2444 VMSTATE_UINT32(device_active, VMXNET3State), 2445 VMSTATE_UINT32(last_command, VMXNET3State), 2446 VMSTATE_UINT32(link_status_and_speed, VMXNET3State), 2447 VMSTATE_UINT32(temp_mac, VMXNET3State), 2448 VMSTATE_UINT64(drv_shmem, VMXNET3State), 2449 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State), 2450 2451 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State, 2452 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr, 2453 Vmxnet3TxqDescr), 2454 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State, 2455 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr, 2456 Vmxnet3RxqDescr), 2457 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State, 2458 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state, 2459 Vmxnet3IntState), 2460 2461 VMSTATE_END_OF_LIST() 2462 }, 2463 .subsections = (const VMStateDescription*[]) { 2464 &vmxstate_vmxnet3_mcast_list, 2465 NULL 2466 } 2467 }; 2468 2469 static Property vmxnet3_properties[] = { 2470 DEFINE_NIC_PROPERTIES(VMXNET3State, conf), 2471 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags, 2472 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), 2473 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, 2474 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), 2475 DEFINE_PROP_END_OF_LIST(), 2476 }; 2477 2478 static void vmxnet3_realize(DeviceState *qdev, Error **errp) 2479 { 2480 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev); 2481 PCIDevice *pci_dev = PCI_DEVICE(qdev); 2482 VMXNET3State *s = VMXNET3(qdev); 2483 2484 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) { 2485 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2486 } 2487 2488 vc->parent_dc_realize(qdev, errp); 2489 } 2490 2491 static void vmxnet3_class_init(ObjectClass *class, void *data) 2492 { 2493 DeviceClass *dc = DEVICE_CLASS(class); 2494 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 2495 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class); 2496 2497 c->realize = vmxnet3_pci_realize; 2498 c->exit = vmxnet3_pci_uninit; 2499 c->vendor_id = PCI_VENDOR_ID_VMWARE; 2500 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2501 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION; 2502 c->romfile = "efi-vmxnet3.rom"; 2503 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 2504 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; 2505 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3; 2506 device_class_set_parent_realize(dc, vmxnet3_realize, 2507 &vc->parent_dc_realize); 2508 dc->desc = "VMWare Paravirtualized Ethernet v3"; 2509 dc->reset = vmxnet3_qdev_reset; 2510 dc->vmsd = &vmstate_vmxnet3; 2511 device_class_set_props(dc, vmxnet3_properties); 2512 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2513 } 2514 2515 static const TypeInfo vmxnet3_info = { 2516 .name = TYPE_VMXNET3, 2517 .parent = TYPE_PCI_DEVICE, 2518 .class_size = sizeof(VMXNET3Class), 2519 .instance_size = sizeof(VMXNET3State), 2520 .class_init = vmxnet3_class_init, 2521 .instance_init = vmxnet3_instance_init, 2522 .interfaces = (InterfaceInfo[]) { 2523 { INTERFACE_PCIE_DEVICE }, 2524 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2525 { } 2526 }, 2527 }; 2528 2529 static void vmxnet3_register_types(void) 2530 { 2531 VMW_CBPRN("vmxnet3_register_types called..."); 2532 type_register_static(&vmxnet3_info); 2533 } 2534 2535 type_init(vmxnet3_register_types) 2536