1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "qemu/error-report.h" 32 #include "qemu/timer.h" 33 #include "hw/sparc/sun4m_iommu.h" 34 #include "hw/rtc/m48t59.h" 35 #include "migration/vmstate.h" 36 #include "hw/sparc/sparc32_dma.h" 37 #include "hw/block/fdc.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "sysemu/sysemu.h" 41 #include "net/net.h" 42 #include "hw/boards.h" 43 #include "hw/scsi/esp.h" 44 #include "hw/nvram/sun_nvram.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/nvram/chrp_nvram.h" 47 #include "hw/nvram/fw_cfg.h" 48 #include "hw/char/escc.h" 49 #include "hw/misc/empty_slot.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/irq.h" 52 #include "hw/loader.h" 53 #include "elf.h" 54 #include "trace.h" 55 #include "qom/object.h" 56 57 /* 58 * Sun4m architecture was used in the following machines: 59 * 60 * SPARCserver 6xxMP/xx 61 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 62 * SPARCclassic X (4/10) 63 * SPARCstation LX/ZX (4/30) 64 * SPARCstation Voyager 65 * SPARCstation 10/xx, SPARCserver 10/xx 66 * SPARCstation 5, SPARCserver 5 67 * SPARCstation 20/xx, SPARCserver 20 68 * SPARCstation 4 69 * 70 * See for example: http://www.sunhelp.org/faq/sunref1.html 71 */ 72 73 #define KERNEL_LOAD_ADDR 0x00004000 74 #define CMDLINE_ADDR 0x007ff000 75 #define INITRD_LOAD_ADDR 0x00800000 76 #define PROM_SIZE_MAX (1 * MiB) 77 #define PROM_VADDR 0xffd00000 78 #define PROM_FILENAME "openbios-sparc32" 79 #define CFG_ADDR 0xd00000510ULL 80 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 81 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 82 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 83 84 #define MAX_CPUS 16 85 #define MAX_PILS 16 86 #define MAX_VSIMMS 4 87 88 #define ESCC_CLOCK 4915200 89 90 struct sun4m_hwdef { 91 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 92 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 93 hwaddr serial_base, fd_base; 94 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 95 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 96 hwaddr bpp_base, dbri_base, sx_base; 97 struct { 98 hwaddr reg_base, vram_base; 99 } vsimm[MAX_VSIMMS]; 100 hwaddr ecc_base; 101 uint64_t max_mem; 102 uint32_t ecc_version; 103 uint32_t iommu_version; 104 uint16_t machine_id; 105 uint8_t nvram_machine_id; 106 }; 107 108 const char *fw_cfg_arch_key_name(uint16_t key) 109 { 110 static const struct { 111 uint16_t key; 112 const char *name; 113 } fw_cfg_arch_wellknown_keys[] = { 114 {FW_CFG_SUN4M_DEPTH, "depth"}, 115 {FW_CFG_SUN4M_WIDTH, "width"}, 116 {FW_CFG_SUN4M_HEIGHT, "height"}, 117 }; 118 119 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 120 if (fw_cfg_arch_wellknown_keys[i].key == key) { 121 return fw_cfg_arch_wellknown_keys[i].name; 122 } 123 } 124 return NULL; 125 } 126 127 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 128 Error **errp) 129 { 130 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 131 } 132 133 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 134 const char *cmdline, const char *boot_devices, 135 ram_addr_t RAM_size, uint32_t kernel_size, 136 int width, int height, int depth, 137 int nvram_machine_id, const char *arch) 138 { 139 unsigned int i; 140 int sysp_end; 141 uint8_t image[0x1ff0]; 142 NvramClass *k = NVRAM_GET_CLASS(nvram); 143 144 memset(image, '\0', sizeof(image)); 145 146 /* OpenBIOS nvram variables partition */ 147 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 148 149 /* Free space partition */ 150 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 151 152 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 153 nvram_machine_id); 154 155 for (i = 0; i < sizeof(image); i++) { 156 (k->write)(nvram, i, image[i]); 157 } 158 } 159 160 void cpu_check_irqs(CPUSPARCState *env) 161 { 162 CPUState *cs; 163 164 /* We should be holding the BQL before we mess with IRQs */ 165 g_assert(qemu_mutex_iothread_locked()); 166 167 if (env->pil_in && (env->interrupt_index == 0 || 168 (env->interrupt_index & ~15) == TT_EXTINT)) { 169 unsigned int i; 170 171 for (i = 15; i > 0; i--) { 172 if (env->pil_in & (1 << i)) { 173 int old_interrupt = env->interrupt_index; 174 175 env->interrupt_index = TT_EXTINT | i; 176 if (old_interrupt != env->interrupt_index) { 177 cs = env_cpu(env); 178 trace_sun4m_cpu_interrupt(i); 179 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 180 } 181 break; 182 } 183 } 184 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 185 cs = env_cpu(env); 186 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 187 env->interrupt_index = 0; 188 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 189 } 190 } 191 192 static void cpu_kick_irq(SPARCCPU *cpu) 193 { 194 CPUSPARCState *env = &cpu->env; 195 CPUState *cs = CPU(cpu); 196 197 cs->halted = 0; 198 cpu_check_irqs(env); 199 qemu_cpu_kick(cs); 200 } 201 202 static void cpu_set_irq(void *opaque, int irq, int level) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUSPARCState *env = &cpu->env; 206 207 if (level) { 208 trace_sun4m_cpu_set_irq_raise(irq); 209 env->pil_in |= 1 << irq; 210 cpu_kick_irq(cpu); 211 } else { 212 trace_sun4m_cpu_set_irq_lower(irq); 213 env->pil_in &= ~(1 << irq); 214 cpu_check_irqs(env); 215 } 216 } 217 218 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 219 { 220 } 221 222 static void sun4m_cpu_reset(void *opaque) 223 { 224 SPARCCPU *cpu = opaque; 225 CPUState *cs = CPU(cpu); 226 227 cpu_reset(cs); 228 } 229 230 static void cpu_halt_signal(void *opaque, int irq, int level) 231 { 232 if (level && current_cpu) { 233 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 234 } 235 } 236 237 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 238 { 239 return addr - 0xf0000000ULL; 240 } 241 242 static unsigned long sun4m_load_kernel(const char *kernel_filename, 243 const char *initrd_filename, 244 ram_addr_t RAM_size, 245 uint32_t *initrd_size) 246 { 247 int linux_boot; 248 unsigned int i; 249 long kernel_size; 250 uint8_t *ptr; 251 252 linux_boot = (kernel_filename != NULL); 253 254 kernel_size = 0; 255 if (linux_boot) { 256 int bswap_needed; 257 258 #ifdef BSWAP_NEEDED 259 bswap_needed = 1; 260 #else 261 bswap_needed = 0; 262 #endif 263 kernel_size = load_elf(kernel_filename, NULL, 264 translate_kernel_address, NULL, 265 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 266 if (kernel_size < 0) 267 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 268 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 269 TARGET_PAGE_SIZE); 270 if (kernel_size < 0) 271 kernel_size = load_image_targphys(kernel_filename, 272 KERNEL_LOAD_ADDR, 273 RAM_size - KERNEL_LOAD_ADDR); 274 if (kernel_size < 0) { 275 error_report("could not load kernel '%s'", kernel_filename); 276 exit(1); 277 } 278 279 /* load initrd */ 280 *initrd_size = 0; 281 if (initrd_filename) { 282 *initrd_size = load_image_targphys(initrd_filename, 283 INITRD_LOAD_ADDR, 284 RAM_size - INITRD_LOAD_ADDR); 285 if ((int)*initrd_size < 0) { 286 error_report("could not load initial ram disk '%s'", 287 initrd_filename); 288 exit(1); 289 } 290 } 291 if (*initrd_size > 0) { 292 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 293 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 294 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 295 stl_p(ptr + 16, INITRD_LOAD_ADDR); 296 stl_p(ptr + 20, *initrd_size); 297 break; 298 } 299 } 300 } 301 } 302 return kernel_size; 303 } 304 305 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 306 { 307 DeviceState *dev; 308 SysBusDevice *s; 309 310 dev = qdev_new(TYPE_SUN4M_IOMMU); 311 qdev_prop_set_uint32(dev, "version", version); 312 s = SYS_BUS_DEVICE(dev); 313 sysbus_realize_and_unref(s, &error_fatal); 314 sysbus_connect_irq(s, 0, irq); 315 sysbus_mmio_map(s, 0, addr); 316 317 return s; 318 } 319 320 static void *sparc32_dma_init(hwaddr dma_base, 321 hwaddr esp_base, qemu_irq espdma_irq, 322 hwaddr le_base, qemu_irq ledma_irq) 323 { 324 DeviceState *dma; 325 ESPDMADeviceState *espdma; 326 LEDMADeviceState *ledma; 327 SysBusESPState *esp; 328 SysBusPCNetState *lance; 329 330 dma = qdev_new(TYPE_SPARC32_DMA); 331 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 332 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 333 334 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 335 OBJECT(dma), "espdma")); 336 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 337 338 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp")); 339 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 340 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 341 342 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 343 OBJECT(dma), "ledma")); 344 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 345 346 lance = SYSBUS_PCNET(object_resolve_path_component( 347 OBJECT(ledma), "lance")); 348 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 349 350 return dma; 351 } 352 353 static DeviceState *slavio_intctl_init(hwaddr addr, 354 hwaddr addrg, 355 qemu_irq **parent_irq) 356 { 357 DeviceState *dev; 358 SysBusDevice *s; 359 unsigned int i, j; 360 361 dev = qdev_new("slavio_intctl"); 362 363 s = SYS_BUS_DEVICE(dev); 364 sysbus_realize_and_unref(s, &error_fatal); 365 366 for (i = 0; i < MAX_CPUS; i++) { 367 for (j = 0; j < MAX_PILS; j++) { 368 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 369 } 370 } 371 sysbus_mmio_map(s, 0, addrg); 372 for (i = 0; i < MAX_CPUS; i++) { 373 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 374 } 375 376 return dev; 377 } 378 379 #define SYS_TIMER_OFFSET 0x10000ULL 380 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 381 382 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 383 qemu_irq *cpu_irqs, unsigned int num_cpus) 384 { 385 DeviceState *dev; 386 SysBusDevice *s; 387 unsigned int i; 388 389 dev = qdev_new("slavio_timer"); 390 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 391 s = SYS_BUS_DEVICE(dev); 392 sysbus_realize_and_unref(s, &error_fatal); 393 sysbus_connect_irq(s, 0, master_irq); 394 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 395 396 for (i = 0; i < MAX_CPUS; i++) { 397 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 398 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 399 } 400 } 401 402 static qemu_irq slavio_system_powerdown; 403 404 static void slavio_powerdown_req(Notifier *n, void *opaque) 405 { 406 qemu_irq_raise(slavio_system_powerdown); 407 } 408 409 static Notifier slavio_system_powerdown_notifier = { 410 .notify = slavio_powerdown_req 411 }; 412 413 #define MISC_LEDS 0x01600000 414 #define MISC_CFG 0x01800000 415 #define MISC_DIAG 0x01a00000 416 #define MISC_MDM 0x01b00000 417 #define MISC_SYS 0x01f00000 418 419 static void slavio_misc_init(hwaddr base, 420 hwaddr aux1_base, 421 hwaddr aux2_base, qemu_irq irq, 422 qemu_irq fdc_tc) 423 { 424 DeviceState *dev; 425 SysBusDevice *s; 426 427 dev = qdev_new("slavio_misc"); 428 s = SYS_BUS_DEVICE(dev); 429 sysbus_realize_and_unref(s, &error_fatal); 430 if (base) { 431 /* 8 bit registers */ 432 /* Slavio control */ 433 sysbus_mmio_map(s, 0, base + MISC_CFG); 434 /* Diagnostics */ 435 sysbus_mmio_map(s, 1, base + MISC_DIAG); 436 /* Modem control */ 437 sysbus_mmio_map(s, 2, base + MISC_MDM); 438 /* 16 bit registers */ 439 /* ss600mp diag LEDs */ 440 sysbus_mmio_map(s, 3, base + MISC_LEDS); 441 /* 32 bit registers */ 442 /* System control */ 443 sysbus_mmio_map(s, 4, base + MISC_SYS); 444 } 445 if (aux1_base) { 446 /* AUX 1 (Misc System Functions) */ 447 sysbus_mmio_map(s, 5, aux1_base); 448 } 449 if (aux2_base) { 450 /* AUX 2 (Software Powerdown Control) */ 451 sysbus_mmio_map(s, 6, aux2_base); 452 } 453 sysbus_connect_irq(s, 0, irq); 454 sysbus_connect_irq(s, 1, fdc_tc); 455 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 456 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 457 } 458 459 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 460 { 461 DeviceState *dev; 462 SysBusDevice *s; 463 464 dev = qdev_new("eccmemctl"); 465 qdev_prop_set_uint32(dev, "version", version); 466 s = SYS_BUS_DEVICE(dev); 467 sysbus_realize_and_unref(s, &error_fatal); 468 sysbus_connect_irq(s, 0, irq); 469 sysbus_mmio_map(s, 0, base); 470 if (version == 0) { // SS-600MP only 471 sysbus_mmio_map(s, 1, base + 0x1000); 472 } 473 } 474 475 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 476 { 477 DeviceState *dev; 478 SysBusDevice *s; 479 480 dev = qdev_new("apc"); 481 s = SYS_BUS_DEVICE(dev); 482 sysbus_realize_and_unref(s, &error_fatal); 483 /* Power management (APC) XXX: not a Slavio device */ 484 sysbus_mmio_map(s, 0, power_base); 485 sysbus_connect_irq(s, 0, cpu_halt); 486 } 487 488 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 489 int height, int depth) 490 { 491 DeviceState *dev; 492 SysBusDevice *s; 493 494 dev = qdev_new("SUNW,tcx"); 495 qdev_prop_set_uint32(dev, "vram_size", vram_size); 496 qdev_prop_set_uint16(dev, "width", width); 497 qdev_prop_set_uint16(dev, "height", height); 498 qdev_prop_set_uint16(dev, "depth", depth); 499 s = SYS_BUS_DEVICE(dev); 500 sysbus_realize_and_unref(s, &error_fatal); 501 502 /* 10/ROM : FCode ROM */ 503 sysbus_mmio_map(s, 0, addr); 504 /* 2/STIP : Stipple */ 505 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 506 /* 3/BLIT : Blitter */ 507 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 508 /* 5/RSTIP : Raw Stipple */ 509 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 510 /* 6/RBLIT : Raw Blitter */ 511 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 512 /* 7/TEC : Transform Engine */ 513 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 514 /* 8/CMAP : DAC */ 515 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 516 /* 9/THC : */ 517 if (depth == 8) { 518 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 519 } else { 520 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 521 } 522 /* 11/DHC : */ 523 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 524 /* 12/ALT : */ 525 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 526 /* 0/DFB8 : 8-bit plane */ 527 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 528 /* 1/DFB24 : 24bit plane */ 529 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 530 /* 4/RDFB32: Raw framebuffer. Control plane */ 531 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 532 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 533 if (depth == 8) { 534 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 535 } 536 537 sysbus_connect_irq(s, 0, irq); 538 } 539 540 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 541 int height, int depth) 542 { 543 DeviceState *dev; 544 SysBusDevice *s; 545 546 dev = qdev_new("cgthree"); 547 qdev_prop_set_uint32(dev, "vram-size", vram_size); 548 qdev_prop_set_uint16(dev, "width", width); 549 qdev_prop_set_uint16(dev, "height", height); 550 qdev_prop_set_uint16(dev, "depth", depth); 551 s = SYS_BUS_DEVICE(dev); 552 sysbus_realize_and_unref(s, &error_fatal); 553 554 /* FCode ROM */ 555 sysbus_mmio_map(s, 0, addr); 556 /* DAC */ 557 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 558 /* 8-bit plane */ 559 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 560 561 sysbus_connect_irq(s, 0, irq); 562 } 563 564 /* NCR89C100/MACIO Internal ID register */ 565 566 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 567 568 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 569 570 static void idreg_init(hwaddr addr) 571 { 572 DeviceState *dev; 573 SysBusDevice *s; 574 575 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 576 s = SYS_BUS_DEVICE(dev); 577 sysbus_realize_and_unref(s, &error_fatal); 578 579 sysbus_mmio_map(s, 0, addr); 580 address_space_write_rom(&address_space_memory, addr, 581 MEMTXATTRS_UNSPECIFIED, 582 idreg_data, sizeof(idreg_data)); 583 } 584 585 typedef struct IDRegState IDRegState; 586 #define MACIO_ID_REGISTER(obj) \ 587 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) 588 589 struct IDRegState { 590 SysBusDevice parent_obj; 591 592 MemoryRegion mem; 593 }; 594 595 static void idreg_realize(DeviceState *ds, Error **errp) 596 { 597 IDRegState *s = MACIO_ID_REGISTER(ds); 598 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 599 Error *local_err = NULL; 600 601 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 602 sizeof(idreg_data), &local_err); 603 if (local_err) { 604 error_propagate(errp, local_err); 605 return; 606 } 607 608 vmstate_register_ram_global(&s->mem); 609 memory_region_set_readonly(&s->mem, true); 610 sysbus_init_mmio(dev, &s->mem); 611 } 612 613 static void idreg_class_init(ObjectClass *oc, void *data) 614 { 615 DeviceClass *dc = DEVICE_CLASS(oc); 616 617 dc->realize = idreg_realize; 618 } 619 620 static const TypeInfo idreg_info = { 621 .name = TYPE_MACIO_ID_REGISTER, 622 .parent = TYPE_SYS_BUS_DEVICE, 623 .instance_size = sizeof(IDRegState), 624 .class_init = idreg_class_init, 625 }; 626 627 #define TYPE_TCX_AFX "tcx_afx" 628 typedef struct AFXState AFXState; 629 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) 630 631 struct AFXState { 632 SysBusDevice parent_obj; 633 634 MemoryRegion mem; 635 }; 636 637 /* SS-5 TCX AFX register */ 638 static void afx_init(hwaddr addr) 639 { 640 DeviceState *dev; 641 SysBusDevice *s; 642 643 dev = qdev_new(TYPE_TCX_AFX); 644 s = SYS_BUS_DEVICE(dev); 645 sysbus_realize_and_unref(s, &error_fatal); 646 647 sysbus_mmio_map(s, 0, addr); 648 } 649 650 static void afx_realize(DeviceState *ds, Error **errp) 651 { 652 AFXState *s = TCX_AFX(ds); 653 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 654 Error *local_err = NULL; 655 656 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 657 &local_err); 658 if (local_err) { 659 error_propagate(errp, local_err); 660 return; 661 } 662 663 vmstate_register_ram_global(&s->mem); 664 sysbus_init_mmio(dev, &s->mem); 665 } 666 667 static void afx_class_init(ObjectClass *oc, void *data) 668 { 669 DeviceClass *dc = DEVICE_CLASS(oc); 670 671 dc->realize = afx_realize; 672 } 673 674 static const TypeInfo afx_info = { 675 .name = TYPE_TCX_AFX, 676 .parent = TYPE_SYS_BUS_DEVICE, 677 .instance_size = sizeof(AFXState), 678 .class_init = afx_class_init, 679 }; 680 681 #define TYPE_OPENPROM "openprom" 682 typedef struct PROMState PROMState; 683 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 684 685 struct PROMState { 686 SysBusDevice parent_obj; 687 688 MemoryRegion prom; 689 }; 690 691 /* Boot PROM (OpenBIOS) */ 692 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 693 { 694 hwaddr *base_addr = (hwaddr *)opaque; 695 return addr + *base_addr - PROM_VADDR; 696 } 697 698 static void prom_init(hwaddr addr, const char *bios_name) 699 { 700 DeviceState *dev; 701 SysBusDevice *s; 702 char *filename; 703 int ret; 704 705 dev = qdev_new(TYPE_OPENPROM); 706 s = SYS_BUS_DEVICE(dev); 707 sysbus_realize_and_unref(s, &error_fatal); 708 709 sysbus_mmio_map(s, 0, addr); 710 711 /* load boot prom */ 712 if (bios_name == NULL) { 713 bios_name = PROM_FILENAME; 714 } 715 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 716 if (filename) { 717 ret = load_elf(filename, NULL, 718 translate_prom_address, &addr, NULL, 719 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 720 if (ret < 0 || ret > PROM_SIZE_MAX) { 721 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 722 } 723 g_free(filename); 724 } else { 725 ret = -1; 726 } 727 if (ret < 0 || ret > PROM_SIZE_MAX) { 728 error_report("could not load prom '%s'", bios_name); 729 exit(1); 730 } 731 } 732 733 static void prom_realize(DeviceState *ds, Error **errp) 734 { 735 PROMState *s = OPENPROM(ds); 736 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 737 Error *local_err = NULL; 738 739 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 740 PROM_SIZE_MAX, &local_err); 741 if (local_err) { 742 error_propagate(errp, local_err); 743 return; 744 } 745 746 vmstate_register_ram_global(&s->prom); 747 memory_region_set_readonly(&s->prom, true); 748 sysbus_init_mmio(dev, &s->prom); 749 } 750 751 static Property prom_properties[] = { 752 {/* end of property list */}, 753 }; 754 755 static void prom_class_init(ObjectClass *klass, void *data) 756 { 757 DeviceClass *dc = DEVICE_CLASS(klass); 758 759 device_class_set_props(dc, prom_properties); 760 dc->realize = prom_realize; 761 } 762 763 static const TypeInfo prom_info = { 764 .name = TYPE_OPENPROM, 765 .parent = TYPE_SYS_BUS_DEVICE, 766 .instance_size = sizeof(PROMState), 767 .class_init = prom_class_init, 768 }; 769 770 #define TYPE_SUN4M_MEMORY "memory" 771 typedef struct RamDevice RamDevice; 772 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) 773 774 struct RamDevice { 775 SysBusDevice parent_obj; 776 HostMemoryBackend *memdev; 777 }; 778 779 /* System RAM */ 780 static void ram_realize(DeviceState *dev, Error **errp) 781 { 782 RamDevice *d = SUN4M_RAM(dev); 783 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 784 785 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 786 } 787 788 static void ram_initfn(Object *obj) 789 { 790 RamDevice *d = SUN4M_RAM(obj); 791 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 792 (Object **)&d->memdev, 793 object_property_allow_set_link, 794 OBJ_PROP_LINK_STRONG); 795 object_property_set_description(obj, "memdev", "Set RAM backend" 796 "Valid value is ID of a hostmem backend"); 797 } 798 799 static void ram_class_init(ObjectClass *klass, void *data) 800 { 801 DeviceClass *dc = DEVICE_CLASS(klass); 802 803 dc->realize = ram_realize; 804 } 805 806 static const TypeInfo ram_info = { 807 .name = TYPE_SUN4M_MEMORY, 808 .parent = TYPE_SYS_BUS_DEVICE, 809 .instance_size = sizeof(RamDevice), 810 .instance_init = ram_initfn, 811 .class_init = ram_class_init, 812 }; 813 814 static void cpu_devinit(const char *cpu_type, unsigned int id, 815 uint64_t prom_addr, qemu_irq **cpu_irqs) 816 { 817 SPARCCPU *cpu; 818 CPUSPARCState *env; 819 820 cpu = SPARC_CPU(object_new(cpu_type)); 821 env = &cpu->env; 822 823 cpu_sparc_set_id(env, id); 824 qemu_register_reset(sun4m_cpu_reset, cpu); 825 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 826 &error_fatal); 827 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 828 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 829 env->prom_addr = prom_addr; 830 } 831 832 static void dummy_fdc_tc(void *opaque, int irq, int level) 833 { 834 } 835 836 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 837 MachineState *machine) 838 { 839 DeviceState *slavio_intctl; 840 unsigned int i; 841 void *nvram; 842 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 843 qemu_irq fdc_tc; 844 unsigned long kernel_size; 845 uint32_t initrd_size; 846 DriveInfo *fd[MAX_FD]; 847 FWCfgState *fw_cfg; 848 DeviceState *dev; 849 SysBusDevice *s; 850 unsigned int smp_cpus = machine->smp.cpus; 851 unsigned int max_cpus = machine->smp.max_cpus; 852 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, 853 TYPE_MEMORY_BACKEND, NULL); 854 855 if (machine->ram_size > hwdef->max_mem) { 856 error_report("Too much memory for this machine: %" PRId64 "," 857 " maximum %" PRId64, 858 machine->ram_size / MiB, hwdef->max_mem / MiB); 859 exit(1); 860 } 861 862 /* init CPUs */ 863 for(i = 0; i < smp_cpus; i++) { 864 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 865 } 866 867 for (i = smp_cpus; i < MAX_CPUS; i++) 868 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 869 870 /* Create and map RAM frontend */ 871 dev = qdev_new("memory"); 872 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); 873 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 874 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 875 876 /* models without ECC don't trap when missing ram is accessed */ 877 if (!hwdef->ecc_base) { 878 empty_slot_init("ecc", machine->ram_size, 879 hwdef->max_mem - machine->ram_size); 880 } 881 882 prom_init(hwdef->slavio_base, bios_name); 883 884 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 885 hwdef->intctl_base + 0x10000ULL, 886 cpu_irqs); 887 888 for (i = 0; i < 32; i++) { 889 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 890 } 891 for (i = 0; i < MAX_CPUS; i++) { 892 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 893 } 894 895 if (hwdef->idreg_base) { 896 idreg_init(hwdef->idreg_base); 897 } 898 899 if (hwdef->afx_base) { 900 afx_init(hwdef->afx_base); 901 } 902 903 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 904 905 if (hwdef->iommu_pad_base) { 906 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 907 Software shouldn't use aliased addresses, neither should it crash 908 when does. Using empty_slot instead of aliasing can help with 909 debugging such accesses */ 910 empty_slot_init("iommu.alias", 911 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 912 } 913 914 sparc32_dma_init(hwdef->dma_base, 915 hwdef->esp_base, slavio_irq[18], 916 hwdef->le_base, slavio_irq[16]); 917 918 if (graphic_depth != 8 && graphic_depth != 24) { 919 error_report("Unsupported depth: %d", graphic_depth); 920 exit (1); 921 } 922 if (vga_interface_type != VGA_NONE) { 923 if (vga_interface_type == VGA_CG3) { 924 if (graphic_depth != 8) { 925 error_report("Unsupported depth: %d", graphic_depth); 926 exit(1); 927 } 928 929 if (!(graphic_width == 1024 && graphic_height == 768) && 930 !(graphic_width == 1152 && graphic_height == 900)) { 931 error_report("Unsupported resolution: %d x %d", graphic_width, 932 graphic_height); 933 exit(1); 934 } 935 936 /* sbus irq 5 */ 937 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 938 graphic_width, graphic_height, graphic_depth); 939 } else { 940 /* If no display specified, default to TCX */ 941 if (graphic_depth != 8 && graphic_depth != 24) { 942 error_report("Unsupported depth: %d", graphic_depth); 943 exit(1); 944 } 945 946 if (!(graphic_width == 1024 && graphic_height == 768)) { 947 error_report("Unsupported resolution: %d x %d", 948 graphic_width, graphic_height); 949 exit(1); 950 } 951 952 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 953 graphic_width, graphic_height, graphic_depth); 954 } 955 } 956 957 for (i = 0; i < MAX_VSIMMS; i++) { 958 /* vsimm registers probed by OBP */ 959 if (hwdef->vsimm[i].reg_base) { 960 char *name = g_strdup_printf("vsimm[%d]", i); 961 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 962 g_free(name); 963 } 964 } 965 966 if (hwdef->sx_base) { 967 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000); 968 } 969 970 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); 971 972 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 973 974 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 975 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 976 dev = qdev_new(TYPE_ESCC); 977 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 978 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 979 qdev_prop_set_uint32(dev, "it_shift", 1); 980 qdev_prop_set_chr(dev, "chrB", NULL); 981 qdev_prop_set_chr(dev, "chrA", NULL); 982 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 983 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 984 s = SYS_BUS_DEVICE(dev); 985 sysbus_realize_and_unref(s, &error_fatal); 986 sysbus_connect_irq(s, 0, slavio_irq[14]); 987 sysbus_connect_irq(s, 1, slavio_irq[14]); 988 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 989 990 dev = qdev_new(TYPE_ESCC); 991 qdev_prop_set_uint32(dev, "disabled", 0); 992 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 993 qdev_prop_set_uint32(dev, "it_shift", 1); 994 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 995 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 996 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 997 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 998 999 s = SYS_BUS_DEVICE(dev); 1000 sysbus_realize_and_unref(s, &error_fatal); 1001 sysbus_connect_irq(s, 0, slavio_irq[15]); 1002 sysbus_connect_irq(s, 1, slavio_irq[15]); 1003 sysbus_mmio_map(s, 0, hwdef->serial_base); 1004 1005 if (hwdef->apc_base) { 1006 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1007 } 1008 1009 if (hwdef->fd_base) { 1010 /* there is zero or one floppy drive */ 1011 memset(fd, 0, sizeof(fd)); 1012 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1013 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1014 &fdc_tc); 1015 } else { 1016 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1017 } 1018 1019 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1020 slavio_irq[30], fdc_tc); 1021 1022 if (hwdef->cs_base) { 1023 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1024 slavio_irq[5]); 1025 } 1026 1027 if (hwdef->dbri_base) { 1028 /* ISDN chip with attached CS4215 audio codec */ 1029 /* prom space */ 1030 create_unimplemented_device("SUNW,DBRI.prom", 1031 hwdef->dbri_base + 0x1000, 0x30); 1032 /* reg space */ 1033 create_unimplemented_device("SUNW,DBRI", 1034 hwdef->dbri_base + 0x10000, 0x100); 1035 } 1036 1037 if (hwdef->bpp_base) { 1038 /* parallel port */ 1039 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20); 1040 } 1041 1042 initrd_size = 0; 1043 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1044 machine->initrd_filename, 1045 machine->ram_size, &initrd_size); 1046 1047 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, 1048 machine->boot_order, machine->ram_size, kernel_size, 1049 graphic_width, graphic_height, graphic_depth, 1050 hwdef->nvram_machine_id, "Sun4m"); 1051 1052 if (hwdef->ecc_base) 1053 ecc_init(hwdef->ecc_base, slavio_irq[28], 1054 hwdef->ecc_version); 1055 1056 dev = qdev_new(TYPE_FW_CFG_MEM); 1057 fw_cfg = FW_CFG(dev); 1058 qdev_prop_set_uint32(dev, "data_width", 1); 1059 qdev_prop_set_bit(dev, "dma_enabled", false); 1060 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1061 OBJECT(fw_cfg)); 1062 s = SYS_BUS_DEVICE(dev); 1063 sysbus_realize_and_unref(s, &error_fatal); 1064 sysbus_mmio_map(s, 0, CFG_ADDR); 1065 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1066 1067 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1068 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1069 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1070 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1071 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1073 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1074 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1075 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1076 if (machine->kernel_cmdline) { 1077 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1078 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1079 machine->kernel_cmdline); 1080 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1081 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1082 strlen(machine->kernel_cmdline) + 1); 1083 } else { 1084 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1085 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1086 } 1087 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1088 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1089 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1090 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1091 } 1092 1093 enum { 1094 ss5_id = 32, 1095 vger_id, 1096 lx_id, 1097 ss4_id, 1098 scls_id, 1099 sbook_id, 1100 ss10_id = 64, 1101 ss20_id, 1102 ss600mp_id, 1103 }; 1104 1105 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1106 /* SS-5 */ 1107 { 1108 .iommu_base = 0x10000000, 1109 .iommu_pad_base = 0x10004000, 1110 .iommu_pad_len = 0x0fffb000, 1111 .tcx_base = 0x50000000, 1112 .cs_base = 0x6c000000, 1113 .slavio_base = 0x70000000, 1114 .ms_kb_base = 0x71000000, 1115 .serial_base = 0x71100000, 1116 .nvram_base = 0x71200000, 1117 .fd_base = 0x71400000, 1118 .counter_base = 0x71d00000, 1119 .intctl_base = 0x71e00000, 1120 .idreg_base = 0x78000000, 1121 .dma_base = 0x78400000, 1122 .esp_base = 0x78800000, 1123 .le_base = 0x78c00000, 1124 .apc_base = 0x6a000000, 1125 .afx_base = 0x6e000000, 1126 .aux1_base = 0x71900000, 1127 .aux2_base = 0x71910000, 1128 .nvram_machine_id = 0x80, 1129 .machine_id = ss5_id, 1130 .iommu_version = 0x05000000, 1131 .max_mem = 0x10000000, 1132 }, 1133 /* SS-10 */ 1134 { 1135 .iommu_base = 0xfe0000000ULL, 1136 .tcx_base = 0xe20000000ULL, 1137 .slavio_base = 0xff0000000ULL, 1138 .ms_kb_base = 0xff1000000ULL, 1139 .serial_base = 0xff1100000ULL, 1140 .nvram_base = 0xff1200000ULL, 1141 .fd_base = 0xff1700000ULL, 1142 .counter_base = 0xff1300000ULL, 1143 .intctl_base = 0xff1400000ULL, 1144 .idreg_base = 0xef0000000ULL, 1145 .dma_base = 0xef0400000ULL, 1146 .esp_base = 0xef0800000ULL, 1147 .le_base = 0xef0c00000ULL, 1148 .apc_base = 0xefa000000ULL, // XXX should not exist 1149 .aux1_base = 0xff1800000ULL, 1150 .aux2_base = 0xff1a01000ULL, 1151 .ecc_base = 0xf00000000ULL, 1152 .ecc_version = 0x10000000, // version 0, implementation 1 1153 .nvram_machine_id = 0x72, 1154 .machine_id = ss10_id, 1155 .iommu_version = 0x03000000, 1156 .max_mem = 0xf00000000ULL, 1157 }, 1158 /* SS-600MP */ 1159 { 1160 .iommu_base = 0xfe0000000ULL, 1161 .tcx_base = 0xe20000000ULL, 1162 .slavio_base = 0xff0000000ULL, 1163 .ms_kb_base = 0xff1000000ULL, 1164 .serial_base = 0xff1100000ULL, 1165 .nvram_base = 0xff1200000ULL, 1166 .counter_base = 0xff1300000ULL, 1167 .intctl_base = 0xff1400000ULL, 1168 .dma_base = 0xef0081000ULL, 1169 .esp_base = 0xef0080000ULL, 1170 .le_base = 0xef0060000ULL, 1171 .apc_base = 0xefa000000ULL, // XXX should not exist 1172 .aux1_base = 0xff1800000ULL, 1173 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1174 .ecc_base = 0xf00000000ULL, 1175 .ecc_version = 0x00000000, // version 0, implementation 0 1176 .nvram_machine_id = 0x71, 1177 .machine_id = ss600mp_id, 1178 .iommu_version = 0x01000000, 1179 .max_mem = 0xf00000000ULL, 1180 }, 1181 /* SS-20 */ 1182 { 1183 .iommu_base = 0xfe0000000ULL, 1184 .tcx_base = 0xe20000000ULL, 1185 .slavio_base = 0xff0000000ULL, 1186 .ms_kb_base = 0xff1000000ULL, 1187 .serial_base = 0xff1100000ULL, 1188 .nvram_base = 0xff1200000ULL, 1189 .fd_base = 0xff1700000ULL, 1190 .counter_base = 0xff1300000ULL, 1191 .intctl_base = 0xff1400000ULL, 1192 .idreg_base = 0xef0000000ULL, 1193 .dma_base = 0xef0400000ULL, 1194 .esp_base = 0xef0800000ULL, 1195 .le_base = 0xef0c00000ULL, 1196 .bpp_base = 0xef4800000ULL, 1197 .apc_base = 0xefa000000ULL, // XXX should not exist 1198 .aux1_base = 0xff1800000ULL, 1199 .aux2_base = 0xff1a01000ULL, 1200 .dbri_base = 0xee0000000ULL, 1201 .sx_base = 0xf80000000ULL, 1202 .vsimm = { 1203 { 1204 .reg_base = 0x9c000000ULL, 1205 .vram_base = 0xfc000000ULL 1206 }, { 1207 .reg_base = 0x90000000ULL, 1208 .vram_base = 0xf0000000ULL 1209 }, { 1210 .reg_base = 0x94000000ULL 1211 }, { 1212 .reg_base = 0x98000000ULL 1213 } 1214 }, 1215 .ecc_base = 0xf00000000ULL, 1216 .ecc_version = 0x20000000, // version 0, implementation 2 1217 .nvram_machine_id = 0x72, 1218 .machine_id = ss20_id, 1219 .iommu_version = 0x13000000, 1220 .max_mem = 0xf00000000ULL, 1221 }, 1222 /* Voyager */ 1223 { 1224 .iommu_base = 0x10000000, 1225 .tcx_base = 0x50000000, 1226 .slavio_base = 0x70000000, 1227 .ms_kb_base = 0x71000000, 1228 .serial_base = 0x71100000, 1229 .nvram_base = 0x71200000, 1230 .fd_base = 0x71400000, 1231 .counter_base = 0x71d00000, 1232 .intctl_base = 0x71e00000, 1233 .idreg_base = 0x78000000, 1234 .dma_base = 0x78400000, 1235 .esp_base = 0x78800000, 1236 .le_base = 0x78c00000, 1237 .apc_base = 0x71300000, // pmc 1238 .aux1_base = 0x71900000, 1239 .aux2_base = 0x71910000, 1240 .nvram_machine_id = 0x80, 1241 .machine_id = vger_id, 1242 .iommu_version = 0x05000000, 1243 .max_mem = 0x10000000, 1244 }, 1245 /* LX */ 1246 { 1247 .iommu_base = 0x10000000, 1248 .iommu_pad_base = 0x10004000, 1249 .iommu_pad_len = 0x0fffb000, 1250 .tcx_base = 0x50000000, 1251 .slavio_base = 0x70000000, 1252 .ms_kb_base = 0x71000000, 1253 .serial_base = 0x71100000, 1254 .nvram_base = 0x71200000, 1255 .fd_base = 0x71400000, 1256 .counter_base = 0x71d00000, 1257 .intctl_base = 0x71e00000, 1258 .idreg_base = 0x78000000, 1259 .dma_base = 0x78400000, 1260 .esp_base = 0x78800000, 1261 .le_base = 0x78c00000, 1262 .aux1_base = 0x71900000, 1263 .aux2_base = 0x71910000, 1264 .nvram_machine_id = 0x80, 1265 .machine_id = lx_id, 1266 .iommu_version = 0x04000000, 1267 .max_mem = 0x10000000, 1268 }, 1269 /* SS-4 */ 1270 { 1271 .iommu_base = 0x10000000, 1272 .tcx_base = 0x50000000, 1273 .cs_base = 0x6c000000, 1274 .slavio_base = 0x70000000, 1275 .ms_kb_base = 0x71000000, 1276 .serial_base = 0x71100000, 1277 .nvram_base = 0x71200000, 1278 .fd_base = 0x71400000, 1279 .counter_base = 0x71d00000, 1280 .intctl_base = 0x71e00000, 1281 .idreg_base = 0x78000000, 1282 .dma_base = 0x78400000, 1283 .esp_base = 0x78800000, 1284 .le_base = 0x78c00000, 1285 .apc_base = 0x6a000000, 1286 .aux1_base = 0x71900000, 1287 .aux2_base = 0x71910000, 1288 .nvram_machine_id = 0x80, 1289 .machine_id = ss4_id, 1290 .iommu_version = 0x05000000, 1291 .max_mem = 0x10000000, 1292 }, 1293 /* SPARCClassic */ 1294 { 1295 .iommu_base = 0x10000000, 1296 .tcx_base = 0x50000000, 1297 .slavio_base = 0x70000000, 1298 .ms_kb_base = 0x71000000, 1299 .serial_base = 0x71100000, 1300 .nvram_base = 0x71200000, 1301 .fd_base = 0x71400000, 1302 .counter_base = 0x71d00000, 1303 .intctl_base = 0x71e00000, 1304 .idreg_base = 0x78000000, 1305 .dma_base = 0x78400000, 1306 .esp_base = 0x78800000, 1307 .le_base = 0x78c00000, 1308 .apc_base = 0x6a000000, 1309 .aux1_base = 0x71900000, 1310 .aux2_base = 0x71910000, 1311 .nvram_machine_id = 0x80, 1312 .machine_id = scls_id, 1313 .iommu_version = 0x05000000, 1314 .max_mem = 0x10000000, 1315 }, 1316 /* SPARCbook */ 1317 { 1318 .iommu_base = 0x10000000, 1319 .tcx_base = 0x50000000, // XXX 1320 .slavio_base = 0x70000000, 1321 .ms_kb_base = 0x71000000, 1322 .serial_base = 0x71100000, 1323 .nvram_base = 0x71200000, 1324 .fd_base = 0x71400000, 1325 .counter_base = 0x71d00000, 1326 .intctl_base = 0x71e00000, 1327 .idreg_base = 0x78000000, 1328 .dma_base = 0x78400000, 1329 .esp_base = 0x78800000, 1330 .le_base = 0x78c00000, 1331 .apc_base = 0x6a000000, 1332 .aux1_base = 0x71900000, 1333 .aux2_base = 0x71910000, 1334 .nvram_machine_id = 0x80, 1335 .machine_id = sbook_id, 1336 .iommu_version = 0x05000000, 1337 .max_mem = 0x10000000, 1338 }, 1339 }; 1340 1341 /* SPARCstation 5 hardware initialisation */ 1342 static void ss5_init(MachineState *machine) 1343 { 1344 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1345 } 1346 1347 /* SPARCstation 10 hardware initialisation */ 1348 static void ss10_init(MachineState *machine) 1349 { 1350 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1351 } 1352 1353 /* SPARCserver 600MP hardware initialisation */ 1354 static void ss600mp_init(MachineState *machine) 1355 { 1356 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1357 } 1358 1359 /* SPARCstation 20 hardware initialisation */ 1360 static void ss20_init(MachineState *machine) 1361 { 1362 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1363 } 1364 1365 /* SPARCstation Voyager hardware initialisation */ 1366 static void vger_init(MachineState *machine) 1367 { 1368 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1369 } 1370 1371 /* SPARCstation LX hardware initialisation */ 1372 static void ss_lx_init(MachineState *machine) 1373 { 1374 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1375 } 1376 1377 /* SPARCstation 4 hardware initialisation */ 1378 static void ss4_init(MachineState *machine) 1379 { 1380 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1381 } 1382 1383 /* SPARCClassic hardware initialisation */ 1384 static void scls_init(MachineState *machine) 1385 { 1386 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1387 } 1388 1389 /* SPARCbook hardware initialisation */ 1390 static void sbook_init(MachineState *machine) 1391 { 1392 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1393 } 1394 1395 static void ss5_class_init(ObjectClass *oc, void *data) 1396 { 1397 MachineClass *mc = MACHINE_CLASS(oc); 1398 1399 mc->desc = "Sun4m platform, SPARCstation 5"; 1400 mc->init = ss5_init; 1401 mc->block_default_type = IF_SCSI; 1402 mc->is_default = true; 1403 mc->default_boot_order = "c"; 1404 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1405 mc->default_display = "tcx"; 1406 mc->default_ram_id = "sun4m.ram"; 1407 } 1408 1409 static const TypeInfo ss5_type = { 1410 .name = MACHINE_TYPE_NAME("SS-5"), 1411 .parent = TYPE_MACHINE, 1412 .class_init = ss5_class_init, 1413 }; 1414 1415 static void ss10_class_init(ObjectClass *oc, void *data) 1416 { 1417 MachineClass *mc = MACHINE_CLASS(oc); 1418 1419 mc->desc = "Sun4m platform, SPARCstation 10"; 1420 mc->init = ss10_init; 1421 mc->block_default_type = IF_SCSI; 1422 mc->max_cpus = 4; 1423 mc->default_boot_order = "c"; 1424 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1425 mc->default_display = "tcx"; 1426 mc->default_ram_id = "sun4m.ram"; 1427 } 1428 1429 static const TypeInfo ss10_type = { 1430 .name = MACHINE_TYPE_NAME("SS-10"), 1431 .parent = TYPE_MACHINE, 1432 .class_init = ss10_class_init, 1433 }; 1434 1435 static void ss600mp_class_init(ObjectClass *oc, void *data) 1436 { 1437 MachineClass *mc = MACHINE_CLASS(oc); 1438 1439 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1440 mc->init = ss600mp_init; 1441 mc->block_default_type = IF_SCSI; 1442 mc->max_cpus = 4; 1443 mc->default_boot_order = "c"; 1444 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1445 mc->default_display = "tcx"; 1446 mc->default_ram_id = "sun4m.ram"; 1447 } 1448 1449 static const TypeInfo ss600mp_type = { 1450 .name = MACHINE_TYPE_NAME("SS-600MP"), 1451 .parent = TYPE_MACHINE, 1452 .class_init = ss600mp_class_init, 1453 }; 1454 1455 static void ss20_class_init(ObjectClass *oc, void *data) 1456 { 1457 MachineClass *mc = MACHINE_CLASS(oc); 1458 1459 mc->desc = "Sun4m platform, SPARCstation 20"; 1460 mc->init = ss20_init; 1461 mc->block_default_type = IF_SCSI; 1462 mc->max_cpus = 4; 1463 mc->default_boot_order = "c"; 1464 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1465 mc->default_display = "tcx"; 1466 mc->default_ram_id = "sun4m.ram"; 1467 } 1468 1469 static const TypeInfo ss20_type = { 1470 .name = MACHINE_TYPE_NAME("SS-20"), 1471 .parent = TYPE_MACHINE, 1472 .class_init = ss20_class_init, 1473 }; 1474 1475 static void voyager_class_init(ObjectClass *oc, void *data) 1476 { 1477 MachineClass *mc = MACHINE_CLASS(oc); 1478 1479 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1480 mc->init = vger_init; 1481 mc->block_default_type = IF_SCSI; 1482 mc->default_boot_order = "c"; 1483 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1484 mc->default_display = "tcx"; 1485 mc->default_ram_id = "sun4m.ram"; 1486 } 1487 1488 static const TypeInfo voyager_type = { 1489 .name = MACHINE_TYPE_NAME("Voyager"), 1490 .parent = TYPE_MACHINE, 1491 .class_init = voyager_class_init, 1492 }; 1493 1494 static void ss_lx_class_init(ObjectClass *oc, void *data) 1495 { 1496 MachineClass *mc = MACHINE_CLASS(oc); 1497 1498 mc->desc = "Sun4m platform, SPARCstation LX"; 1499 mc->init = ss_lx_init; 1500 mc->block_default_type = IF_SCSI; 1501 mc->default_boot_order = "c"; 1502 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1503 mc->default_display = "tcx"; 1504 mc->default_ram_id = "sun4m.ram"; 1505 } 1506 1507 static const TypeInfo ss_lx_type = { 1508 .name = MACHINE_TYPE_NAME("LX"), 1509 .parent = TYPE_MACHINE, 1510 .class_init = ss_lx_class_init, 1511 }; 1512 1513 static void ss4_class_init(ObjectClass *oc, void *data) 1514 { 1515 MachineClass *mc = MACHINE_CLASS(oc); 1516 1517 mc->desc = "Sun4m platform, SPARCstation 4"; 1518 mc->init = ss4_init; 1519 mc->block_default_type = IF_SCSI; 1520 mc->default_boot_order = "c"; 1521 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1522 mc->default_display = "tcx"; 1523 mc->default_ram_id = "sun4m.ram"; 1524 } 1525 1526 static const TypeInfo ss4_type = { 1527 .name = MACHINE_TYPE_NAME("SS-4"), 1528 .parent = TYPE_MACHINE, 1529 .class_init = ss4_class_init, 1530 }; 1531 1532 static void scls_class_init(ObjectClass *oc, void *data) 1533 { 1534 MachineClass *mc = MACHINE_CLASS(oc); 1535 1536 mc->desc = "Sun4m platform, SPARCClassic"; 1537 mc->init = scls_init; 1538 mc->block_default_type = IF_SCSI; 1539 mc->default_boot_order = "c"; 1540 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1541 mc->default_display = "tcx"; 1542 mc->default_ram_id = "sun4m.ram"; 1543 } 1544 1545 static const TypeInfo scls_type = { 1546 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1547 .parent = TYPE_MACHINE, 1548 .class_init = scls_class_init, 1549 }; 1550 1551 static void sbook_class_init(ObjectClass *oc, void *data) 1552 { 1553 MachineClass *mc = MACHINE_CLASS(oc); 1554 1555 mc->desc = "Sun4m platform, SPARCbook"; 1556 mc->init = sbook_init; 1557 mc->block_default_type = IF_SCSI; 1558 mc->default_boot_order = "c"; 1559 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1560 mc->default_display = "tcx"; 1561 mc->default_ram_id = "sun4m.ram"; 1562 } 1563 1564 static const TypeInfo sbook_type = { 1565 .name = MACHINE_TYPE_NAME("SPARCbook"), 1566 .parent = TYPE_MACHINE, 1567 .class_init = sbook_class_init, 1568 }; 1569 1570 static void sun4m_register_types(void) 1571 { 1572 type_register_static(&idreg_info); 1573 type_register_static(&afx_info); 1574 type_register_static(&prom_info); 1575 type_register_static(&ram_info); 1576 1577 type_register_static(&ss5_type); 1578 type_register_static(&ss10_type); 1579 type_register_static(&ss600mp_type); 1580 type_register_static(&ss20_type); 1581 type_register_static(&voyager_type); 1582 type_register_static(&ss_lx_type); 1583 type_register_static(&ss4_type); 1584 type_register_static(&scls_type); 1585 type_register_static(&sbook_type); 1586 } 1587 1588 type_init(sun4m_register_types) 1589