1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * Copyright (C) 2016-2017, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef FTGMAC100_H 11 #define FTGMAC100_H 12 #include "qom/object.h" 13 14 #define TYPE_FTGMAC100 "ftgmac100" 15 typedef struct FTGMAC100State FTGMAC100State; 16 #define FTGMAC100(obj) OBJECT_CHECK(FTGMAC100State, (obj), TYPE_FTGMAC100) 17 18 #include "hw/sysbus.h" 19 #include "net/net.h" 20 21 /* 22 * Max frame size for the receiving buffer 23 */ 24 #define FTGMAC100_MAX_FRAME_SIZE 9220 25 26 struct FTGMAC100State { 27 /*< private >*/ 28 SysBusDevice parent_obj; 29 30 /*< public >*/ 31 NICState *nic; 32 NICConf conf; 33 qemu_irq irq; 34 MemoryRegion iomem; 35 36 uint8_t frame[FTGMAC100_MAX_FRAME_SIZE]; 37 38 uint32_t irq_state; 39 uint32_t isr; 40 uint32_t ier; 41 uint32_t rx_enabled; 42 uint32_t rx_ring; 43 uint32_t rx_descriptor; 44 uint32_t tx_ring; 45 uint32_t tx_descriptor; 46 uint32_t math[2]; 47 uint32_t rbsr; 48 uint32_t itc; 49 uint32_t aptcr; 50 uint32_t dblac; 51 uint32_t revr; 52 uint32_t fear1; 53 uint32_t tpafcr; 54 uint32_t maccr; 55 uint32_t phycr; 56 uint32_t phydata; 57 uint32_t fcr; 58 59 60 uint32_t phy_status; 61 uint32_t phy_control; 62 uint32_t phy_advertise; 63 uint32_t phy_int; 64 uint32_t phy_int_mask; 65 66 bool aspeed; 67 uint32_t txdes0_edotr; 68 uint32_t rxdes0_edorr; 69 }; 70 71 #define TYPE_ASPEED_MII "aspeed-mmi" 72 typedef struct AspeedMiiState AspeedMiiState; 73 #define ASPEED_MII(obj) OBJECT_CHECK(AspeedMiiState, (obj), TYPE_ASPEED_MII) 74 75 /* 76 * AST2600 MII controller 77 */ 78 struct AspeedMiiState { 79 /*< private >*/ 80 SysBusDevice parent_obj; 81 82 FTGMAC100State *nic; 83 84 MemoryRegion iomem; 85 uint32_t phycr; 86 uint32_t phydata; 87 }; 88 89 #endif 90