1 #include "qemu/osdep.h" 2 #include "hw/irq.h" 3 #include "hw/qdev-properties.h" 4 #include "net/net.h" 5 #include "qemu/module.h" 6 #include "trace.h" 7 #include "hw/sysbus.h" 8 #include "migration/vmstate.h" 9 #include "qom/object.h" 10 11 /* MIPSnet register offsets */ 12 13 #define MIPSNET_DEV_ID 0x00 14 #define MIPSNET_BUSY 0x08 15 #define MIPSNET_RX_DATA_COUNT 0x0c 16 #define MIPSNET_TX_DATA_COUNT 0x10 17 #define MIPSNET_INT_CTL 0x14 18 # define MIPSNET_INTCTL_TXDONE 0x00000001 19 # define MIPSNET_INTCTL_RXDONE 0x00000002 20 # define MIPSNET_INTCTL_TESTBIT 0x80000000 21 #define MIPSNET_INTERRUPT_INFO 0x18 22 #define MIPSNET_RX_DATA_BUFFER 0x1c 23 #define MIPSNET_TX_DATA_BUFFER 0x20 24 25 #define MAX_ETH_FRAME_SIZE 1514 26 27 #define TYPE_MIPS_NET "mipsnet" 28 typedef struct MIPSnetState MIPSnetState; 29 #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET) 30 31 struct MIPSnetState { 32 SysBusDevice parent_obj; 33 34 uint32_t busy; 35 uint32_t rx_count; 36 uint32_t rx_read; 37 uint32_t tx_count; 38 uint32_t tx_written; 39 uint32_t intctl; 40 uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; 41 uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; 42 MemoryRegion io; 43 qemu_irq irq; 44 NICState *nic; 45 NICConf conf; 46 }; 47 48 static void mipsnet_reset(MIPSnetState *s) 49 { 50 s->busy = 1; 51 s->rx_count = 0; 52 s->rx_read = 0; 53 s->tx_count = 0; 54 s->tx_written = 0; 55 s->intctl = 0; 56 memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); 57 memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); 58 } 59 60 static void mipsnet_update_irq(MIPSnetState *s) 61 { 62 int isr = !!s->intctl; 63 trace_mipsnet_irq(isr, s->intctl); 64 qemu_set_irq(s->irq, isr); 65 } 66 67 static int mipsnet_buffer_full(MIPSnetState *s) 68 { 69 if (s->rx_count >= MAX_ETH_FRAME_SIZE) { 70 return 1; 71 } 72 return 0; 73 } 74 75 static int mipsnet_can_receive(NetClientState *nc) 76 { 77 MIPSnetState *s = qemu_get_nic_opaque(nc); 78 79 if (s->busy) { 80 return 0; 81 } 82 return !mipsnet_buffer_full(s); 83 } 84 85 static ssize_t mipsnet_receive(NetClientState *nc, 86 const uint8_t *buf, size_t size) 87 { 88 MIPSnetState *s = qemu_get_nic_opaque(nc); 89 90 trace_mipsnet_receive(size); 91 if (!mipsnet_can_receive(nc)) { 92 return 0; 93 } 94 95 if (size >= sizeof(s->rx_buffer)) { 96 return 0; 97 } 98 s->busy = 1; 99 100 /* Just accept everything. */ 101 102 /* Write packet data. */ 103 memcpy(s->rx_buffer, buf, size); 104 105 s->rx_count = size; 106 s->rx_read = 0; 107 108 /* Now we can signal we have received something. */ 109 s->intctl |= MIPSNET_INTCTL_RXDONE; 110 mipsnet_update_irq(s); 111 112 return size; 113 } 114 115 static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, 116 unsigned int size) 117 { 118 MIPSnetState *s = opaque; 119 int ret = 0; 120 121 addr &= 0x3f; 122 switch (addr) { 123 case MIPSNET_DEV_ID: 124 ret = be32_to_cpu(0x4d495053); /* MIPS */ 125 break; 126 case MIPSNET_DEV_ID + 4: 127 ret = be32_to_cpu(0x4e455430); /* NET0 */ 128 break; 129 case MIPSNET_BUSY: 130 ret = s->busy; 131 break; 132 case MIPSNET_RX_DATA_COUNT: 133 ret = s->rx_count; 134 break; 135 case MIPSNET_TX_DATA_COUNT: 136 ret = s->tx_count; 137 break; 138 case MIPSNET_INT_CTL: 139 ret = s->intctl; 140 s->intctl &= ~MIPSNET_INTCTL_TESTBIT; 141 break; 142 case MIPSNET_INTERRUPT_INFO: 143 /* XXX: This seems to be a per-VPE interrupt number. */ 144 ret = 0; 145 break; 146 case MIPSNET_RX_DATA_BUFFER: 147 if (s->rx_count) { 148 s->rx_count--; 149 ret = s->rx_buffer[s->rx_read++]; 150 if (mipsnet_can_receive(s->nic->ncs)) { 151 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 152 } 153 } 154 break; 155 /* Reads as zero. */ 156 case MIPSNET_TX_DATA_BUFFER: 157 default: 158 break; 159 } 160 trace_mipsnet_read(addr, ret); 161 return ret; 162 } 163 164 static void mipsnet_ioport_write(void *opaque, hwaddr addr, 165 uint64_t val, unsigned int size) 166 { 167 MIPSnetState *s = opaque; 168 169 addr &= 0x3f; 170 trace_mipsnet_write(addr, val); 171 switch (addr) { 172 case MIPSNET_TX_DATA_COUNT: 173 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; 174 s->tx_written = 0; 175 break; 176 case MIPSNET_INT_CTL: 177 if (val & MIPSNET_INTCTL_TXDONE) { 178 s->intctl &= ~MIPSNET_INTCTL_TXDONE; 179 } else if (val & MIPSNET_INTCTL_RXDONE) { 180 s->intctl &= ~MIPSNET_INTCTL_RXDONE; 181 } else if (val & MIPSNET_INTCTL_TESTBIT) { 182 mipsnet_reset(s); 183 s->intctl |= MIPSNET_INTCTL_TESTBIT; 184 } else if (!val) { 185 /* ACK testbit interrupt, flag was cleared on read. */ 186 } 187 s->busy = !!s->intctl; 188 mipsnet_update_irq(s); 189 if (mipsnet_can_receive(s->nic->ncs)) { 190 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 191 } 192 break; 193 case MIPSNET_TX_DATA_BUFFER: 194 s->tx_buffer[s->tx_written++] = val; 195 if ((s->tx_written >= MAX_ETH_FRAME_SIZE) 196 || (s->tx_written == s->tx_count)) { 197 /* Send buffer. */ 198 trace_mipsnet_send(s->tx_written); 199 qemu_send_packet(qemu_get_queue(s->nic), 200 s->tx_buffer, s->tx_written); 201 s->tx_count = s->tx_written = 0; 202 s->intctl |= MIPSNET_INTCTL_TXDONE; 203 s->busy = 1; 204 mipsnet_update_irq(s); 205 } 206 break; 207 /* Read-only registers */ 208 case MIPSNET_DEV_ID: 209 case MIPSNET_BUSY: 210 case MIPSNET_RX_DATA_COUNT: 211 case MIPSNET_INTERRUPT_INFO: 212 case MIPSNET_RX_DATA_BUFFER: 213 default: 214 break; 215 } 216 } 217 218 static const VMStateDescription vmstate_mipsnet = { 219 .name = "mipsnet", 220 .version_id = 0, 221 .minimum_version_id = 0, 222 .fields = (VMStateField[]) { 223 VMSTATE_UINT32(busy, MIPSnetState), 224 VMSTATE_UINT32(rx_count, MIPSnetState), 225 VMSTATE_UINT32(rx_read, MIPSnetState), 226 VMSTATE_UINT32(tx_count, MIPSnetState), 227 VMSTATE_UINT32(tx_written, MIPSnetState), 228 VMSTATE_UINT32(intctl, MIPSnetState), 229 VMSTATE_BUFFER(rx_buffer, MIPSnetState), 230 VMSTATE_BUFFER(tx_buffer, MIPSnetState), 231 VMSTATE_END_OF_LIST() 232 } 233 }; 234 235 static NetClientInfo net_mipsnet_info = { 236 .type = NET_CLIENT_DRIVER_NIC, 237 .size = sizeof(NICState), 238 .receive = mipsnet_receive, 239 }; 240 241 static const MemoryRegionOps mipsnet_ioport_ops = { 242 .read = mipsnet_ioport_read, 243 .write = mipsnet_ioport_write, 244 .impl.min_access_size = 1, 245 .impl.max_access_size = 4, 246 }; 247 248 static void mipsnet_realize(DeviceState *dev, Error **errp) 249 { 250 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 251 MIPSnetState *s = MIPS_NET(dev); 252 253 memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, 254 "mipsnet-io", 36); 255 sysbus_init_mmio(sbd, &s->io); 256 sysbus_init_irq(sbd, &s->irq); 257 258 s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf, 259 object_get_typename(OBJECT(dev)), dev->id, s); 260 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 261 } 262 263 static void mipsnet_sysbus_reset(DeviceState *dev) 264 { 265 MIPSnetState *s = MIPS_NET(dev); 266 mipsnet_reset(s); 267 } 268 269 static Property mipsnet_properties[] = { 270 DEFINE_NIC_PROPERTIES(MIPSnetState, conf), 271 DEFINE_PROP_END_OF_LIST(), 272 }; 273 274 static void mipsnet_class_init(ObjectClass *klass, void *data) 275 { 276 DeviceClass *dc = DEVICE_CLASS(klass); 277 278 dc->realize = mipsnet_realize; 279 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 280 dc->desc = "MIPS Simulator network device"; 281 dc->reset = mipsnet_sysbus_reset; 282 dc->vmsd = &vmstate_mipsnet; 283 device_class_set_props(dc, mipsnet_properties); 284 } 285 286 static const TypeInfo mipsnet_info = { 287 .name = TYPE_MIPS_NET, 288 .parent = TYPE_SYS_BUS_DEVICE, 289 .instance_size = sizeof(MIPSnetState), 290 .class_init = mipsnet_class_init, 291 }; 292 293 static void mipsnet_register_types(void) 294 { 295 type_register_static(&mipsnet_info); 296 } 297 298 type_init(mipsnet_register_types) 299