1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti 9 * Upstream code cleanup (c) 2018 Pekka Enberg 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qemu/units.h" 17 #include "qemu/cutils.h" 18 #include "qapi/error.h" 19 #include "cpu.h" 20 #include "hw/arm/bcm2836.h" 21 #include "hw/registerfields.h" 22 #include "qemu/error-report.h" 23 #include "hw/boards.h" 24 #include "hw/loader.h" 25 #include "hw/arm/boot.h" 26 #include "sysemu/sysemu.h" 27 #include "qom/object.h" 28 29 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ 30 #define MVBAR_ADDR 0x400 /* secure vectors */ 31 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ 32 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ 33 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ 34 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ 35 36 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ 37 #define MACH_TYPE_BCM2708 3138 38 39 struct RaspiMachineState { 40 /*< private >*/ 41 MachineState parent_obj; 42 /*< public >*/ 43 BCM283XState soc; 44 }; 45 typedef struct RaspiMachineState RaspiMachineState; 46 47 struct RaspiMachineClass { 48 /*< private >*/ 49 MachineClass parent_obj; 50 /*< public >*/ 51 uint32_t board_rev; 52 }; 53 typedef struct RaspiMachineClass RaspiMachineClass; 54 55 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") 56 #define RASPI_MACHINE(obj) \ 57 OBJECT_CHECK(RaspiMachineState, (obj), TYPE_RASPI_MACHINE) 58 59 #define RASPI_MACHINE_CLASS(klass) \ 60 OBJECT_CLASS_CHECK(RaspiMachineClass, (klass), TYPE_RASPI_MACHINE) 61 #define RASPI_MACHINE_GET_CLASS(obj) \ 62 OBJECT_GET_CLASS(RaspiMachineClass, (obj), TYPE_RASPI_MACHINE) 63 64 /* 65 * Board revision codes: 66 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ 67 */ 68 FIELD(REV_CODE, REVISION, 0, 4); 69 FIELD(REV_CODE, TYPE, 4, 8); 70 FIELD(REV_CODE, PROCESSOR, 12, 4); 71 FIELD(REV_CODE, MANUFACTURER, 16, 4); 72 FIELD(REV_CODE, MEMORY_SIZE, 20, 3); 73 FIELD(REV_CODE, STYLE, 23, 1); 74 75 static uint64_t board_ram_size(uint32_t board_rev) 76 { 77 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 78 return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); 79 } 80 81 static int board_processor_id(uint32_t board_rev) 82 { 83 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 84 return FIELD_EX32(board_rev, REV_CODE, PROCESSOR); 85 } 86 87 static int board_version(uint32_t board_rev) 88 { 89 return board_processor_id(board_rev) + 1; 90 } 91 92 static const char *board_soc_type(uint32_t board_rev) 93 { 94 static const char *soc_types[] = { 95 NULL, TYPE_BCM2836, TYPE_BCM2837, 96 }; 97 int proc_id = board_processor_id(board_rev); 98 99 if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) { 100 error_report("Unsupported processor id '%d' (board revision: 0x%x)", 101 proc_id, board_rev); 102 exit(1); 103 } 104 return soc_types[proc_id]; 105 } 106 107 static int cores_count(uint32_t board_rev) 108 { 109 static const int soc_cores_count[] = { 110 0, BCM283X_NCPUS, BCM283X_NCPUS, 111 }; 112 int proc_id = board_processor_id(board_rev); 113 114 if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) { 115 error_report("Unsupported processor id '%d' (board revision: 0x%x)", 116 proc_id, board_rev); 117 exit(1); 118 } 119 return soc_cores_count[proc_id]; 120 } 121 122 static const char *board_type(uint32_t board_rev) 123 { 124 static const char *types[] = { 125 "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", 126 "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", 127 }; 128 assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ 129 int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); 130 if (bt >= ARRAY_SIZE(types) || !types[bt]) { 131 return "Unknown"; 132 } 133 return types[bt]; 134 } 135 136 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) 137 { 138 static const uint32_t smpboot[] = { 139 0xe1a0e00f, /* mov lr, pc */ 140 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ 141 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ 142 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ 143 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ 144 0xe320f001, /* 1: yield */ 145 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ 146 0xe3530000, /* cmp r3, #0 ;spin while zero */ 147 0x0afffffb, /* beq 1b */ 148 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ 149 0xe12fff13, /* bx r3 ;jump to target */ 150 0x400000cc, /* (constant: mailbox 3 read/clear base) */ 151 }; 152 153 /* check that we don't overrun board setup vectors */ 154 QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); 155 /* check that board setup address is correctly relocated */ 156 QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 157 || (BOARDSETUP_ADDR >> 4) >= 0x100); 158 159 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 160 info->smp_loader_start, 161 arm_boot_address_space(cpu, info)); 162 } 163 164 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 165 { 166 AddressSpace *as = arm_boot_address_space(cpu, info); 167 /* Unlike the AArch32 version we don't need to call the board setup hook. 168 * The mechanism for doing the spin-table is also entirely different. 169 * We must have four 64-bit fields at absolute addresses 170 * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for 171 * our CPUs, and which we must ensure are zero initialized before 172 * the primary CPU goes into the kernel. We put these variables inside 173 * a rom blob, so that the reset for ROM contents zeroes them for us. 174 */ 175 static const uint32_t smpboot[] = { 176 0xd2801b05, /* mov x5, 0xd8 */ 177 0xd53800a6, /* mrs x6, mpidr_el1 */ 178 0x924004c6, /* and x6, x6, #0x3 */ 179 0xd503205f, /* spin: wfe */ 180 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ 181 0xb4ffffc4, /* cbz x4, spin */ 182 0xd2800000, /* mov x0, #0x0 */ 183 0xd2800001, /* mov x1, #0x0 */ 184 0xd2800002, /* mov x2, #0x0 */ 185 0xd2800003, /* mov x3, #0x0 */ 186 0xd61f0080, /* br x4 */ 187 }; 188 189 static const uint64_t spintables[] = { 190 0, 0, 0, 0 191 }; 192 193 rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), 194 info->smp_loader_start, as); 195 rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), 196 SPINTABLE_ADDR, as); 197 } 198 199 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) 200 { 201 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); 202 } 203 204 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 205 { 206 CPUState *cs = CPU(cpu); 207 cpu_set_pc(cs, info->smp_loader_start); 208 } 209 210 static void setup_boot(MachineState *machine, int version, size_t ram_size) 211 { 212 static struct arm_boot_info binfo; 213 int r; 214 215 binfo.board_id = MACH_TYPE_BCM2708; 216 binfo.ram_size = ram_size; 217 binfo.nb_cpus = machine->smp.cpus; 218 219 if (version <= 2) { 220 /* The rpi1 and 2 require some custom setup code to run in Secure 221 * mode before booting a kernel (to set up the SMC vectors so 222 * that we get a no-op SMC; this is used by Linux to call the 223 * firmware for some cache maintenance operations. 224 * The rpi3 doesn't need this. 225 */ 226 binfo.board_setup_addr = BOARDSETUP_ADDR; 227 binfo.write_board_setup = write_board_setup; 228 binfo.secure_board_setup = true; 229 binfo.secure_boot = true; 230 } 231 232 /* Pi2 and Pi3 requires SMP setup */ 233 if (version >= 2) { 234 binfo.smp_loader_start = SMPBOOT_ADDR; 235 if (version == 2) { 236 binfo.write_secondary_boot = write_smpboot; 237 } else { 238 binfo.write_secondary_boot = write_smpboot64; 239 } 240 binfo.secondary_cpu_reset_hook = reset_secondary; 241 } 242 243 /* If the user specified a "firmware" image (e.g. UEFI), we bypass 244 * the normal Linux boot process 245 */ 246 if (machine->firmware) { 247 hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2; 248 /* load the firmware image (typically kernel.img) */ 249 r = load_image_targphys(machine->firmware, firmware_addr, 250 ram_size - firmware_addr); 251 if (r < 0) { 252 error_report("Failed to load firmware from %s", machine->firmware); 253 exit(1); 254 } 255 256 binfo.entry = firmware_addr; 257 binfo.firmware_loaded = true; 258 } 259 260 arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo); 261 } 262 263 static void raspi_machine_init(MachineState *machine) 264 { 265 RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); 266 RaspiMachineState *s = RASPI_MACHINE(machine); 267 uint32_t board_rev = mc->board_rev; 268 int version = board_version(board_rev); 269 uint64_t ram_size = board_ram_size(board_rev); 270 uint32_t vcram_size; 271 DriveInfo *di; 272 BlockBackend *blk; 273 BusState *bus; 274 DeviceState *carddev; 275 276 if (machine->ram_size != ram_size) { 277 char *size_str = size_to_str(ram_size); 278 error_report("Invalid RAM size, should be %s", size_str); 279 g_free(size_str); 280 exit(1); 281 } 282 283 /* FIXME: Remove when we have custom CPU address space support */ 284 memory_region_add_subregion_overlap(get_system_memory(), 0, 285 machine->ram, 0); 286 287 /* Setup the SOC */ 288 object_initialize_child(OBJECT(machine), "soc", &s->soc, 289 board_soc_type(board_rev)); 290 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); 291 object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev, 292 &error_abort); 293 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 294 295 /* Create and plug in the SD cards */ 296 di = drive_get_next(IF_SD); 297 blk = di ? blk_by_legacy_dinfo(di) : NULL; 298 bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); 299 if (bus == NULL) { 300 error_report("No SD bus found in SOC object"); 301 exit(1); 302 } 303 carddev = qdev_new(TYPE_SD_CARD); 304 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); 305 qdev_realize_and_unref(carddev, bus, &error_fatal); 306 307 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", 308 &error_abort); 309 setup_boot(machine, version, machine->ram_size - vcram_size); 310 } 311 312 static void raspi_machine_class_init(ObjectClass *oc, void *data) 313 { 314 MachineClass *mc = MACHINE_CLASS(oc); 315 RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); 316 uint32_t board_rev = (uint32_t)(uintptr_t)data; 317 318 rmc->board_rev = board_rev; 319 mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev)); 320 mc->init = raspi_machine_init; 321 mc->block_default_type = IF_SD; 322 mc->no_parallel = 1; 323 mc->no_floppy = 1; 324 mc->no_cdrom = 1; 325 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); 326 mc->default_ram_size = board_ram_size(board_rev); 327 mc->default_ram_id = "ram"; 328 if (board_version(board_rev) == 2) { 329 mc->ignore_memory_transaction_failures = true; 330 } 331 }; 332 333 static const TypeInfo raspi_machine_types[] = { 334 { 335 .name = MACHINE_TYPE_NAME("raspi2"), 336 .parent = TYPE_RASPI_MACHINE, 337 .class_init = raspi_machine_class_init, 338 .class_data = (void *)0xa21041, 339 #ifdef TARGET_AARCH64 340 }, { 341 .name = MACHINE_TYPE_NAME("raspi3"), 342 .parent = TYPE_RASPI_MACHINE, 343 .class_init = raspi_machine_class_init, 344 .class_data = (void *)0xa02082, 345 #endif 346 }, { 347 .name = TYPE_RASPI_MACHINE, 348 .parent = TYPE_MACHINE, 349 .instance_size = sizeof(RaspiMachineState), 350 .class_size = sizeof(RaspiMachineClass), 351 .abstract = true, 352 } 353 }; 354 355 DEFINE_TYPES(raspi_machine_types) 356