1 /* 2 * Nordic Semiconductor nRF51 SoC 3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf 4 * 5 * Copyright 2018 Joel Stanley <joel@jms.id.au> 6 * 7 * This code is licensed under the GPL version 2 or later. See 8 * the COPYING file in the top-level directory. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "hw/arm/arm.h" 15 #include "hw/sysbus.h" 16 #include "hw/boards.h" 17 #include "hw/devices.h" 18 #include "hw/misc/unimp.h" 19 #include "exec/address-spaces.h" 20 #include "sysemu/sysemu.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 24 #include "hw/arm/nrf51.h" 25 #include "hw/arm/nrf51_soc.h" 26 27 /* 28 * The size and base is for the NRF51822 part. If other parts 29 * are supported in the future, add a sub-class of NRF51SoC for 30 * the specific variants 31 */ 32 #define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) 33 #define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) 34 35 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) 36 37 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) 38 { 39 NRF51State *s = NRF51_SOC(dev_soc); 40 MemoryRegion *mr; 41 Error *err = NULL; 42 43 if (!s->board_memory) { 44 error_setg(errp, "memory property was not set"); 45 return; 46 } 47 48 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", 49 &err); 50 if (err) { 51 error_propagate(errp, err); 52 return; 53 } 54 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 55 if (err) { 56 error_propagate(errp, err); 57 return; 58 } 59 60 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); 61 62 memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, 63 &err); 64 if (err) { 65 error_propagate(errp, err); 66 return; 67 } 68 memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash); 69 70 memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); 71 if (err) { 72 error_propagate(errp, err); 73 return; 74 } 75 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); 76 77 /* UART */ 78 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); 79 if (err) { 80 error_propagate(errp, err); 81 return; 82 } 83 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); 84 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); 85 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, 86 qdev_get_gpio_in(DEVICE(&s->cpu), 87 BASE_TO_IRQ(NRF51_UART_BASE))); 88 89 /* RNG */ 90 object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); 91 if (err) { 92 error_propagate(errp, err); 93 return; 94 } 95 96 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); 97 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); 98 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, 99 qdev_get_gpio_in(DEVICE(&s->cpu), 100 BASE_TO_IRQ(NRF51_RNG_BASE))); 101 102 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, 103 NRF51_IOMEM_SIZE); 104 create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, 105 NRF51_FICR_SIZE); 106 create_unimplemented_device("nrf51_soc.private", 107 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); 108 } 109 110 static void nrf51_soc_init(Object *obj) 111 { 112 NRF51State *s = NRF51_SOC(obj); 113 114 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); 115 116 sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), 117 TYPE_ARMV7M); 118 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", 119 ARM_CPU_TYPE_NAME("cortex-m0")); 120 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); 121 122 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart), 123 TYPE_NRF51_UART); 124 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", 125 &error_abort); 126 127 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), 128 TYPE_NRF51_RNG); 129 } 130 131 static Property nrf51_soc_properties[] = { 132 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, 133 MemoryRegion *), 134 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), 135 DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, 136 NRF51822_FLASH_SIZE), 137 DEFINE_PROP_END_OF_LIST(), 138 }; 139 140 static void nrf51_soc_class_init(ObjectClass *klass, void *data) 141 { 142 DeviceClass *dc = DEVICE_CLASS(klass); 143 144 dc->realize = nrf51_soc_realize; 145 dc->props = nrf51_soc_properties; 146 } 147 148 static const TypeInfo nrf51_soc_info = { 149 .name = TYPE_NRF51_SOC, 150 .parent = TYPE_SYS_BUS_DEVICE, 151 .instance_size = sizeof(NRF51State), 152 .instance_init = nrf51_soc_init, 153 .class_init = nrf51_soc_class_init, 154 }; 155 156 static void nrf51_soc_types(void) 157 { 158 type_register_static(&nrf51_soc_info); 159 } 160 type_init(nrf51_soc_types) 161