1 /* 2 * GPIO Controller for a lot of Freescale SoCs 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Alexander Graf, <agraf@suse.de> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/irq.h" 24 #include "hw/sysbus.h" 25 #include "migration/vmstate.h" 26 #include "qemu/module.h" 27 #include "qom/object.h" 28 29 #define TYPE_MPC8XXX_GPIO "mpc8xxx_gpio" 30 typedef struct MPC8XXXGPIOState MPC8XXXGPIOState; 31 #define MPC8XXX_GPIO(obj) OBJECT_CHECK(MPC8XXXGPIOState, (obj), TYPE_MPC8XXX_GPIO) 32 33 struct MPC8XXXGPIOState { 34 SysBusDevice parent_obj; 35 36 MemoryRegion iomem; 37 qemu_irq irq; 38 qemu_irq out[32]; 39 40 uint32_t dir; 41 uint32_t odr; 42 uint32_t dat; 43 uint32_t ier; 44 uint32_t imr; 45 uint32_t icr; 46 }; 47 48 static const VMStateDescription vmstate_mpc8xxx_gpio = { 49 .name = "mpc8xxx_gpio", 50 .version_id = 1, 51 .minimum_version_id = 1, 52 .fields = (VMStateField[]) { 53 VMSTATE_UINT32(dir, MPC8XXXGPIOState), 54 VMSTATE_UINT32(odr, MPC8XXXGPIOState), 55 VMSTATE_UINT32(dat, MPC8XXXGPIOState), 56 VMSTATE_UINT32(ier, MPC8XXXGPIOState), 57 VMSTATE_UINT32(imr, MPC8XXXGPIOState), 58 VMSTATE_UINT32(icr, MPC8XXXGPIOState), 59 VMSTATE_END_OF_LIST() 60 } 61 }; 62 63 static void mpc8xxx_gpio_update(MPC8XXXGPIOState *s) 64 { 65 qemu_set_irq(s->irq, !!(s->ier & s->imr)); 66 } 67 68 static uint64_t mpc8xxx_gpio_read(void *opaque, hwaddr offset, 69 unsigned size) 70 { 71 MPC8XXXGPIOState *s = (MPC8XXXGPIOState *)opaque; 72 73 if (size != 4) { 74 /* All registers are 32bit */ 75 return 0; 76 } 77 78 switch (offset) { 79 case 0x0: /* Direction */ 80 return s->dir; 81 case 0x4: /* Open Drain */ 82 return s->odr; 83 case 0x8: /* Data */ 84 return s->dat; 85 case 0xC: /* Interrupt Event */ 86 return s->ier; 87 case 0x10: /* Interrupt Mask */ 88 return s->imr; 89 case 0x14: /* Interrupt Control */ 90 return s->icr; 91 default: 92 return 0; 93 } 94 } 95 96 static void mpc8xxx_write_data(MPC8XXXGPIOState *s, uint32_t new_data) 97 { 98 uint32_t old_data = s->dat; 99 uint32_t diff = old_data ^ new_data; 100 int i; 101 102 for (i = 0; i < 32; i++) { 103 uint32_t mask = 0x80000000 >> i; 104 if (!(diff & mask)) { 105 continue; 106 } 107 108 if (s->dir & mask) { 109 /* Output */ 110 qemu_set_irq(s->out[i], (new_data & mask) != 0); 111 } 112 } 113 114 s->dat = new_data; 115 } 116 117 static void mpc8xxx_gpio_write(void *opaque, hwaddr offset, 118 uint64_t value, unsigned size) 119 { 120 MPC8XXXGPIOState *s = (MPC8XXXGPIOState *)opaque; 121 122 if (size != 4) { 123 /* All registers are 32bit */ 124 return; 125 } 126 127 switch (offset) { 128 case 0x0: /* Direction */ 129 s->dir = value; 130 break; 131 case 0x4: /* Open Drain */ 132 s->odr = value; 133 break; 134 case 0x8: /* Data */ 135 mpc8xxx_write_data(s, value); 136 break; 137 case 0xC: /* Interrupt Event */ 138 s->ier &= ~value; 139 break; 140 case 0x10: /* Interrupt Mask */ 141 s->imr = value; 142 break; 143 case 0x14: /* Interrupt Control */ 144 s->icr = value; 145 break; 146 } 147 148 mpc8xxx_gpio_update(s); 149 } 150 151 static void mpc8xxx_gpio_reset(DeviceState *dev) 152 { 153 MPC8XXXGPIOState *s = MPC8XXX_GPIO(dev); 154 155 s->dir = 0; 156 s->odr = 0; 157 s->dat = 0; 158 s->ier = 0; 159 s->imr = 0; 160 s->icr = 0; 161 } 162 163 static void mpc8xxx_gpio_set_irq(void * opaque, int irq, int level) 164 { 165 MPC8XXXGPIOState *s = (MPC8XXXGPIOState *)opaque; 166 uint32_t mask; 167 168 mask = 0x80000000 >> irq; 169 if ((s->dir & mask) == 0) { 170 uint32_t old_value = s->dat & mask; 171 172 s->dat &= ~mask; 173 if (level) 174 s->dat |= mask; 175 176 if (!(s->icr & irq) || (old_value && !level)) { 177 s->ier |= mask; 178 } 179 180 mpc8xxx_gpio_update(s); 181 } 182 } 183 184 static const MemoryRegionOps mpc8xxx_gpio_ops = { 185 .read = mpc8xxx_gpio_read, 186 .write = mpc8xxx_gpio_write, 187 .endianness = DEVICE_BIG_ENDIAN, 188 }; 189 190 static void mpc8xxx_gpio_initfn(Object *obj) 191 { 192 DeviceState *dev = DEVICE(obj); 193 MPC8XXXGPIOState *s = MPC8XXX_GPIO(obj); 194 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 195 196 memory_region_init_io(&s->iomem, obj, &mpc8xxx_gpio_ops, 197 s, "mpc8xxx_gpio", 0x1000); 198 sysbus_init_mmio(sbd, &s->iomem); 199 sysbus_init_irq(sbd, &s->irq); 200 qdev_init_gpio_in(dev, mpc8xxx_gpio_set_irq, 32); 201 qdev_init_gpio_out(dev, s->out, 32); 202 } 203 204 static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data) 205 { 206 DeviceClass *dc = DEVICE_CLASS(klass); 207 208 dc->vmsd = &vmstate_mpc8xxx_gpio; 209 dc->reset = mpc8xxx_gpio_reset; 210 } 211 212 static const TypeInfo mpc8xxx_gpio_info = { 213 .name = TYPE_MPC8XXX_GPIO, 214 .parent = TYPE_SYS_BUS_DEVICE, 215 .instance_size = sizeof(MPC8XXXGPIOState), 216 .instance_init = mpc8xxx_gpio_initfn, 217 .class_init = mpc8xxx_gpio_class_init, 218 }; 219 220 static void mpc8xxx_gpio_register_types(void) 221 { 222 type_register_static(&mpc8xxx_gpio_info); 223 } 224 225 type_init(mpc8xxx_gpio_register_types) 226