1 /* 2 * QEMU TCX Frame buffer 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qapi/error.h" 28 #include "ui/console.h" 29 #include "ui/pixel_ops.h" 30 #include "hw/loader.h" 31 #include "hw/qdev-properties.h" 32 #include "hw/sysbus.h" 33 #include "migration/vmstate.h" 34 #include "qemu/error-report.h" 35 #include "qemu/module.h" 36 #include "qom/object.h" 37 38 #define TCX_ROM_FILE "QEMU,tcx.bin" 39 #define FCODE_MAX_ROM_SIZE 0x10000 40 41 #define MAXX 1024 42 #define MAXY 768 43 #define TCX_DAC_NREGS 16 44 #define TCX_THC_NREGS 0x1000 45 #define TCX_DHC_NREGS 0x4000 46 #define TCX_TEC_NREGS 0x1000 47 #define TCX_ALT_NREGS 0x8000 48 #define TCX_STIP_NREGS 0x800000 49 #define TCX_BLIT_NREGS 0x800000 50 #define TCX_RSTIP_NREGS 0x800000 51 #define TCX_RBLIT_NREGS 0x800000 52 53 #define TCX_THC_MISC 0x818 54 #define TCX_THC_CURSXY 0x8fc 55 #define TCX_THC_CURSMASK 0x900 56 #define TCX_THC_CURSBITS 0x980 57 58 #define TYPE_TCX "SUNW,tcx" 59 typedef struct TCXState TCXState; 60 #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX) 61 62 struct TCXState { 63 SysBusDevice parent_obj; 64 65 QemuConsole *con; 66 qemu_irq irq; 67 uint8_t *vram; 68 uint32_t *vram24, *cplane; 69 hwaddr prom_addr; 70 MemoryRegion rom; 71 MemoryRegion vram_mem; 72 MemoryRegion vram_8bit; 73 MemoryRegion vram_24bit; 74 MemoryRegion stip; 75 MemoryRegion blit; 76 MemoryRegion vram_cplane; 77 MemoryRegion rstip; 78 MemoryRegion rblit; 79 MemoryRegion tec; 80 MemoryRegion dac; 81 MemoryRegion thc; 82 MemoryRegion dhc; 83 MemoryRegion alt; 84 MemoryRegion thc24; 85 86 ram_addr_t vram24_offset, cplane_offset; 87 uint32_t tmpblit; 88 uint32_t vram_size; 89 uint32_t palette[260]; 90 uint8_t r[260], g[260], b[260]; 91 uint16_t width, height, depth; 92 uint8_t dac_index, dac_state; 93 uint32_t thcmisc; 94 uint32_t cursmask[32]; 95 uint32_t cursbits[32]; 96 uint16_t cursx; 97 uint16_t cursy; 98 }; 99 100 static void tcx_set_dirty(TCXState *s, ram_addr_t addr, int len) 101 { 102 memory_region_set_dirty(&s->vram_mem, addr, len); 103 104 if (s->depth == 24) { 105 memory_region_set_dirty(&s->vram_mem, s->vram24_offset + addr * 4, 106 len * 4); 107 memory_region_set_dirty(&s->vram_mem, s->cplane_offset + addr * 4, 108 len * 4); 109 } 110 } 111 112 static int tcx_check_dirty(TCXState *s, DirtyBitmapSnapshot *snap, 113 ram_addr_t addr, int len) 114 { 115 int ret; 116 117 ret = memory_region_snapshot_get_dirty(&s->vram_mem, snap, addr, len); 118 119 if (s->depth == 24) { 120 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, 121 s->vram24_offset + addr * 4, len * 4); 122 ret |= memory_region_snapshot_get_dirty(&s->vram_mem, snap, 123 s->cplane_offset + addr * 4, len * 4); 124 } 125 126 return ret; 127 } 128 129 static void update_palette_entries(TCXState *s, int start, int end) 130 { 131 DisplaySurface *surface = qemu_console_surface(s->con); 132 int i; 133 134 for (i = start; i < end; i++) { 135 if (is_surface_bgr(surface)) { 136 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); 137 } else { 138 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); 139 } 140 } 141 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 142 } 143 144 static void tcx_draw_line32(TCXState *s1, uint8_t *d, 145 const uint8_t *s, int width) 146 { 147 int x; 148 uint8_t val; 149 uint32_t *p = (uint32_t *)d; 150 151 for (x = 0; x < width; x++) { 152 val = *s++; 153 *p++ = s1->palette[val]; 154 } 155 } 156 157 static void tcx_draw_cursor32(TCXState *s1, uint8_t *d, 158 int y, int width) 159 { 160 int x, len; 161 uint32_t mask, bits; 162 uint32_t *p = (uint32_t *)d; 163 164 y = y - s1->cursy; 165 mask = s1->cursmask[y]; 166 bits = s1->cursbits[y]; 167 len = MIN(width - s1->cursx, 32); 168 p = &p[s1->cursx]; 169 for (x = 0; x < len; x++) { 170 if (mask & 0x80000000) { 171 if (bits & 0x80000000) { 172 *p = s1->palette[259]; 173 } else { 174 *p = s1->palette[258]; 175 } 176 } 177 p++; 178 mask <<= 1; 179 bits <<= 1; 180 } 181 } 182 183 /* 184 XXX Could be much more optimal: 185 * detect if line/page/whole screen is in 24 bit mode 186 * if destination is also BGR, use memcpy 187 */ 188 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, 189 const uint8_t *s, int width, 190 const uint32_t *cplane, 191 const uint32_t *s24) 192 { 193 DisplaySurface *surface = qemu_console_surface(s1->con); 194 int x, bgr, r, g, b; 195 uint8_t val, *p8; 196 uint32_t *p = (uint32_t *)d; 197 uint32_t dval; 198 bgr = is_surface_bgr(surface); 199 for(x = 0; x < width; x++, s++, s24++) { 200 if (be32_to_cpu(*cplane) & 0x03000000) { 201 /* 24-bit direct, BGR order */ 202 p8 = (uint8_t *)s24; 203 p8++; 204 b = *p8++; 205 g = *p8++; 206 r = *p8; 207 if (bgr) 208 dval = rgb_to_pixel32bgr(r, g, b); 209 else 210 dval = rgb_to_pixel32(r, g, b); 211 } else { 212 /* 8-bit pseudocolor */ 213 val = *s; 214 dval = s1->palette[val]; 215 } 216 *p++ = dval; 217 cplane++; 218 } 219 } 220 221 /* Fixed line length 1024 allows us to do nice tricks not possible on 222 VGA... */ 223 224 static void tcx_update_display(void *opaque) 225 { 226 TCXState *ts = opaque; 227 DisplaySurface *surface = qemu_console_surface(ts->con); 228 ram_addr_t page; 229 DirtyBitmapSnapshot *snap = NULL; 230 int y, y_start, dd, ds; 231 uint8_t *d, *s; 232 233 if (surface_bits_per_pixel(surface) != 32) { 234 return; 235 } 236 237 page = 0; 238 y_start = -1; 239 d = surface_data(surface); 240 s = ts->vram; 241 dd = surface_stride(surface); 242 ds = 1024; 243 244 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, 245 memory_region_size(&ts->vram_mem), 246 DIRTY_MEMORY_VGA); 247 248 for (y = 0; y < ts->height; y++, page += ds) { 249 if (tcx_check_dirty(ts, snap, page, ds)) { 250 if (y_start < 0) 251 y_start = y; 252 253 tcx_draw_line32(ts, d, s, ts->width); 254 if (y >= ts->cursy && y < ts->cursy + 32 && ts->cursx < ts->width) { 255 tcx_draw_cursor32(ts, d, y, ts->width); 256 } 257 } else { 258 if (y_start >= 0) { 259 /* flush to display */ 260 dpy_gfx_update(ts->con, 0, y_start, 261 ts->width, y - y_start); 262 y_start = -1; 263 } 264 } 265 s += ds; 266 d += dd; 267 } 268 if (y_start >= 0) { 269 /* flush to display */ 270 dpy_gfx_update(ts->con, 0, y_start, 271 ts->width, y - y_start); 272 } 273 g_free(snap); 274 } 275 276 static void tcx24_update_display(void *opaque) 277 { 278 TCXState *ts = opaque; 279 DisplaySurface *surface = qemu_console_surface(ts->con); 280 ram_addr_t page; 281 DirtyBitmapSnapshot *snap = NULL; 282 int y, y_start, dd, ds; 283 uint8_t *d, *s; 284 uint32_t *cptr, *s24; 285 286 if (surface_bits_per_pixel(surface) != 32) { 287 return; 288 } 289 290 page = 0; 291 y_start = -1; 292 d = surface_data(surface); 293 s = ts->vram; 294 s24 = ts->vram24; 295 cptr = ts->cplane; 296 dd = surface_stride(surface); 297 ds = 1024; 298 299 snap = memory_region_snapshot_and_clear_dirty(&ts->vram_mem, 0x0, 300 memory_region_size(&ts->vram_mem), 301 DIRTY_MEMORY_VGA); 302 303 for (y = 0; y < ts->height; y++, page += ds) { 304 if (tcx_check_dirty(ts, snap, page, ds)) { 305 if (y_start < 0) 306 y_start = y; 307 308 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); 309 if (y >= ts->cursy && y < ts->cursy+32 && ts->cursx < ts->width) { 310 tcx_draw_cursor32(ts, d, y, ts->width); 311 } 312 } else { 313 if (y_start >= 0) { 314 /* flush to display */ 315 dpy_gfx_update(ts->con, 0, y_start, 316 ts->width, y - y_start); 317 y_start = -1; 318 } 319 } 320 d += dd; 321 s += ds; 322 cptr += ds; 323 s24 += ds; 324 } 325 if (y_start >= 0) { 326 /* flush to display */ 327 dpy_gfx_update(ts->con, 0, y_start, 328 ts->width, y - y_start); 329 } 330 g_free(snap); 331 } 332 333 static void tcx_invalidate_display(void *opaque) 334 { 335 TCXState *s = opaque; 336 337 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 338 qemu_console_resize(s->con, s->width, s->height); 339 } 340 341 static void tcx24_invalidate_display(void *opaque) 342 { 343 TCXState *s = opaque; 344 345 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 346 qemu_console_resize(s->con, s->width, s->height); 347 } 348 349 static int vmstate_tcx_post_load(void *opaque, int version_id) 350 { 351 TCXState *s = opaque; 352 353 update_palette_entries(s, 0, 256); 354 tcx_set_dirty(s, 0, memory_region_size(&s->vram_mem)); 355 return 0; 356 } 357 358 static const VMStateDescription vmstate_tcx = { 359 .name ="tcx", 360 .version_id = 4, 361 .minimum_version_id = 4, 362 .post_load = vmstate_tcx_post_load, 363 .fields = (VMStateField[]) { 364 VMSTATE_UINT16(height, TCXState), 365 VMSTATE_UINT16(width, TCXState), 366 VMSTATE_UINT16(depth, TCXState), 367 VMSTATE_BUFFER(r, TCXState), 368 VMSTATE_BUFFER(g, TCXState), 369 VMSTATE_BUFFER(b, TCXState), 370 VMSTATE_UINT8(dac_index, TCXState), 371 VMSTATE_UINT8(dac_state, TCXState), 372 VMSTATE_END_OF_LIST() 373 } 374 }; 375 376 static void tcx_reset(DeviceState *d) 377 { 378 TCXState *s = TCX(d); 379 380 /* Initialize palette */ 381 memset(s->r, 0, 260); 382 memset(s->g, 0, 260); 383 memset(s->b, 0, 260); 384 s->r[255] = s->g[255] = s->b[255] = 255; 385 s->r[256] = s->g[256] = s->b[256] = 255; 386 s->r[258] = s->g[258] = s->b[258] = 255; 387 update_palette_entries(s, 0, 260); 388 memset(s->vram, 0, MAXX*MAXY); 389 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), 390 DIRTY_MEMORY_VGA); 391 s->dac_index = 0; 392 s->dac_state = 0; 393 s->cursx = 0xf000; /* Put cursor off screen */ 394 s->cursy = 0xf000; 395 } 396 397 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, 398 unsigned size) 399 { 400 TCXState *s = opaque; 401 uint32_t val = 0; 402 403 switch (s->dac_state) { 404 case 0: 405 val = s->r[s->dac_index] << 24; 406 s->dac_state++; 407 break; 408 case 1: 409 val = s->g[s->dac_index] << 24; 410 s->dac_state++; 411 break; 412 case 2: 413 val = s->b[s->dac_index] << 24; 414 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 415 /* fall through */ 416 default: 417 s->dac_state = 0; 418 break; 419 } 420 421 return val; 422 } 423 424 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, 425 unsigned size) 426 { 427 TCXState *s = opaque; 428 unsigned index; 429 430 switch (addr) { 431 case 0: /* Address */ 432 s->dac_index = val >> 24; 433 s->dac_state = 0; 434 break; 435 case 4: /* Pixel colours */ 436 case 12: /* Overlay (cursor) colours */ 437 if (addr & 8) { 438 index = (s->dac_index & 3) + 256; 439 } else { 440 index = s->dac_index; 441 } 442 switch (s->dac_state) { 443 case 0: 444 s->r[index] = val >> 24; 445 update_palette_entries(s, index, index + 1); 446 s->dac_state++; 447 break; 448 case 1: 449 s->g[index] = val >> 24; 450 update_palette_entries(s, index, index + 1); 451 s->dac_state++; 452 break; 453 case 2: 454 s->b[index] = val >> 24; 455 update_palette_entries(s, index, index + 1); 456 s->dac_index = (s->dac_index + 1) & 0xff; /* Index autoincrement */ 457 /* fall through */ 458 default: 459 s->dac_state = 0; 460 break; 461 } 462 break; 463 default: /* Control registers */ 464 break; 465 } 466 } 467 468 static const MemoryRegionOps tcx_dac_ops = { 469 .read = tcx_dac_readl, 470 .write = tcx_dac_writel, 471 .endianness = DEVICE_NATIVE_ENDIAN, 472 .valid = { 473 .min_access_size = 4, 474 .max_access_size = 4, 475 }, 476 }; 477 478 static uint64_t tcx_stip_readl(void *opaque, hwaddr addr, 479 unsigned size) 480 { 481 return 0; 482 } 483 484 static void tcx_stip_writel(void *opaque, hwaddr addr, 485 uint64_t val, unsigned size) 486 { 487 TCXState *s = opaque; 488 int i; 489 uint32_t col; 490 491 if (!(addr & 4)) { 492 s->tmpblit = val; 493 } else { 494 addr = (addr >> 3) & 0xfffff; 495 col = cpu_to_be32(s->tmpblit); 496 if (s->depth == 24) { 497 for (i = 0; i < 32; i++) { 498 if (val & 0x80000000) { 499 s->vram[addr + i] = s->tmpblit; 500 s->vram24[addr + i] = col; 501 } 502 val <<= 1; 503 } 504 } else { 505 for (i = 0; i < 32; i++) { 506 if (val & 0x80000000) { 507 s->vram[addr + i] = s->tmpblit; 508 } 509 val <<= 1; 510 } 511 } 512 tcx_set_dirty(s, addr, 32); 513 } 514 } 515 516 static void tcx_rstip_writel(void *opaque, hwaddr addr, 517 uint64_t val, unsigned size) 518 { 519 TCXState *s = opaque; 520 int i; 521 uint32_t col; 522 523 if (!(addr & 4)) { 524 s->tmpblit = val; 525 } else { 526 addr = (addr >> 3) & 0xfffff; 527 col = cpu_to_be32(s->tmpblit); 528 if (s->depth == 24) { 529 for (i = 0; i < 32; i++) { 530 if (val & 0x80000000) { 531 s->vram[addr + i] = s->tmpblit; 532 s->vram24[addr + i] = col; 533 s->cplane[addr + i] = col; 534 } 535 val <<= 1; 536 } 537 } else { 538 for (i = 0; i < 32; i++) { 539 if (val & 0x80000000) { 540 s->vram[addr + i] = s->tmpblit; 541 } 542 val <<= 1; 543 } 544 } 545 tcx_set_dirty(s, addr, 32); 546 } 547 } 548 549 static const MemoryRegionOps tcx_stip_ops = { 550 .read = tcx_stip_readl, 551 .write = tcx_stip_writel, 552 .endianness = DEVICE_NATIVE_ENDIAN, 553 .valid = { 554 .min_access_size = 4, 555 .max_access_size = 4, 556 }, 557 }; 558 559 static const MemoryRegionOps tcx_rstip_ops = { 560 .read = tcx_stip_readl, 561 .write = tcx_rstip_writel, 562 .endianness = DEVICE_NATIVE_ENDIAN, 563 .valid = { 564 .min_access_size = 4, 565 .max_access_size = 4, 566 }, 567 }; 568 569 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, 570 unsigned size) 571 { 572 return 0; 573 } 574 575 static void tcx_blit_writel(void *opaque, hwaddr addr, 576 uint64_t val, unsigned size) 577 { 578 TCXState *s = opaque; 579 uint32_t adsr, len; 580 int i; 581 582 if (!(addr & 4)) { 583 s->tmpblit = val; 584 } else { 585 addr = (addr >> 3) & 0xfffff; 586 adsr = val & 0xffffff; 587 len = ((val >> 24) & 0x1f) + 1; 588 if (adsr == 0xffffff) { 589 memset(&s->vram[addr], s->tmpblit, len); 590 if (s->depth == 24) { 591 val = s->tmpblit & 0xffffff; 592 val = cpu_to_be32(val); 593 for (i = 0; i < len; i++) { 594 s->vram24[addr + i] = val; 595 } 596 } 597 } else { 598 memcpy(&s->vram[addr], &s->vram[adsr], len); 599 if (s->depth == 24) { 600 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 601 } 602 } 603 tcx_set_dirty(s, addr, len); 604 } 605 } 606 607 static void tcx_rblit_writel(void *opaque, hwaddr addr, 608 uint64_t val, unsigned size) 609 { 610 TCXState *s = opaque; 611 uint32_t adsr, len; 612 int i; 613 614 if (!(addr & 4)) { 615 s->tmpblit = val; 616 } else { 617 addr = (addr >> 3) & 0xfffff; 618 adsr = val & 0xffffff; 619 len = ((val >> 24) & 0x1f) + 1; 620 if (adsr == 0xffffff) { 621 memset(&s->vram[addr], s->tmpblit, len); 622 if (s->depth == 24) { 623 val = s->tmpblit & 0xffffff; 624 val = cpu_to_be32(val); 625 for (i = 0; i < len; i++) { 626 s->vram24[addr + i] = val; 627 s->cplane[addr + i] = val; 628 } 629 } 630 } else { 631 memcpy(&s->vram[addr], &s->vram[adsr], len); 632 if (s->depth == 24) { 633 memcpy(&s->vram24[addr], &s->vram24[adsr], len * 4); 634 memcpy(&s->cplane[addr], &s->cplane[adsr], len * 4); 635 } 636 } 637 tcx_set_dirty(s, addr, len); 638 } 639 } 640 641 static const MemoryRegionOps tcx_blit_ops = { 642 .read = tcx_blit_readl, 643 .write = tcx_blit_writel, 644 .endianness = DEVICE_NATIVE_ENDIAN, 645 .valid = { 646 .min_access_size = 4, 647 .max_access_size = 4, 648 }, 649 }; 650 651 static const MemoryRegionOps tcx_rblit_ops = { 652 .read = tcx_blit_readl, 653 .write = tcx_rblit_writel, 654 .endianness = DEVICE_NATIVE_ENDIAN, 655 .valid = { 656 .min_access_size = 4, 657 .max_access_size = 4, 658 }, 659 }; 660 661 static void tcx_invalidate_cursor_position(TCXState *s) 662 { 663 int ymin, ymax, start, end; 664 665 /* invalidate only near the cursor */ 666 ymin = s->cursy; 667 if (ymin >= s->height) { 668 return; 669 } 670 ymax = MIN(s->height, ymin + 32); 671 start = ymin * 1024; 672 end = ymax * 1024; 673 674 tcx_set_dirty(s, start, end - start); 675 } 676 677 static uint64_t tcx_thc_readl(void *opaque, hwaddr addr, 678 unsigned size) 679 { 680 TCXState *s = opaque; 681 uint64_t val; 682 683 if (addr == TCX_THC_MISC) { 684 val = s->thcmisc | 0x02000000; 685 } else { 686 val = 0; 687 } 688 return val; 689 } 690 691 static void tcx_thc_writel(void *opaque, hwaddr addr, 692 uint64_t val, unsigned size) 693 { 694 TCXState *s = opaque; 695 696 if (addr == TCX_THC_CURSXY) { 697 tcx_invalidate_cursor_position(s); 698 s->cursx = val >> 16; 699 s->cursy = val; 700 tcx_invalidate_cursor_position(s); 701 } else if (addr >= TCX_THC_CURSMASK && addr < TCX_THC_CURSMASK + 128) { 702 s->cursmask[(addr - TCX_THC_CURSMASK) >> 2] = val; 703 tcx_invalidate_cursor_position(s); 704 } else if (addr >= TCX_THC_CURSBITS && addr < TCX_THC_CURSBITS + 128) { 705 s->cursbits[(addr - TCX_THC_CURSBITS) >> 2] = val; 706 tcx_invalidate_cursor_position(s); 707 } else if (addr == TCX_THC_MISC) { 708 s->thcmisc = val; 709 } 710 711 } 712 713 static const MemoryRegionOps tcx_thc_ops = { 714 .read = tcx_thc_readl, 715 .write = tcx_thc_writel, 716 .endianness = DEVICE_NATIVE_ENDIAN, 717 .valid = { 718 .min_access_size = 4, 719 .max_access_size = 4, 720 }, 721 }; 722 723 static uint64_t tcx_dummy_readl(void *opaque, hwaddr addr, 724 unsigned size) 725 { 726 return 0; 727 } 728 729 static void tcx_dummy_writel(void *opaque, hwaddr addr, 730 uint64_t val, unsigned size) 731 { 732 return; 733 } 734 735 static const MemoryRegionOps tcx_dummy_ops = { 736 .read = tcx_dummy_readl, 737 .write = tcx_dummy_writel, 738 .endianness = DEVICE_NATIVE_ENDIAN, 739 .valid = { 740 .min_access_size = 4, 741 .max_access_size = 4, 742 }, 743 }; 744 745 static const GraphicHwOps tcx_ops = { 746 .invalidate = tcx_invalidate_display, 747 .gfx_update = tcx_update_display, 748 }; 749 750 static const GraphicHwOps tcx24_ops = { 751 .invalidate = tcx24_invalidate_display, 752 .gfx_update = tcx24_update_display, 753 }; 754 755 static void tcx_initfn(Object *obj) 756 { 757 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 758 TCXState *s = TCX(obj); 759 760 memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom", 761 FCODE_MAX_ROM_SIZE, &error_fatal); 762 sysbus_init_mmio(sbd, &s->rom); 763 764 /* 2/STIP : Stippler */ 765 memory_region_init_io(&s->stip, obj, &tcx_stip_ops, s, "tcx.stip", 766 TCX_STIP_NREGS); 767 sysbus_init_mmio(sbd, &s->stip); 768 769 /* 3/BLIT : Blitter */ 770 memory_region_init_io(&s->blit, obj, &tcx_blit_ops, s, "tcx.blit", 771 TCX_BLIT_NREGS); 772 sysbus_init_mmio(sbd, &s->blit); 773 774 /* 5/RSTIP : Raw Stippler */ 775 memory_region_init_io(&s->rstip, obj, &tcx_rstip_ops, s, "tcx.rstip", 776 TCX_RSTIP_NREGS); 777 sysbus_init_mmio(sbd, &s->rstip); 778 779 /* 6/RBLIT : Raw Blitter */ 780 memory_region_init_io(&s->rblit, obj, &tcx_rblit_ops, s, "tcx.rblit", 781 TCX_RBLIT_NREGS); 782 sysbus_init_mmio(sbd, &s->rblit); 783 784 /* 7/TEC : ??? */ 785 memory_region_init_io(&s->tec, obj, &tcx_dummy_ops, s, "tcx.tec", 786 TCX_TEC_NREGS); 787 sysbus_init_mmio(sbd, &s->tec); 788 789 /* 8/CMAP : DAC */ 790 memory_region_init_io(&s->dac, obj, &tcx_dac_ops, s, "tcx.dac", 791 TCX_DAC_NREGS); 792 sysbus_init_mmio(sbd, &s->dac); 793 794 /* 9/THC : Cursor */ 795 memory_region_init_io(&s->thc, obj, &tcx_thc_ops, s, "tcx.thc", 796 TCX_THC_NREGS); 797 sysbus_init_mmio(sbd, &s->thc); 798 799 /* 11/DHC : ??? */ 800 memory_region_init_io(&s->dhc, obj, &tcx_dummy_ops, s, "tcx.dhc", 801 TCX_DHC_NREGS); 802 sysbus_init_mmio(sbd, &s->dhc); 803 804 /* 12/ALT : ??? */ 805 memory_region_init_io(&s->alt, obj, &tcx_dummy_ops, s, "tcx.alt", 806 TCX_ALT_NREGS); 807 sysbus_init_mmio(sbd, &s->alt); 808 } 809 810 static void tcx_realizefn(DeviceState *dev, Error **errp) 811 { 812 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 813 TCXState *s = TCX(dev); 814 ram_addr_t vram_offset = 0; 815 int size, ret; 816 uint8_t *vram_base; 817 char *fcode_filename; 818 819 memory_region_init_ram_nomigrate(&s->vram_mem, OBJECT(s), "tcx.vram", 820 s->vram_size * (1 + 4 + 4), &error_fatal); 821 vmstate_register_ram_global(&s->vram_mem); 822 memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); 823 vram_base = memory_region_get_ram_ptr(&s->vram_mem); 824 825 /* 10/ROM : FCode ROM */ 826 vmstate_register_ram_global(&s->rom); 827 fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, TCX_ROM_FILE); 828 if (fcode_filename) { 829 ret = load_image_mr(fcode_filename, &s->rom); 830 g_free(fcode_filename); 831 if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) { 832 warn_report("tcx: could not load prom '%s'", TCX_ROM_FILE); 833 } 834 } 835 836 /* 0/DFB8 : 8-bit plane */ 837 s->vram = vram_base; 838 size = s->vram_size; 839 memory_region_init_alias(&s->vram_8bit, OBJECT(s), "tcx.vram.8bit", 840 &s->vram_mem, vram_offset, size); 841 sysbus_init_mmio(sbd, &s->vram_8bit); 842 vram_offset += size; 843 vram_base += size; 844 845 /* 1/DFB24 : 24bit plane */ 846 size = s->vram_size * 4; 847 s->vram24 = (uint32_t *)vram_base; 848 s->vram24_offset = vram_offset; 849 memory_region_init_alias(&s->vram_24bit, OBJECT(s), "tcx.vram.24bit", 850 &s->vram_mem, vram_offset, size); 851 sysbus_init_mmio(sbd, &s->vram_24bit); 852 vram_offset += size; 853 vram_base += size; 854 855 /* 4/RDFB32 : Raw Framebuffer */ 856 size = s->vram_size * 4; 857 s->cplane = (uint32_t *)vram_base; 858 s->cplane_offset = vram_offset; 859 memory_region_init_alias(&s->vram_cplane, OBJECT(s), "tcx.vram.cplane", 860 &s->vram_mem, vram_offset, size); 861 sysbus_init_mmio(sbd, &s->vram_cplane); 862 863 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 864 if (s->depth == 8) { 865 memory_region_init_io(&s->thc24, OBJECT(s), &tcx_dummy_ops, s, 866 "tcx.thc24", TCX_THC_NREGS); 867 sysbus_init_mmio(sbd, &s->thc24); 868 } 869 870 sysbus_init_irq(sbd, &s->irq); 871 872 if (s->depth == 8) { 873 s->con = graphic_console_init(dev, 0, &tcx_ops, s); 874 } else { 875 s->con = graphic_console_init(dev, 0, &tcx24_ops, s); 876 } 877 s->thcmisc = 0; 878 879 qemu_console_resize(s->con, s->width, s->height); 880 } 881 882 static Property tcx_properties[] = { 883 DEFINE_PROP_UINT32("vram_size", TCXState, vram_size, -1), 884 DEFINE_PROP_UINT16("width", TCXState, width, -1), 885 DEFINE_PROP_UINT16("height", TCXState, height, -1), 886 DEFINE_PROP_UINT16("depth", TCXState, depth, -1), 887 DEFINE_PROP_END_OF_LIST(), 888 }; 889 890 static void tcx_class_init(ObjectClass *klass, void *data) 891 { 892 DeviceClass *dc = DEVICE_CLASS(klass); 893 894 dc->realize = tcx_realizefn; 895 dc->reset = tcx_reset; 896 dc->vmsd = &vmstate_tcx; 897 device_class_set_props(dc, tcx_properties); 898 } 899 900 static const TypeInfo tcx_info = { 901 .name = TYPE_TCX, 902 .parent = TYPE_SYS_BUS_DEVICE, 903 .instance_size = sizeof(TCXState), 904 .instance_init = tcx_initfn, 905 .class_init = tcx_class_init, 906 }; 907 908 static void tcx_register_types(void) 909 { 910 type_register_static(&tcx_info); 911 } 912 913 type_init(tcx_register_types) 914