1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_homer.h" 31 #include "hw/ppc/pnv_xive.h" 32 #include "hw/ppc/pnv_core.h" 33 #include "hw/pci-host/pnv_phb3.h" 34 #include "hw/pci-host/pnv_phb4.h" 35 #include "qom/object.h" 36 37 #define TYPE_PNV_CHIP "pnv-chip" 38 typedef struct PnvChip PnvChip; 39 typedef struct PnvChipClass PnvChipClass; 40 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 41 #define PNV_CHIP_CLASS(klass) \ 42 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 43 #define PNV_CHIP_GET_CLASS(obj) \ 44 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 45 46 struct PnvChip { 47 /*< private >*/ 48 SysBusDevice parent_obj; 49 50 /*< public >*/ 51 uint32_t chip_id; 52 uint64_t ram_start; 53 uint64_t ram_size; 54 55 uint32_t nr_cores; 56 uint32_t nr_threads; 57 uint64_t cores_mask; 58 PnvCore **cores; 59 60 uint32_t num_phbs; 61 62 MemoryRegion xscom_mmio; 63 MemoryRegion xscom; 64 AddressSpace xscom_as; 65 66 gchar *dt_isa_nodename; 67 }; 68 69 #define TYPE_PNV8_CHIP "pnv8-chip" 70 typedef struct Pnv8Chip Pnv8Chip; 71 #define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP) 72 73 struct Pnv8Chip { 74 /*< private >*/ 75 PnvChip parent_obj; 76 77 /*< public >*/ 78 MemoryRegion icp_mmio; 79 80 PnvLpcController lpc; 81 Pnv8Psi psi; 82 PnvOCC occ; 83 PnvHomer homer; 84 85 #define PNV8_CHIP_PHB3_MAX 4 86 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; 87 88 XICSFabric *xics; 89 }; 90 91 #define TYPE_PNV9_CHIP "pnv9-chip" 92 typedef struct Pnv9Chip Pnv9Chip; 93 #define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP) 94 95 struct Pnv9Chip { 96 /*< private >*/ 97 PnvChip parent_obj; 98 99 /*< public >*/ 100 PnvXive xive; 101 Pnv9Psi psi; 102 PnvLpcController lpc; 103 PnvOCC occ; 104 PnvHomer homer; 105 106 uint32_t nr_quads; 107 PnvQuad *quads; 108 109 #define PNV9_CHIP_MAX_PEC 3 110 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 111 }; 112 113 /* 114 * A SMT8 fused core is a pair of SMT4 cores. 115 */ 116 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 117 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 118 119 #define TYPE_PNV10_CHIP "pnv10-chip" 120 typedef struct Pnv10Chip Pnv10Chip; 121 #define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) 122 123 struct Pnv10Chip { 124 /*< private >*/ 125 PnvChip parent_obj; 126 127 /*< public >*/ 128 Pnv9Psi psi; 129 PnvLpcController lpc; 130 }; 131 132 struct PnvChipClass { 133 /*< private >*/ 134 SysBusDeviceClass parent_class; 135 136 /*< public >*/ 137 uint64_t chip_cfam_id; 138 uint64_t cores_mask; 139 uint32_t num_phbs; 140 141 DeviceRealize parent_realize; 142 143 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 144 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 145 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 146 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 147 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 148 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 149 void (*dt_populate)(PnvChip *chip, void *fdt); 150 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 151 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 152 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 153 }; 154 155 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 156 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 157 158 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 159 #define PNV_CHIP_POWER8E(obj) \ 160 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 161 162 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 163 #define PNV_CHIP_POWER8(obj) \ 164 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 165 166 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 167 #define PNV_CHIP_POWER8NVL(obj) \ 168 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 169 170 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 171 #define PNV_CHIP_POWER9(obj) \ 172 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 173 174 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") 175 #define PNV_CHIP_POWER10(obj) \ 176 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) 177 178 /* 179 * This generates a HW chip id depending on an index, as found on a 180 * two socket system with dual chip modules : 181 * 182 * 0x0, 0x1, 0x10, 0x11 183 * 184 * 4 chips should be the maximum 185 * 186 * TODO: use a machine property to define the chip ids 187 */ 188 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 189 190 /* 191 * Converts back a HW chip id to an index. This is useful to calculate 192 * the MMIO addresses of some controllers which depend on the chip id. 193 */ 194 #define PNV_CHIP_INDEX(chip) \ 195 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 196 197 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 198 199 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 200 typedef struct PnvMachineClass PnvMachineClass; 201 typedef struct PnvMachineState PnvMachineState; 202 #define PNV_MACHINE(obj) \ 203 OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) 204 #define PNV_MACHINE_GET_CLASS(obj) \ 205 OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) 206 #define PNV_MACHINE_CLASS(klass) \ 207 OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) 208 209 210 struct PnvMachineClass { 211 /*< private >*/ 212 MachineClass parent_class; 213 214 /*< public >*/ 215 const char *compat; 216 int compat_size; 217 218 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 219 }; 220 221 struct PnvMachineState { 222 /*< private >*/ 223 MachineState parent_obj; 224 225 uint32_t initrd_base; 226 long initrd_size; 227 228 uint32_t num_chips; 229 PnvChip **chips; 230 231 ISABus *isa_bus; 232 uint32_t cpld_irqstate; 233 234 IPMIBmc *bmc; 235 Notifier powerdown_notifier; 236 237 PnvPnor *pnor; 238 239 hwaddr fw_load_addr; 240 }; 241 242 #define PNV_FDT_ADDR 0x01000000 243 #define PNV_TIMEBASE_FREQ 512000000ULL 244 245 /* 246 * BMC helpers 247 */ 248 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 249 void pnv_bmc_powerdown(IPMIBmc *bmc); 250 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 251 IPMIBmc *pnv_bmc_find(Error **errp); 252 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); 253 254 /* 255 * POWER8 MMIO base addresses 256 */ 257 #define PNV_XSCOM_SIZE 0x800000000ull 258 #define PNV_XSCOM_BASE(chip) \ 259 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 260 261 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 262 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 263 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 264 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 265 266 #define PNV_HOMER_SIZE 0x0000000000400000ull 267 #define PNV_HOMER_BASE(chip) \ 268 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) 269 270 271 /* 272 * XSCOM 0x20109CA defines the ICP BAR: 273 * 274 * 0:29 : bits 14 to 43 of address to define 1 MB region. 275 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 276 * 31:63 : Constant 0 277 * 278 * Usually defined as : 279 * 280 * 0xffffe00200000000 -> 0x0003ffff80000000 281 * 0xffffe00600000000 -> 0x0003ffff80100000 282 * 0xffffe02200000000 -> 0x0003ffff80800000 283 * 0xffffe02600000000 -> 0x0003ffff80900000 284 */ 285 #define PNV_ICP_SIZE 0x0000000000100000ull 286 #define PNV_ICP_BASE(chip) \ 287 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 288 289 290 #define PNV_PSIHB_SIZE 0x0000000000100000ull 291 #define PNV_PSIHB_BASE(chip) \ 292 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 293 294 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 295 #define PNV_PSIHB_FSP_BASE(chip) \ 296 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 297 PNV_PSIHB_FSP_SIZE) 298 299 /* 300 * POWER9 MMIO base addresses 301 */ 302 #define PNV9_CHIP_BASE(chip, base) \ 303 ((base) + ((uint64_t) (chip)->chip_id << 42)) 304 305 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 306 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 307 308 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 309 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 310 311 #define PNV9_LPCM_SIZE 0x0000000100000000ull 312 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 313 314 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 315 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 316 317 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 318 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 319 320 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 321 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 322 323 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 324 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 325 326 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 327 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 328 329 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 330 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 331 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 332 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) 333 334 #define PNV9_HOMER_SIZE 0x0000000000400000ull 335 #define PNV9_HOMER_BASE(chip) \ 336 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) 337 338 /* 339 * POWER10 MMIO base addresses - 16TB stride per chip 340 */ 341 #define PNV10_CHIP_BASE(chip, base) \ 342 ((base) + ((uint64_t) (chip)->chip_id << 44)) 343 344 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 345 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 346 347 #define PNV10_LPCM_SIZE 0x0000000100000000ull 348 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 349 350 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 351 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 352 353 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 354 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 355 356 #endif /* PPC_PNV_H */ 357