1 /* 2 * APIC support 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/> 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "qemu/thread.h" 22 #include "hw/i386/apic_internal.h" 23 #include "hw/i386/apic.h" 24 #include "hw/i386/ioapic.h" 25 #include "hw/intc/i8259.h" 26 #include "hw/pci/msi.h" 27 #include "qemu/host-utils.h" 28 #include "trace.h" 29 #include "hw/i386/apic-msidef.h" 30 #include "qapi/error.h" 31 #include "qom/object.h" 32 33 #define MAX_APICS 255 34 #define MAX_APIC_WORDS 8 35 36 #define SYNC_FROM_VAPIC 0x1 37 #define SYNC_TO_VAPIC 0x2 38 #define SYNC_ISR_IRR_TO_VAPIC 0x4 39 40 static APICCommonState *local_apics[MAX_APICS + 1]; 41 42 #define TYPE_APIC "apic" 43 #define APIC(obj) \ 44 OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC) 45 46 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode); 47 static void apic_update_irq(APICCommonState *s); 48 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 49 uint8_t dest, uint8_t dest_mode); 50 51 /* Find first bit starting from msb */ 52 static int apic_fls_bit(uint32_t value) 53 { 54 return 31 - clz32(value); 55 } 56 57 /* Find first bit starting from lsb */ 58 static int apic_ffs_bit(uint32_t value) 59 { 60 return ctz32(value); 61 } 62 63 static inline void apic_reset_bit(uint32_t *tab, int index) 64 { 65 int i, mask; 66 i = index >> 5; 67 mask = 1 << (index & 0x1f); 68 tab[i] &= ~mask; 69 } 70 71 /* return -1 if no bit is set */ 72 static int get_highest_priority_int(uint32_t *tab) 73 { 74 int i; 75 for (i = 7; i >= 0; i--) { 76 if (tab[i] != 0) { 77 return i * 32 + apic_fls_bit(tab[i]); 78 } 79 } 80 return -1; 81 } 82 83 static void apic_sync_vapic(APICCommonState *s, int sync_type) 84 { 85 VAPICState vapic_state; 86 size_t length; 87 off_t start; 88 int vector; 89 90 if (!s->vapic_paddr) { 91 return; 92 } 93 if (sync_type & SYNC_FROM_VAPIC) { 94 cpu_physical_memory_read(s->vapic_paddr, &vapic_state, 95 sizeof(vapic_state)); 96 s->tpr = vapic_state.tpr; 97 } 98 if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) { 99 start = offsetof(VAPICState, isr); 100 length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); 101 102 if (sync_type & SYNC_TO_VAPIC) { 103 assert(qemu_cpu_is_self(CPU(s->cpu))); 104 105 vapic_state.tpr = s->tpr; 106 vapic_state.enabled = 1; 107 start = 0; 108 length = sizeof(VAPICState); 109 } 110 111 vector = get_highest_priority_int(s->isr); 112 if (vector < 0) { 113 vector = 0; 114 } 115 vapic_state.isr = vector & 0xf0; 116 117 vapic_state.zero = 0; 118 119 vector = get_highest_priority_int(s->irr); 120 if (vector < 0) { 121 vector = 0; 122 } 123 vapic_state.irr = vector & 0xff; 124 125 address_space_write_rom(&address_space_memory, 126 s->vapic_paddr + start, 127 MEMTXATTRS_UNSPECIFIED, 128 ((void *)&vapic_state) + start, length); 129 } 130 } 131 132 static void apic_vapic_base_update(APICCommonState *s) 133 { 134 apic_sync_vapic(s, SYNC_TO_VAPIC); 135 } 136 137 static void apic_local_deliver(APICCommonState *s, int vector) 138 { 139 uint32_t lvt = s->lvt[vector]; 140 int trigger_mode; 141 142 trace_apic_local_deliver(vector, (lvt >> 8) & 7); 143 144 if (lvt & APIC_LVT_MASKED) 145 return; 146 147 switch ((lvt >> 8) & 7) { 148 case APIC_DM_SMI: 149 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI); 150 break; 151 152 case APIC_DM_NMI: 153 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI); 154 break; 155 156 case APIC_DM_EXTINT: 157 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD); 158 break; 159 160 case APIC_DM_FIXED: 161 trigger_mode = APIC_TRIGGER_EDGE; 162 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) && 163 (lvt & APIC_LVT_LEVEL_TRIGGER)) 164 trigger_mode = APIC_TRIGGER_LEVEL; 165 apic_set_irq(s, lvt & 0xff, trigger_mode); 166 } 167 } 168 169 void apic_deliver_pic_intr(DeviceState *dev, int level) 170 { 171 APICCommonState *s = APIC(dev); 172 173 if (level) { 174 apic_local_deliver(s, APIC_LVT_LINT0); 175 } else { 176 uint32_t lvt = s->lvt[APIC_LVT_LINT0]; 177 178 switch ((lvt >> 8) & 7) { 179 case APIC_DM_FIXED: 180 if (!(lvt & APIC_LVT_LEVEL_TRIGGER)) 181 break; 182 apic_reset_bit(s->irr, lvt & 0xff); 183 /* fall through */ 184 case APIC_DM_EXTINT: 185 apic_update_irq(s); 186 break; 187 } 188 } 189 } 190 191 static void apic_external_nmi(APICCommonState *s) 192 { 193 apic_local_deliver(s, APIC_LVT_LINT1); 194 } 195 196 #define foreach_apic(apic, deliver_bitmask, code) \ 197 {\ 198 int __i, __j;\ 199 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ 200 uint32_t __mask = deliver_bitmask[__i];\ 201 if (__mask) {\ 202 for(__j = 0; __j < 32; __j++) {\ 203 if (__mask & (1U << __j)) {\ 204 apic = local_apics[__i * 32 + __j];\ 205 if (apic) {\ 206 code;\ 207 }\ 208 }\ 209 }\ 210 }\ 211 }\ 212 } 213 214 static void apic_bus_deliver(const uint32_t *deliver_bitmask, 215 uint8_t delivery_mode, uint8_t vector_num, 216 uint8_t trigger_mode) 217 { 218 APICCommonState *apic_iter; 219 220 switch (delivery_mode) { 221 case APIC_DM_LOWPRI: 222 /* XXX: search for focus processor, arbitration */ 223 { 224 int i, d; 225 d = -1; 226 for(i = 0; i < MAX_APIC_WORDS; i++) { 227 if (deliver_bitmask[i]) { 228 d = i * 32 + apic_ffs_bit(deliver_bitmask[i]); 229 break; 230 } 231 } 232 if (d >= 0) { 233 apic_iter = local_apics[d]; 234 if (apic_iter) { 235 apic_set_irq(apic_iter, vector_num, trigger_mode); 236 } 237 } 238 } 239 return; 240 241 case APIC_DM_FIXED: 242 break; 243 244 case APIC_DM_SMI: 245 foreach_apic(apic_iter, deliver_bitmask, 246 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI) 247 ); 248 return; 249 250 case APIC_DM_NMI: 251 foreach_apic(apic_iter, deliver_bitmask, 252 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI) 253 ); 254 return; 255 256 case APIC_DM_INIT: 257 /* normal INIT IPI sent to processors */ 258 foreach_apic(apic_iter, deliver_bitmask, 259 cpu_interrupt(CPU(apic_iter->cpu), 260 CPU_INTERRUPT_INIT) 261 ); 262 return; 263 264 case APIC_DM_EXTINT: 265 /* handled in I/O APIC code */ 266 break; 267 268 default: 269 return; 270 } 271 272 foreach_apic(apic_iter, deliver_bitmask, 273 apic_set_irq(apic_iter, vector_num, trigger_mode) ); 274 } 275 276 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, 277 uint8_t vector_num, uint8_t trigger_mode) 278 { 279 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 280 281 trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num, 282 trigger_mode); 283 284 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 285 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 286 } 287 288 static void apic_set_base(APICCommonState *s, uint64_t val) 289 { 290 s->apicbase = (val & 0xfffff000) | 291 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); 292 /* if disabled, cannot be enabled again */ 293 if (!(val & MSR_IA32_APICBASE_ENABLE)) { 294 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; 295 cpu_clear_apic_feature(&s->cpu->env); 296 s->spurious_vec &= ~APIC_SV_ENABLE; 297 } 298 } 299 300 static void apic_set_tpr(APICCommonState *s, uint8_t val) 301 { 302 /* Updates from cr8 are ignored while the VAPIC is active */ 303 if (!s->vapic_paddr) { 304 s->tpr = val << 4; 305 apic_update_irq(s); 306 } 307 } 308 309 int apic_get_highest_priority_irr(DeviceState *dev) 310 { 311 APICCommonState *s; 312 313 if (!dev) { 314 /* no interrupts */ 315 return -1; 316 } 317 s = APIC_COMMON(dev); 318 return get_highest_priority_int(s->irr); 319 } 320 321 static uint8_t apic_get_tpr(APICCommonState *s) 322 { 323 apic_sync_vapic(s, SYNC_FROM_VAPIC); 324 return s->tpr >> 4; 325 } 326 327 int apic_get_ppr(APICCommonState *s) 328 { 329 int tpr, isrv, ppr; 330 331 tpr = (s->tpr >> 4); 332 isrv = get_highest_priority_int(s->isr); 333 if (isrv < 0) 334 isrv = 0; 335 isrv >>= 4; 336 if (tpr >= isrv) 337 ppr = s->tpr; 338 else 339 ppr = isrv << 4; 340 return ppr; 341 } 342 343 static int apic_get_arb_pri(APICCommonState *s) 344 { 345 /* XXX: arbitration */ 346 return 0; 347 } 348 349 350 /* 351 * <0 - low prio interrupt, 352 * 0 - no interrupt, 353 * >0 - interrupt number 354 */ 355 static int apic_irq_pending(APICCommonState *s) 356 { 357 int irrv, ppr; 358 359 if (!(s->spurious_vec & APIC_SV_ENABLE)) { 360 return 0; 361 } 362 363 irrv = get_highest_priority_int(s->irr); 364 if (irrv < 0) { 365 return 0; 366 } 367 ppr = apic_get_ppr(s); 368 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) { 369 return -1; 370 } 371 372 return irrv; 373 } 374 375 /* signal the CPU if an irq is pending */ 376 static void apic_update_irq(APICCommonState *s) 377 { 378 CPUState *cpu; 379 DeviceState *dev = (DeviceState *)s; 380 381 cpu = CPU(s->cpu); 382 if (!qemu_cpu_is_self(cpu)) { 383 cpu_interrupt(cpu, CPU_INTERRUPT_POLL); 384 } else if (apic_irq_pending(s) > 0) { 385 cpu_interrupt(cpu, CPU_INTERRUPT_HARD); 386 } else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 387 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); 388 } 389 } 390 391 void apic_poll_irq(DeviceState *dev) 392 { 393 APICCommonState *s = APIC(dev); 394 395 apic_sync_vapic(s, SYNC_FROM_VAPIC); 396 apic_update_irq(s); 397 } 398 399 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode) 400 { 401 apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num)); 402 403 apic_set_bit(s->irr, vector_num); 404 if (trigger_mode) 405 apic_set_bit(s->tmr, vector_num); 406 else 407 apic_reset_bit(s->tmr, vector_num); 408 if (s->vapic_paddr) { 409 apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC); 410 /* 411 * The vcpu thread needs to see the new IRR before we pull its current 412 * TPR value. That way, if we miss a lowering of the TRP, the guest 413 * has the chance to notice the new IRR and poll for IRQs on its own. 414 */ 415 smp_wmb(); 416 apic_sync_vapic(s, SYNC_FROM_VAPIC); 417 } 418 apic_update_irq(s); 419 } 420 421 static void apic_eoi(APICCommonState *s) 422 { 423 int isrv; 424 isrv = get_highest_priority_int(s->isr); 425 if (isrv < 0) 426 return; 427 apic_reset_bit(s->isr, isrv); 428 if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) { 429 ioapic_eoi_broadcast(isrv); 430 } 431 apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC); 432 apic_update_irq(s); 433 } 434 435 static int apic_find_dest(uint8_t dest) 436 { 437 APICCommonState *apic = local_apics[dest]; 438 int i; 439 440 if (apic && apic->id == dest) 441 return dest; /* shortcut in case apic->id == local_apics[dest]->id */ 442 443 for (i = 0; i < MAX_APICS; i++) { 444 apic = local_apics[i]; 445 if (apic && apic->id == dest) 446 return i; 447 if (!apic) 448 break; 449 } 450 451 return -1; 452 } 453 454 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 455 uint8_t dest, uint8_t dest_mode) 456 { 457 APICCommonState *apic_iter; 458 int i; 459 460 if (dest_mode == 0) { 461 if (dest == 0xff) { 462 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); 463 } else { 464 int idx = apic_find_dest(dest); 465 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 466 if (idx >= 0) 467 apic_set_bit(deliver_bitmask, idx); 468 } 469 } else { 470 /* XXX: cluster mode */ 471 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); 472 for(i = 0; i < MAX_APICS; i++) { 473 apic_iter = local_apics[i]; 474 if (apic_iter) { 475 if (apic_iter->dest_mode == 0xf) { 476 if (dest & apic_iter->log_dest) 477 apic_set_bit(deliver_bitmask, i); 478 } else if (apic_iter->dest_mode == 0x0) { 479 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && 480 (dest & apic_iter->log_dest & 0x0f)) { 481 apic_set_bit(deliver_bitmask, i); 482 } 483 } 484 } else { 485 break; 486 } 487 } 488 } 489 } 490 491 static void apic_startup(APICCommonState *s, int vector_num) 492 { 493 s->sipi_vector = vector_num; 494 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 495 } 496 497 void apic_sipi(DeviceState *dev) 498 { 499 APICCommonState *s = APIC(dev); 500 501 cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI); 502 503 if (!s->wait_for_sipi) 504 return; 505 cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); 506 s->wait_for_sipi = 0; 507 } 508 509 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode, 510 uint8_t delivery_mode, uint8_t vector_num, 511 uint8_t trigger_mode) 512 { 513 APICCommonState *s = APIC(dev); 514 uint32_t deliver_bitmask[MAX_APIC_WORDS]; 515 int dest_shorthand = (s->icr[0] >> 18) & 3; 516 APICCommonState *apic_iter; 517 518 switch (dest_shorthand) { 519 case 0: 520 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); 521 break; 522 case 1: 523 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); 524 apic_set_bit(deliver_bitmask, s->id); 525 break; 526 case 2: 527 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 528 break; 529 case 3: 530 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); 531 apic_reset_bit(deliver_bitmask, s->id); 532 break; 533 } 534 535 switch (delivery_mode) { 536 case APIC_DM_INIT: 537 { 538 int trig_mode = (s->icr[0] >> 15) & 1; 539 int level = (s->icr[0] >> 14) & 1; 540 if (level == 0 && trig_mode == 1) { 541 foreach_apic(apic_iter, deliver_bitmask, 542 apic_iter->arb_id = apic_iter->id ); 543 return; 544 } 545 } 546 break; 547 548 case APIC_DM_SIPI: 549 foreach_apic(apic_iter, deliver_bitmask, 550 apic_startup(apic_iter, vector_num) ); 551 return; 552 } 553 554 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode); 555 } 556 557 static bool apic_check_pic(APICCommonState *s) 558 { 559 DeviceState *dev = (DeviceState *)s; 560 561 if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) { 562 return false; 563 } 564 apic_deliver_pic_intr(dev, 1); 565 return true; 566 } 567 568 int apic_get_interrupt(DeviceState *dev) 569 { 570 APICCommonState *s = APIC(dev); 571 int intno; 572 573 /* if the APIC is installed or enabled, we let the 8259 handle the 574 IRQs */ 575 if (!s) 576 return -1; 577 if (!(s->spurious_vec & APIC_SV_ENABLE)) 578 return -1; 579 580 apic_sync_vapic(s, SYNC_FROM_VAPIC); 581 intno = apic_irq_pending(s); 582 583 /* if there is an interrupt from the 8259, let the caller handle 584 * that first since ExtINT interrupts ignore the priority. 585 */ 586 if (intno == 0 || apic_check_pic(s)) { 587 apic_sync_vapic(s, SYNC_TO_VAPIC); 588 return -1; 589 } else if (intno < 0) { 590 apic_sync_vapic(s, SYNC_TO_VAPIC); 591 return s->spurious_vec & 0xff; 592 } 593 apic_reset_bit(s->irr, intno); 594 apic_set_bit(s->isr, intno); 595 apic_sync_vapic(s, SYNC_TO_VAPIC); 596 597 apic_update_irq(s); 598 599 return intno; 600 } 601 602 int apic_accept_pic_intr(DeviceState *dev) 603 { 604 APICCommonState *s = APIC(dev); 605 uint32_t lvt0; 606 607 if (!s) 608 return -1; 609 610 lvt0 = s->lvt[APIC_LVT_LINT0]; 611 612 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || 613 (lvt0 & APIC_LVT_MASKED) == 0) 614 return isa_pic != NULL; 615 616 return 0; 617 } 618 619 static void apic_timer_update(APICCommonState *s, int64_t current_time) 620 { 621 if (apic_next_timer(s, current_time)) { 622 timer_mod(s->timer, s->next_time); 623 } else { 624 timer_del(s->timer); 625 } 626 } 627 628 static void apic_timer(void *opaque) 629 { 630 APICCommonState *s = opaque; 631 632 apic_local_deliver(s, APIC_LVT_TIMER); 633 apic_timer_update(s, s->next_time); 634 } 635 636 static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) 637 { 638 DeviceState *dev; 639 APICCommonState *s; 640 uint32_t val; 641 int index; 642 643 if (size < 4) { 644 return 0; 645 } 646 647 dev = cpu_get_current_apic(); 648 if (!dev) { 649 return 0; 650 } 651 s = APIC(dev); 652 653 index = (addr >> 4) & 0xff; 654 switch(index) { 655 case 0x02: /* id */ 656 val = s->id << 24; 657 break; 658 case 0x03: /* version */ 659 val = s->version | ((APIC_LVT_NB - 1) << 16); 660 break; 661 case 0x08: 662 apic_sync_vapic(s, SYNC_FROM_VAPIC); 663 if (apic_report_tpr_access) { 664 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); 665 } 666 val = s->tpr; 667 break; 668 case 0x09: 669 val = apic_get_arb_pri(s); 670 break; 671 case 0x0a: 672 /* ppr */ 673 val = apic_get_ppr(s); 674 break; 675 case 0x0b: 676 val = 0; 677 break; 678 case 0x0d: 679 val = s->log_dest << 24; 680 break; 681 case 0x0e: 682 val = (s->dest_mode << 28) | 0xfffffff; 683 break; 684 case 0x0f: 685 val = s->spurious_vec; 686 break; 687 case 0x10 ... 0x17: 688 val = s->isr[index & 7]; 689 break; 690 case 0x18 ... 0x1f: 691 val = s->tmr[index & 7]; 692 break; 693 case 0x20 ... 0x27: 694 val = s->irr[index & 7]; 695 break; 696 case 0x28: 697 val = s->esr; 698 break; 699 case 0x30: 700 case 0x31: 701 val = s->icr[index & 1]; 702 break; 703 case 0x32 ... 0x37: 704 val = s->lvt[index - 0x32]; 705 break; 706 case 0x38: 707 val = s->initial_count; 708 break; 709 case 0x39: 710 val = apic_get_current_count(s); 711 break; 712 case 0x3e: 713 val = s->divide_conf; 714 break; 715 default: 716 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 717 val = 0; 718 break; 719 } 720 trace_apic_mem_readl(addr, val); 721 return val; 722 } 723 724 static void apic_send_msi(MSIMessage *msi) 725 { 726 uint64_t addr = msi->address; 727 uint32_t data = msi->data; 728 uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; 729 uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; 730 uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; 731 uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; 732 uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; 733 /* XXX: Ignore redirection hint. */ 734 apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); 735 } 736 737 static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, 738 unsigned size) 739 { 740 DeviceState *dev; 741 APICCommonState *s; 742 int index = (addr >> 4) & 0xff; 743 744 if (size < 4) { 745 return; 746 } 747 748 if (addr > 0xfff || !index) { 749 /* MSI and MMIO APIC are at the same memory location, 750 * but actually not on the global bus: MSI is on PCI bus 751 * APIC is connected directly to the CPU. 752 * Mapping them on the global bus happens to work because 753 * MSI registers are reserved in APIC MMIO and vice versa. */ 754 MSIMessage msi = { .address = addr, .data = val }; 755 apic_send_msi(&msi); 756 return; 757 } 758 759 dev = cpu_get_current_apic(); 760 if (!dev) { 761 return; 762 } 763 s = APIC(dev); 764 765 trace_apic_mem_writel(addr, val); 766 767 switch(index) { 768 case 0x02: 769 s->id = (val >> 24); 770 break; 771 case 0x03: 772 break; 773 case 0x08: 774 if (apic_report_tpr_access) { 775 cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); 776 } 777 s->tpr = val; 778 apic_sync_vapic(s, SYNC_TO_VAPIC); 779 apic_update_irq(s); 780 break; 781 case 0x09: 782 case 0x0a: 783 break; 784 case 0x0b: /* EOI */ 785 apic_eoi(s); 786 break; 787 case 0x0d: 788 s->log_dest = val >> 24; 789 break; 790 case 0x0e: 791 s->dest_mode = val >> 28; 792 break; 793 case 0x0f: 794 s->spurious_vec = val & 0x1ff; 795 apic_update_irq(s); 796 break; 797 case 0x10 ... 0x17: 798 case 0x18 ... 0x1f: 799 case 0x20 ... 0x27: 800 case 0x28: 801 break; 802 case 0x30: 803 s->icr[0] = val; 804 apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, 805 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), 806 (s->icr[0] >> 15) & 1); 807 break; 808 case 0x31: 809 s->icr[1] = val; 810 break; 811 case 0x32 ... 0x37: 812 { 813 int n = index - 0x32; 814 s->lvt[n] = val; 815 if (n == APIC_LVT_TIMER) { 816 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 817 } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) { 818 apic_update_irq(s); 819 } 820 } 821 break; 822 case 0x38: 823 s->initial_count = val; 824 s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 825 apic_timer_update(s, s->initial_count_load_time); 826 break; 827 case 0x39: 828 break; 829 case 0x3e: 830 { 831 int v; 832 s->divide_conf = val & 0xb; 833 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); 834 s->count_shift = (v + 1) & 7; 835 } 836 break; 837 default: 838 s->esr |= APIC_ESR_ILLEGAL_ADDRESS; 839 break; 840 } 841 } 842 843 static void apic_pre_save(APICCommonState *s) 844 { 845 apic_sync_vapic(s, SYNC_FROM_VAPIC); 846 } 847 848 static void apic_post_load(APICCommonState *s) 849 { 850 if (s->timer_expiry != -1) { 851 timer_mod(s->timer, s->timer_expiry); 852 } else { 853 timer_del(s->timer); 854 } 855 } 856 857 static const MemoryRegionOps apic_io_ops = { 858 .read = apic_mem_read, 859 .write = apic_mem_write, 860 .impl.min_access_size = 1, 861 .impl.max_access_size = 4, 862 .valid.min_access_size = 1, 863 .valid.max_access_size = 4, 864 .endianness = DEVICE_NATIVE_ENDIAN, 865 }; 866 867 static void apic_realize(DeviceState *dev, Error **errp) 868 { 869 APICCommonState *s = APIC(dev); 870 871 if (s->id >= MAX_APICS) { 872 error_setg(errp, "%s initialization failed. APIC ID %d is invalid", 873 object_get_typename(OBJECT(dev)), s->id); 874 return; 875 } 876 877 memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi", 878 APIC_SPACE_SIZE); 879 880 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s); 881 local_apics[s->id] = s; 882 883 msi_nonbroken = true; 884 } 885 886 static void apic_unrealize(DeviceState *dev) 887 { 888 APICCommonState *s = APIC(dev); 889 890 timer_del(s->timer); 891 timer_free(s->timer); 892 local_apics[s->id] = NULL; 893 } 894 895 static void apic_class_init(ObjectClass *klass, void *data) 896 { 897 APICCommonClass *k = APIC_COMMON_CLASS(klass); 898 899 k->realize = apic_realize; 900 k->unrealize = apic_unrealize; 901 k->set_base = apic_set_base; 902 k->set_tpr = apic_set_tpr; 903 k->get_tpr = apic_get_tpr; 904 k->vapic_base_update = apic_vapic_base_update; 905 k->external_nmi = apic_external_nmi; 906 k->pre_save = apic_pre_save; 907 k->post_load = apic_post_load; 908 k->send_msi = apic_send_msi; 909 } 910 911 static const TypeInfo apic_info = { 912 .name = TYPE_APIC, 913 .instance_size = sizeof(APICCommonState), 914 .parent = TYPE_APIC_COMMON, 915 .class_init = apic_class_init, 916 }; 917 918 static void apic_register_types(void) 919 { 920 type_register_static(&apic_info); 921 } 922 923 type_init(apic_register_types) 924