1 #ifndef QEMU_HW_ESP_H 2 #define QEMU_HW_ESP_H 3 4 #include "hw/scsi/scsi.h" 5 #include "hw/sysbus.h" 6 #include "qom/object.h" 7 8 /* esp.c */ 9 #define ESP_MAX_DEVS 7 10 typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); 11 12 #define ESP_REGS 16 13 #define TI_BUFSZ 16 14 #define ESP_CMDBUF_SZ 32 15 16 typedef struct ESPState ESPState; 17 18 enum pdma_origin_id { 19 PDMA, 20 TI, 21 CMD, 22 ASYNC, 23 }; 24 25 struct ESPState { 26 uint8_t rregs[ESP_REGS]; 27 uint8_t wregs[ESP_REGS]; 28 qemu_irq irq; 29 qemu_irq irq_data; 30 uint8_t chip_id; 31 bool tchi_written; 32 int32_t ti_size; 33 uint32_t ti_rptr, ti_wptr; 34 uint32_t status; 35 uint32_t deferred_status; 36 bool deferred_complete; 37 uint32_t dma; 38 uint8_t ti_buf[TI_BUFSZ]; 39 SCSIBus bus; 40 SCSIDevice *current_dev; 41 SCSIRequest *current_req; 42 uint8_t cmdbuf[ESP_CMDBUF_SZ]; 43 uint32_t cmdlen; 44 uint32_t do_cmd; 45 46 /* The amount of data left in the current DMA transfer. */ 47 uint32_t dma_left; 48 /* The size of the current DMA transfer. Zero if no transfer is in 49 progress. */ 50 uint32_t dma_counter; 51 int dma_enabled; 52 53 uint32_t async_len; 54 uint8_t *async_buf; 55 56 ESPDMAMemoryReadWriteFunc dma_memory_read; 57 ESPDMAMemoryReadWriteFunc dma_memory_write; 58 void *dma_opaque; 59 void (*dma_cb)(ESPState *s); 60 uint8_t pdma_buf[32]; 61 int pdma_origin; 62 uint32_t pdma_len; 63 uint32_t pdma_start; 64 uint32_t pdma_cur; 65 void (*pdma_cb)(ESPState *s); 66 }; 67 68 #define TYPE_ESP "esp" 69 typedef struct SysBusESPState SysBusESPState; 70 #define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP) 71 72 struct SysBusESPState { 73 /*< private >*/ 74 SysBusDevice parent_obj; 75 /*< public >*/ 76 77 MemoryRegion iomem; 78 MemoryRegion pdma; 79 uint32_t it_shift; 80 ESPState esp; 81 }; 82 83 #define ESP_TCLO 0x0 84 #define ESP_TCMID 0x1 85 #define ESP_FIFO 0x2 86 #define ESP_CMD 0x3 87 #define ESP_RSTAT 0x4 88 #define ESP_WBUSID 0x4 89 #define ESP_RINTR 0x5 90 #define ESP_WSEL 0x5 91 #define ESP_RSEQ 0x6 92 #define ESP_WSYNTP 0x6 93 #define ESP_RFLAGS 0x7 94 #define ESP_WSYNO 0x7 95 #define ESP_CFG1 0x8 96 #define ESP_RRES1 0x9 97 #define ESP_WCCF 0x9 98 #define ESP_RRES2 0xa 99 #define ESP_WTEST 0xa 100 #define ESP_CFG2 0xb 101 #define ESP_CFG3 0xc 102 #define ESP_RES3 0xd 103 #define ESP_TCHI 0xe 104 #define ESP_RES4 0xf 105 106 #define CMD_DMA 0x80 107 #define CMD_CMD 0x7f 108 109 #define CMD_NOP 0x00 110 #define CMD_FLUSH 0x01 111 #define CMD_RESET 0x02 112 #define CMD_BUSRESET 0x03 113 #define CMD_TI 0x10 114 #define CMD_ICCS 0x11 115 #define CMD_MSGACC 0x12 116 #define CMD_PAD 0x18 117 #define CMD_SATN 0x1a 118 #define CMD_RSTATN 0x1b 119 #define CMD_SEL 0x41 120 #define CMD_SELATN 0x42 121 #define CMD_SELATNS 0x43 122 #define CMD_ENSEL 0x44 123 #define CMD_DISSEL 0x45 124 125 #define STAT_DO 0x00 126 #define STAT_DI 0x01 127 #define STAT_CD 0x02 128 #define STAT_ST 0x03 129 #define STAT_MO 0x06 130 #define STAT_MI 0x07 131 #define STAT_PIO_MASK 0x06 132 133 #define STAT_TC 0x10 134 #define STAT_PE 0x20 135 #define STAT_GE 0x40 136 #define STAT_INT 0x80 137 138 #define BUSID_DID 0x07 139 140 #define INTR_FC 0x08 141 #define INTR_BS 0x10 142 #define INTR_DC 0x20 143 #define INTR_RST 0x80 144 145 #define SEQ_0 0x0 146 #define SEQ_CD 0x4 147 148 #define CFG1_RESREPT 0x40 149 150 #define TCHI_FAS100A 0x4 151 #define TCHI_AM53C974 0x12 152 153 void esp_dma_enable(ESPState *s, int irq, int level); 154 void esp_request_cancelled(SCSIRequest *req); 155 void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid); 156 void esp_transfer_data(SCSIRequest *req, uint32_t len); 157 void esp_hard_reset(ESPState *s); 158 uint64_t esp_reg_read(ESPState *s, uint32_t saddr); 159 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val); 160 extern const VMStateDescription vmstate_esp; 161 162 #endif 163