1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2018 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #ifndef ASPEED_GPIO_H 11 #define ASPEED_GPIO_H 12 13 #include "hw/sysbus.h" 14 #include "qom/object.h" 15 16 #define TYPE_ASPEED_GPIO "aspeed.gpio" 17 typedef struct AspeedGPIOClass AspeedGPIOClass; 18 typedef struct AspeedGPIOState AspeedGPIOState; 19 #define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO) 20 #define ASPEED_GPIO_CLASS(klass) \ 21 OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO) 22 #define ASPEED_GPIO_GET_CLASS(obj) \ 23 OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO) 24 25 #define ASPEED_GPIO_MAX_NR_SETS 8 26 #define ASPEED_REGS_PER_BANK 14 27 #define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS) 28 #define ASPEED_GPIO_NR_PINS 228 29 #define ASPEED_GROUPS_PER_SET 4 30 #define ASPEED_GPIO_NR_DEBOUNCE_REGS 3 31 #define ASPEED_CHARS_PER_GROUP_LABEL 4 32 33 typedef struct GPIOSets GPIOSets; 34 35 typedef struct GPIOSetProperties { 36 uint32_t input; 37 uint32_t output; 38 char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL]; 39 } GPIOSetProperties; 40 41 enum GPIORegType { 42 gpio_not_a_reg, 43 gpio_reg_data_value, 44 gpio_reg_direction, 45 gpio_reg_int_enable, 46 gpio_reg_int_sens_0, 47 gpio_reg_int_sens_1, 48 gpio_reg_int_sens_2, 49 gpio_reg_int_status, 50 gpio_reg_reset_tolerant, 51 gpio_reg_debounce_1, 52 gpio_reg_debounce_2, 53 gpio_reg_cmd_source_0, 54 gpio_reg_cmd_source_1, 55 gpio_reg_data_read, 56 gpio_reg_input_mask, 57 }; 58 59 typedef struct AspeedGPIOReg { 60 uint16_t set_idx; 61 enum GPIORegType type; 62 } AspeedGPIOReg; 63 64 struct AspeedGPIOClass { 65 SysBusDevice parent_obj; 66 const GPIOSetProperties *props; 67 uint32_t nr_gpio_pins; 68 uint32_t nr_gpio_sets; 69 uint32_t gap; 70 const AspeedGPIOReg *reg_table; 71 }; 72 73 struct AspeedGPIOState { 74 /* <private> */ 75 SysBusDevice parent; 76 77 /*< public >*/ 78 MemoryRegion iomem; 79 int pending; 80 qemu_irq irq; 81 qemu_irq gpios[ASPEED_GPIO_NR_PINS]; 82 83 /* Parallel GPIO Registers */ 84 uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS]; 85 struct GPIOSets { 86 uint32_t data_value; /* Reflects pin values */ 87 uint32_t data_read; /* Contains last value written to data value */ 88 uint32_t direction; 89 uint32_t int_enable; 90 uint32_t int_sens_0; 91 uint32_t int_sens_1; 92 uint32_t int_sens_2; 93 uint32_t int_status; 94 uint32_t reset_tol; 95 uint32_t cmd_source_0; 96 uint32_t cmd_source_1; 97 uint32_t debounce_1; 98 uint32_t debounce_2; 99 uint32_t input_mask; 100 } sets[ASPEED_GPIO_MAX_NR_SETS]; 101 }; 102 103 #endif /* _ASPEED_GPIO_H_ */ 104