1 /* 2 * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface) 3 * 4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer 5 * Copyright (c) 2013 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/isa/isa.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/rtc/m48t59.h" 30 #include "m48t59-internal.h" 31 #include "qapi/error.h" 32 #include "qemu/module.h" 33 #include "qom/object.h" 34 35 #define TYPE_M48TXX_ISA "isa-m48txx" 36 typedef struct M48txxISADeviceClass M48txxISADeviceClass; 37 typedef struct M48txxISAState M48txxISAState; 38 #define M48TXX_ISA_GET_CLASS(obj) \ 39 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA) 40 #define M48TXX_ISA_CLASS(klass) \ 41 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) 42 #define M48TXX_ISA(obj) \ 43 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) 44 45 struct M48txxISAState { 46 ISADevice parent_obj; 47 M48t59State state; 48 uint32_t io_base; 49 MemoryRegion io; 50 }; 51 52 struct M48txxISADeviceClass { 53 ISADeviceClass parent_class; 54 M48txxInfo info; 55 }; 56 57 static M48txxInfo m48txx_isa_info[] = { 58 { 59 .bus_name = "isa-m48t59", 60 .model = 59, 61 .size = 0x2000, 62 } 63 }; 64 65 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, 66 int base_year, int model) 67 { 68 ISADevice *isa_dev; 69 DeviceState *dev; 70 int i; 71 72 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 73 if (m48txx_isa_info[i].size != size || 74 m48txx_isa_info[i].model != model) { 75 continue; 76 } 77 78 isa_dev = isa_new(m48txx_isa_info[i].bus_name); 79 dev = DEVICE(isa_dev); 80 qdev_prop_set_uint32(dev, "iobase", io_base); 81 qdev_prop_set_int32(dev, "base-year", base_year); 82 isa_realize_and_unref(isa_dev, bus, &error_fatal); 83 return NVRAM(dev); 84 } 85 86 assert(false); 87 return NULL; 88 } 89 90 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) 91 { 92 M48txxISAState *d = M48TXX_ISA(obj); 93 return m48t59_read(&d->state, addr); 94 } 95 96 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) 97 { 98 M48txxISAState *d = M48TXX_ISA(obj); 99 m48t59_write(&d->state, addr, val); 100 } 101 102 static void m48txx_isa_toggle_lock(Nvram *obj, int lock) 103 { 104 M48txxISAState *d = M48TXX_ISA(obj); 105 m48t59_toggle_lock(&d->state, lock); 106 } 107 108 static Property m48t59_isa_properties[] = { 109 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), 110 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), 111 DEFINE_PROP_END_OF_LIST(), 112 }; 113 114 static void m48t59_reset_isa(DeviceState *d) 115 { 116 M48txxISAState *isa = M48TXX_ISA(d); 117 M48t59State *NVRAM = &isa->state; 118 119 m48t59_reset_common(NVRAM); 120 } 121 122 static void m48t59_isa_realize(DeviceState *dev, Error **errp) 123 { 124 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev); 125 ISADevice *isadev = ISA_DEVICE(dev); 126 M48txxISAState *d = M48TXX_ISA(dev); 127 M48t59State *s = &d->state; 128 129 s->model = u->info.model; 130 s->size = u->info.size; 131 isa_init_irq(isadev, &s->IRQ, 8); 132 m48t59_realize_common(s, errp); 133 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4); 134 if (d->io_base != 0) { 135 isa_register_ioport(isadev, &d->io, d->io_base); 136 } 137 } 138 139 static void m48txx_isa_class_init(ObjectClass *klass, void *data) 140 { 141 DeviceClass *dc = DEVICE_CLASS(klass); 142 NvramClass *nc = NVRAM_CLASS(klass); 143 144 dc->realize = m48t59_isa_realize; 145 dc->reset = m48t59_reset_isa; 146 device_class_set_props(dc, m48t59_isa_properties); 147 nc->read = m48txx_isa_read; 148 nc->write = m48txx_isa_write; 149 nc->toggle_lock = m48txx_isa_toggle_lock; 150 } 151 152 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) 153 { 154 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); 155 M48txxInfo *info = data; 156 157 u->info = *info; 158 } 159 160 static const TypeInfo m48txx_isa_type_info = { 161 .name = TYPE_M48TXX_ISA, 162 .parent = TYPE_ISA_DEVICE, 163 .instance_size = sizeof(M48txxISAState), 164 .abstract = true, 165 .class_init = m48txx_isa_class_init, 166 .interfaces = (InterfaceInfo[]) { 167 { TYPE_NVRAM }, 168 { } 169 } 170 }; 171 172 static void m48t59_isa_register_types(void) 173 { 174 TypeInfo isa_type_info = { 175 .parent = TYPE_M48TXX_ISA, 176 .class_size = sizeof(M48txxISADeviceClass), 177 .class_init = m48txx_isa_concrete_class_init, 178 }; 179 int i; 180 181 type_register_static(&m48txx_isa_type_info); 182 183 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 184 isa_type_info.name = m48txx_isa_info[i].bus_name; 185 isa_type_info.class_data = &m48txx_isa_info[i]; 186 type_register(&isa_type_info); 187 } 188 } 189 190 type_init(m48t59_isa_register_types) 191