1 #ifndef HW_SPAPR_H 2 #define HW_SPAPR_H 3 4 #include "qemu/units.h" 5 #include "sysemu/dma.h" 6 #include "hw/boards.h" 7 #include "hw/ppc/spapr_drc.h" 8 #include "hw/mem/pc-dimm.h" 9 #include "hw/ppc/spapr_ovec.h" 10 #include "hw/ppc/spapr_irq.h" 11 #include "qom/object.h" 12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13 #include "hw/ppc/xics.h" /* For ICSState */ 14 #include "hw/ppc/spapr_tpm_proxy.h" 15 16 struct SpaprVioBus; 17 struct SpaprPhbState; 18 struct SpaprNvram; 19 20 typedef struct SpaprEventLogEntry SpaprEventLogEntry; 21 typedef struct SpaprEventSource SpaprEventSource; 22 typedef struct SpaprPendingHpt SpaprPendingHpt; 23 24 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 25 #define SPAPR_ENTRY_POINT 0x100 26 27 #define SPAPR_TIMEBASE_FREQ 512000000ULL 28 29 #define TYPE_SPAPR_RTC "spapr-rtc" 30 31 typedef struct SpaprRtcState SpaprRtcState; 32 #define SPAPR_RTC(obj) \ 33 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC) 34 35 struct SpaprRtcState { 36 /*< private >*/ 37 DeviceState parent_obj; 38 int64_t ns_offset; 39 }; 40 41 typedef struct SpaprDimmState SpaprDimmState; 42 typedef struct SpaprMachineClass SpaprMachineClass; 43 44 #define TYPE_SPAPR_MACHINE "spapr-machine" 45 typedef struct SpaprMachineState SpaprMachineState; 46 #define SPAPR_MACHINE(obj) \ 47 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE) 48 #define SPAPR_MACHINE_GET_CLASS(obj) \ 49 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE) 50 #define SPAPR_MACHINE_CLASS(klass) \ 51 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE) 52 53 typedef enum { 54 SPAPR_RESIZE_HPT_DEFAULT = 0, 55 SPAPR_RESIZE_HPT_DISABLED, 56 SPAPR_RESIZE_HPT_ENABLED, 57 SPAPR_RESIZE_HPT_REQUIRED, 58 } SpaprResizeHpt; 59 60 /** 61 * Capabilities 62 */ 63 64 /* Hardware Transactional Memory */ 65 #define SPAPR_CAP_HTM 0x00 66 /* Vector Scalar Extensions */ 67 #define SPAPR_CAP_VSX 0x01 68 /* Decimal Floating Point */ 69 #define SPAPR_CAP_DFP 0x02 70 /* Cache Flush on Privilege Change */ 71 #define SPAPR_CAP_CFPC 0x03 72 /* Speculation Barrier Bounds Checking */ 73 #define SPAPR_CAP_SBBC 0x04 74 /* Indirect Branch Serialisation */ 75 #define SPAPR_CAP_IBS 0x05 76 /* HPT Maximum Page Size (encoded as a shift) */ 77 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 78 /* Nested KVM-HV */ 79 #define SPAPR_CAP_NESTED_KVM_HV 0x07 80 /* Large Decrementer */ 81 #define SPAPR_CAP_LARGE_DECREMENTER 0x08 82 /* Count Cache Flush Assist HW Instruction */ 83 #define SPAPR_CAP_CCF_ASSIST 0x09 84 /* Implements PAPR FWNMI option */ 85 #define SPAPR_CAP_FWNMI 0x0A 86 /* Num Caps */ 87 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1) 88 89 /* 90 * Capability Values 91 */ 92 /* Bool Caps */ 93 #define SPAPR_CAP_OFF 0x00 94 #define SPAPR_CAP_ON 0x01 95 96 /* Custom Caps */ 97 98 /* Generic */ 99 #define SPAPR_CAP_BROKEN 0x00 100 #define SPAPR_CAP_WORKAROUND 0x01 101 #define SPAPR_CAP_FIXED 0x02 102 /* SPAPR_CAP_IBS (cap-ibs) */ 103 #define SPAPR_CAP_FIXED_IBS 0x02 104 #define SPAPR_CAP_FIXED_CCD 0x03 105 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 106 107 #define FDT_MAX_SIZE 0x100000 108 109 /* 110 * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken 111 * from Linux kernel arch/powerpc/mm/numa.h. It represents the 112 * amount of associativity domains for non-CPU resources. 113 * 114 * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 115 * array for any non-CPU resource. 116 * 117 * VCPU_ASSOC_SIZE represents the size of ibm,associativity array 118 * for CPUs, which has an extra element (vcpu_id) in the end. 119 */ 120 #define MAX_DISTANCE_REF_POINTS 4 121 #define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1) 122 #define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1) 123 124 typedef struct SpaprCapabilities SpaprCapabilities; 125 struct SpaprCapabilities { 126 uint8_t caps[SPAPR_CAP_NUM]; 127 }; 128 129 /** 130 * SpaprMachineClass: 131 */ 132 struct SpaprMachineClass { 133 /*< private >*/ 134 MachineClass parent_class; 135 136 /*< public >*/ 137 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 138 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 139 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 140 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 141 bool pre_2_10_has_unused_icps; 142 bool legacy_irq_allocation; 143 uint32_t nr_xirqs; 144 bool broken_host_serial_model; /* present real host info to the guest */ 145 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 146 bool linux_pci_probe; 147 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 148 hwaddr rma_limit; /* clamp the RMA to this size */ 149 bool pre_5_1_assoc_refpoints; 150 151 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 152 uint64_t *buid, hwaddr *pio, 153 hwaddr *mmio32, hwaddr *mmio64, 154 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 155 hwaddr *nv2atsd, Error **errp); 156 SpaprResizeHpt resize_hpt_default; 157 SpaprCapabilities default_caps; 158 SpaprIrq *irq; 159 }; 160 161 /** 162 * SpaprMachineState: 163 */ 164 struct SpaprMachineState { 165 /*< private >*/ 166 MachineState parent_obj; 167 168 struct SpaprVioBus *vio_bus; 169 QLIST_HEAD(, SpaprPhbState) phbs; 170 struct SpaprNvram *nvram; 171 SpaprRtcState rtc; 172 173 SpaprResizeHpt resize_hpt; 174 void *htab; 175 uint32_t htab_shift; 176 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */ 177 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 178 179 hwaddr rma_size; 180 uint32_t fdt_size; 181 uint32_t fdt_initial_size; 182 void *fdt_blob; 183 long kernel_size; 184 bool kernel_le; 185 uint64_t kernel_addr; 186 uint32_t initrd_base; 187 long initrd_size; 188 uint64_t rtc_offset; /* Now used only during incoming migration */ 189 struct PPCTimebase tb; 190 bool has_graphics; 191 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 192 193 Notifier epow_notifier; 194 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 195 bool use_hotplug_event_source; 196 SpaprEventSource *event_sources; 197 198 /* ibm,client-architecture-support option negotiation */ 199 bool cas_pre_isa3_guest; 200 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 201 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 202 uint32_t max_compat_pvr; 203 204 /* Migration state */ 205 int htab_save_index; 206 bool htab_first_pass; 207 int htab_fd; 208 209 /* Pending DIMM unplug cache. It is populated when a LMB 210 * unplug starts. It can be regenerated if a migration 211 * occurs during the unplug process. */ 212 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 213 214 /* State related to FWNMI option */ 215 216 /* System Reset and Machine Check Notification Routine addresses 217 * registered by "ibm,nmi-register" RTAS call. 218 */ 219 target_ulong fwnmi_system_reset_addr; 220 target_ulong fwnmi_machine_check_addr; 221 222 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 223 * set to -1 if a FWNMI machine check is not in progress, else is set to 224 * the CPU that was delivered the machine check, and is set back to -1 225 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 226 * to synchronize other CPUs. 227 */ 228 int fwnmi_machine_check_interlock; 229 QemuCond fwnmi_machine_check_interlock_cond; 230 231 /*< public >*/ 232 char *kvm_type; 233 char *host_model; 234 char *host_serial; 235 236 int32_t irq_map_nr; 237 unsigned long *irq_map; 238 SpaprIrq *irq; 239 qemu_irq *qirqs; 240 SpaprInterruptController *active_intc; 241 ICSState *ics; 242 SpaprXive *xive; 243 244 bool cmd_line_caps[SPAPR_CAP_NUM]; 245 SpaprCapabilities def, eff, mig; 246 247 unsigned gpu_numa_id; 248 SpaprTpmProxy *tpm_proxy; 249 250 uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE]; 251 252 Error *fwnmi_migration_blocker; 253 }; 254 255 #define H_SUCCESS 0 256 #define H_BUSY 1 /* Hardware busy -- retry later */ 257 #define H_CLOSED 2 /* Resource closed */ 258 #define H_NOT_AVAILABLE 3 259 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 260 #define H_PARTIAL 5 261 #define H_IN_PROGRESS 14 /* Kind of like busy */ 262 #define H_PAGE_REGISTERED 15 263 #define H_PARTIAL_STORE 16 264 #define H_PENDING 17 /* returned from H_POLL_PENDING */ 265 #define H_CONTINUE 18 /* Returned from H_Join on success */ 266 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 267 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 268 is a good time to retry */ 269 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 270 is a good time to retry */ 271 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 272 is a good time to retry */ 273 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 274 is a good time to retry */ 275 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 276 is a good time to retry */ 277 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 278 is a good time to retry */ 279 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 280 #define H_HARDWARE -1 /* Hardware error */ 281 #define H_FUNCTION -2 /* Function not supported */ 282 #define H_PRIVILEGE -3 /* Caller not privileged */ 283 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 284 #define H_BAD_MODE -5 /* Illegal msr value */ 285 #define H_PTEG_FULL -6 /* PTEG is full */ 286 #define H_NOT_FOUND -7 /* PTE was not found" */ 287 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 288 #define H_NO_MEM -9 289 #define H_AUTHORITY -10 290 #define H_PERMISSION -11 291 #define H_DROPPED -12 292 #define H_SOURCE_PARM -13 293 #define H_DEST_PARM -14 294 #define H_REMOTE_PARM -15 295 #define H_RESOURCE -16 296 #define H_ADAPTER_PARM -17 297 #define H_RH_PARM -18 298 #define H_RCQ_PARM -19 299 #define H_SCQ_PARM -20 300 #define H_EQ_PARM -21 301 #define H_RT_PARM -22 302 #define H_ST_PARM -23 303 #define H_SIGT_PARM -24 304 #define H_TOKEN_PARM -25 305 #define H_MLENGTH_PARM -27 306 #define H_MEM_PARM -28 307 #define H_MEM_ACCESS_PARM -29 308 #define H_ATTR_PARM -30 309 #define H_PORT_PARM -31 310 #define H_MCG_PARM -32 311 #define H_VL_PARM -33 312 #define H_TSIZE_PARM -34 313 #define H_TRACE_PARM -35 314 315 #define H_MASK_PARM -37 316 #define H_MCG_FULL -38 317 #define H_ALIAS_EXIST -39 318 #define H_P_COUNTER -40 319 #define H_TABLE_FULL -41 320 #define H_ALT_TABLE -42 321 #define H_MR_CONDITION -43 322 #define H_NOT_ENOUGH_RESOURCES -44 323 #define H_R_STATE -45 324 #define H_RESCINDEND -46 325 #define H_P2 -55 326 #define H_P3 -56 327 #define H_P4 -57 328 #define H_P5 -58 329 #define H_P6 -59 330 #define H_P7 -60 331 #define H_P8 -61 332 #define H_P9 -62 333 #define H_OVERLAP -68 334 #define H_UNSUPPORTED_FLAG -256 335 #define H_MULTI_THREADS_ACTIVE -9005 336 337 338 /* Long Busy is a condition that can be returned by the firmware 339 * when a call cannot be completed now, but the identical call 340 * should be retried later. This prevents calls blocking in the 341 * firmware for long periods of time. Annoyingly the firmware can return 342 * a range of return codes, hinting at how long we should wait before 343 * retrying. If you don't care for the hint, the macro below is a good 344 * way to check for the long_busy return codes 345 */ 346 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 347 && (x <= H_LONG_BUSY_END_RANGE)) 348 349 /* Flags */ 350 #define H_LARGE_PAGE (1ULL<<(63-16)) 351 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 352 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 353 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 354 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 355 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 356 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 357 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 358 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 359 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 360 #define H_ANDCOND (1ULL<<(63-33)) 361 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 362 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 363 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 364 #define H_COPY_PAGE (1ULL<<(63-49)) 365 #define H_N (1ULL<<(63-61)) 366 #define H_PP1 (1ULL<<(63-62)) 367 #define H_PP2 (1ULL<<(63-63)) 368 369 /* Values for 2nd argument to H_SET_MODE */ 370 #define H_SET_MODE_RESOURCE_SET_CIABR 1 371 #define H_SET_MODE_RESOURCE_SET_DAWR 2 372 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 373 #define H_SET_MODE_RESOURCE_LE 4 374 375 /* Flags for H_SET_MODE_RESOURCE_LE */ 376 #define H_SET_MODE_ENDIAN_BIG 0 377 #define H_SET_MODE_ENDIAN_LITTLE 1 378 379 /* VASI States */ 380 #define H_VASI_INVALID 0 381 #define H_VASI_ENABLED 1 382 #define H_VASI_ABORTED 2 383 #define H_VASI_SUSPENDING 3 384 #define H_VASI_SUSPENDED 4 385 #define H_VASI_RESUMED 5 386 #define H_VASI_COMPLETED 6 387 388 /* DABRX flags */ 389 #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 390 #define H_DABRX_KERNEL (1ULL<<(63-62)) 391 #define H_DABRX_USER (1ULL<<(63-63)) 392 393 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 394 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 395 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 396 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 397 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 398 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 399 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 400 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 401 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 402 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 403 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 404 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 405 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 406 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 407 408 /* Each control block has to be on a 4K boundary */ 409 #define H_CB_ALIGNMENT 4096 410 411 /* pSeries hypervisor opcodes */ 412 #define H_REMOVE 0x04 413 #define H_ENTER 0x08 414 #define H_READ 0x0c 415 #define H_CLEAR_MOD 0x10 416 #define H_CLEAR_REF 0x14 417 #define H_PROTECT 0x18 418 #define H_GET_TCE 0x1c 419 #define H_PUT_TCE 0x20 420 #define H_SET_SPRG0 0x24 421 #define H_SET_DABR 0x28 422 #define H_PAGE_INIT 0x2c 423 #define H_SET_ASR 0x30 424 #define H_ASR_ON 0x34 425 #define H_ASR_OFF 0x38 426 #define H_LOGICAL_CI_LOAD 0x3c 427 #define H_LOGICAL_CI_STORE 0x40 428 #define H_LOGICAL_CACHE_LOAD 0x44 429 #define H_LOGICAL_CACHE_STORE 0x48 430 #define H_LOGICAL_ICBI 0x4c 431 #define H_LOGICAL_DCBF 0x50 432 #define H_GET_TERM_CHAR 0x54 433 #define H_PUT_TERM_CHAR 0x58 434 #define H_REAL_TO_LOGICAL 0x5c 435 #define H_HYPERVISOR_DATA 0x60 436 #define H_EOI 0x64 437 #define H_CPPR 0x68 438 #define H_IPI 0x6c 439 #define H_IPOLL 0x70 440 #define H_XIRR 0x74 441 #define H_PERFMON 0x7c 442 #define H_MIGRATE_DMA 0x78 443 #define H_REGISTER_VPA 0xDC 444 #define H_CEDE 0xE0 445 #define H_CONFER 0xE4 446 #define H_PROD 0xE8 447 #define H_GET_PPP 0xEC 448 #define H_SET_PPP 0xF0 449 #define H_PURR 0xF4 450 #define H_PIC 0xF8 451 #define H_REG_CRQ 0xFC 452 #define H_FREE_CRQ 0x100 453 #define H_VIO_SIGNAL 0x104 454 #define H_SEND_CRQ 0x108 455 #define H_COPY_RDMA 0x110 456 #define H_REGISTER_LOGICAL_LAN 0x114 457 #define H_FREE_LOGICAL_LAN 0x118 458 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C 459 #define H_SEND_LOGICAL_LAN 0x120 460 #define H_BULK_REMOVE 0x124 461 #define H_MULTICAST_CTRL 0x130 462 #define H_SET_XDABR 0x134 463 #define H_STUFF_TCE 0x138 464 #define H_PUT_TCE_INDIRECT 0x13C 465 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C 466 #define H_VTERM_PARTNER_INFO 0x150 467 #define H_REGISTER_VTERM 0x154 468 #define H_FREE_VTERM 0x158 469 #define H_RESET_EVENTS 0x15C 470 #define H_ALLOC_RESOURCE 0x160 471 #define H_FREE_RESOURCE 0x164 472 #define H_MODIFY_QP 0x168 473 #define H_QUERY_QP 0x16C 474 #define H_REREGISTER_PMR 0x170 475 #define H_REGISTER_SMR 0x174 476 #define H_QUERY_MR 0x178 477 #define H_QUERY_MW 0x17C 478 #define H_QUERY_HCA 0x180 479 #define H_QUERY_PORT 0x184 480 #define H_MODIFY_PORT 0x188 481 #define H_DEFINE_AQP1 0x18C 482 #define H_GET_TRACE_BUFFER 0x190 483 #define H_DEFINE_AQP0 0x194 484 #define H_RESIZE_MR 0x198 485 #define H_ATTACH_MCQP 0x19C 486 #define H_DETACH_MCQP 0x1A0 487 #define H_CREATE_RPT 0x1A4 488 #define H_REMOVE_RPT 0x1A8 489 #define H_REGISTER_RPAGES 0x1AC 490 #define H_DISABLE_AND_GETC 0x1B0 491 #define H_ERROR_DATA 0x1B4 492 #define H_GET_HCA_INFO 0x1B8 493 #define H_GET_PERF_COUNT 0x1BC 494 #define H_MANAGE_TRACE 0x1C0 495 #define H_GET_CPU_CHARACTERISTICS 0x1C8 496 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 497 #define H_QUERY_INT_STATE 0x1E4 498 #define H_POLL_PENDING 0x1D8 499 #define H_ILLAN_ATTRIBUTES 0x244 500 #define H_MODIFY_HEA_QP 0x250 501 #define H_QUERY_HEA_QP 0x254 502 #define H_QUERY_HEA 0x258 503 #define H_QUERY_HEA_PORT 0x25C 504 #define H_MODIFY_HEA_PORT 0x260 505 #define H_REG_BCMC 0x264 506 #define H_DEREG_BCMC 0x268 507 #define H_REGISTER_HEA_RPAGES 0x26C 508 #define H_DISABLE_AND_GET_HEA 0x270 509 #define H_GET_HEA_INFO 0x274 510 #define H_ALLOC_HEA_RESOURCE 0x278 511 #define H_ADD_CONN 0x284 512 #define H_DEL_CONN 0x288 513 #define H_JOIN 0x298 514 #define H_VASI_STATE 0x2A4 515 #define H_ENABLE_CRQ 0x2B0 516 #define H_GET_EM_PARMS 0x2B8 517 #define H_SET_MPP 0x2D0 518 #define H_GET_MPP 0x2D4 519 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC 520 #define H_XIRR_X 0x2FC 521 #define H_RANDOM 0x300 522 #define H_SET_MODE 0x31C 523 #define H_RESIZE_HPT_PREPARE 0x36C 524 #define H_RESIZE_HPT_COMMIT 0x370 525 #define H_CLEAN_SLB 0x374 526 #define H_INVALIDATE_PID 0x378 527 #define H_REGISTER_PROC_TBL 0x37C 528 #define H_SIGNAL_SYS_RESET 0x380 529 530 #define H_INT_GET_SOURCE_INFO 0x3A8 531 #define H_INT_SET_SOURCE_CONFIG 0x3AC 532 #define H_INT_GET_SOURCE_CONFIG 0x3B0 533 #define H_INT_GET_QUEUE_INFO 0x3B4 534 #define H_INT_SET_QUEUE_CONFIG 0x3B8 535 #define H_INT_GET_QUEUE_CONFIG 0x3BC 536 #define H_INT_SET_OS_REPORTING_LINE 0x3C0 537 #define H_INT_GET_OS_REPORTING_LINE 0x3C4 538 #define H_INT_ESB 0x3C8 539 #define H_INT_SYNC 0x3CC 540 #define H_INT_RESET 0x3D0 541 #define H_SCM_READ_METADATA 0x3E4 542 #define H_SCM_WRITE_METADATA 0x3E8 543 #define H_SCM_BIND_MEM 0x3EC 544 #define H_SCM_UNBIND_MEM 0x3F0 545 #define H_SCM_UNBIND_ALL 0x3FC 546 547 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL 548 549 /* The hcalls above are standardized in PAPR and implemented by pHyp 550 * as well. 551 * 552 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 553 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 554 * for "platform-specific" hcalls. 555 */ 556 #define KVMPPC_HCALL_BASE 0xf000 557 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 558 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 559 /* Client Architecture support */ 560 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 561 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 562 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT 563 564 /* 565 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 566 * Secure VM mode via an Ultravisor / Protected Execution Facility 567 */ 568 #define SVM_HCALL_BASE 0xEF00 569 #define SVM_H_TPM_COMM 0xEF10 570 #define SVM_HCALL_MAX SVM_H_TPM_COMM 571 572 573 typedef struct SpaprDeviceTreeUpdateHeader { 574 uint32_t version_id; 575 } SpaprDeviceTreeUpdateHeader; 576 577 #define hcall_dprintf(fmt, ...) \ 578 do { \ 579 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 580 } while (0) 581 582 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 583 target_ulong opcode, 584 target_ulong *args); 585 586 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 587 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 588 target_ulong *args); 589 590 target_ulong do_client_architecture_support(PowerPCCPU *cpu, 591 SpaprMachineState *spapr, 592 target_ulong addr, 593 target_ulong fdt_bufsize); 594 595 /* Virtual Processor Area structure constants */ 596 #define VPA_MIN_SIZE 640 597 #define VPA_SIZE_OFFSET 0x4 598 #define VPA_SHARED_PROC_OFFSET 0x9 599 #define VPA_SHARED_PROC_VAL 0x2 600 #define VPA_DISPATCH_COUNTER 0x100 601 602 /* ibm,set-eeh-option */ 603 #define RTAS_EEH_DISABLE 0 604 #define RTAS_EEH_ENABLE 1 605 #define RTAS_EEH_THAW_IO 2 606 #define RTAS_EEH_THAW_DMA 3 607 608 /* ibm,get-config-addr-info2 */ 609 #define RTAS_GET_PE_ADDR 0 610 #define RTAS_GET_PE_MODE 1 611 #define RTAS_PE_MODE_NONE 0 612 #define RTAS_PE_MODE_NOT_SHARED 1 613 #define RTAS_PE_MODE_SHARED 2 614 615 /* ibm,read-slot-reset-state2 */ 616 #define RTAS_EEH_PE_STATE_NORMAL 0 617 #define RTAS_EEH_PE_STATE_RESET 1 618 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 619 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4 620 #define RTAS_EEH_PE_STATE_UNAVAIL 5 621 #define RTAS_EEH_NOT_SUPPORT 0 622 #define RTAS_EEH_SUPPORT 1 623 #define RTAS_EEH_PE_UNAVAIL_INFO 1000 624 #define RTAS_EEH_PE_RECOVER_INFO 0 625 626 /* ibm,set-slot-reset */ 627 #define RTAS_SLOT_RESET_DEACTIVATE 0 628 #define RTAS_SLOT_RESET_HOT 1 629 #define RTAS_SLOT_RESET_FUNDAMENTAL 3 630 631 /* ibm,slot-error-detail */ 632 #define RTAS_SLOT_TEMP_ERR_LOG 1 633 #define RTAS_SLOT_PERM_ERR_LOG 2 634 635 /* RTAS return codes */ 636 #define RTAS_OUT_SUCCESS 0 637 #define RTAS_OUT_NO_ERRORS_FOUND 1 638 #define RTAS_OUT_HW_ERROR -1 639 #define RTAS_OUT_BUSY -2 640 #define RTAS_OUT_PARAM_ERROR -3 641 #define RTAS_OUT_NOT_SUPPORTED -3 642 #define RTAS_OUT_NO_SUCH_INDICATOR -3 643 #define RTAS_OUT_NOT_AUTHORIZED -9002 644 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 645 646 /* DDW pagesize mask values from ibm,query-pe-dma-window */ 647 #define RTAS_DDW_PGSIZE_4K 0x01 648 #define RTAS_DDW_PGSIZE_64K 0x02 649 #define RTAS_DDW_PGSIZE_16M 0x04 650 #define RTAS_DDW_PGSIZE_32M 0x08 651 #define RTAS_DDW_PGSIZE_64M 0x10 652 #define RTAS_DDW_PGSIZE_128M 0x20 653 #define RTAS_DDW_PGSIZE_256M 0x40 654 #define RTAS_DDW_PGSIZE_16G 0x80 655 656 /* RTAS tokens */ 657 #define RTAS_TOKEN_BASE 0x2000 658 659 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 660 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 661 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 662 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 663 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 664 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 665 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 666 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 667 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 668 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 669 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 670 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 671 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 672 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 673 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 674 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 675 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 676 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 677 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 678 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 679 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 680 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 681 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 682 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 683 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 684 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 685 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 686 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 687 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 688 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 689 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 690 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 691 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 692 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 693 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 694 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 695 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 696 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 697 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 698 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 699 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 700 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 701 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 702 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 703 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 704 705 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 706 707 /* RTAS ibm,get-system-parameter token values */ 708 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 709 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 710 #define RTAS_SYSPARM_UUID 48 711 712 /* RTAS indicator/sensor types 713 * 714 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 715 * 716 * NOTE: currently only DR-related sensors are implemented here 717 */ 718 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 719 #define RTAS_SENSOR_TYPE_DR 9002 720 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 721 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 722 723 /* Possible values for the platform-processor-diagnostics-run-mode parameter 724 * of the RTAS ibm,get-system-parameter call. 725 */ 726 #define DIAGNOSTICS_RUN_MODE_DISABLED 0 727 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 728 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 729 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 730 731 static inline uint64_t ppc64_phys_to_real(uint64_t addr) 732 { 733 return addr & ~0xF000000000000000ULL; 734 } 735 736 static inline uint32_t rtas_ld(target_ulong phys, int n) 737 { 738 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 739 } 740 741 static inline uint64_t rtas_ldq(target_ulong phys, int n) 742 { 743 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 744 } 745 746 static inline void rtas_st(target_ulong phys, int n, uint32_t val) 747 { 748 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 749 } 750 751 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 752 uint32_t token, 753 uint32_t nargs, target_ulong args, 754 uint32_t nret, target_ulong rets); 755 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 756 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 757 uint32_t token, uint32_t nargs, target_ulong args, 758 uint32_t nret, target_ulong rets); 759 void spapr_dt_rtas_tokens(void *fdt, int rtas); 760 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 761 762 #define SPAPR_TCE_PAGE_SHIFT 12 763 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 764 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 765 766 #define SPAPR_VIO_BASE_LIOBN 0x00000000 767 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 768 #define SPAPR_PCI_LIOBN(phb_index, window_num) \ 769 (0x80000000 | ((phb_index) << 8) | (window_num)) 770 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 771 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 772 773 #define RTAS_SIZE 2048 774 #define RTAS_ERROR_LOG_MAX 2048 775 776 /* Offset from rtas-base where error log is placed */ 777 #define RTAS_ERROR_LOG_OFFSET 0x30 778 779 #define RTAS_EVENT_SCAN_RATE 1 780 781 /* This helper should be used to encode interrupt specifiers when the related 782 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 783 * VIO devices, RTAS event sources and PHBs). 784 */ 785 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 786 { 787 intspec[0] = cpu_to_be32(irq); 788 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 789 } 790 791 typedef struct SpaprTceTable SpaprTceTable; 792 793 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 794 #define SPAPR_TCE_TABLE(obj) \ 795 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE) 796 797 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 798 #define SPAPR_IOMMU_MEMORY_REGION(obj) \ 799 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION) 800 801 struct SpaprTceTable { 802 DeviceState parent; 803 uint32_t liobn; 804 uint32_t nb_table; 805 uint64_t bus_offset; 806 uint32_t page_shift; 807 uint64_t *table; 808 uint32_t mig_nb_table; 809 uint64_t *mig_table; 810 bool bypass; 811 bool need_vfio; 812 bool skipping_replay; 813 int fd; 814 MemoryRegion root; 815 IOMMUMemoryRegion iommu; 816 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 817 QLIST_ENTRY(SpaprTceTable) list; 818 }; 819 820 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 821 822 struct SpaprEventLogEntry { 823 uint32_t summary; 824 uint32_t extended_length; 825 void *extended_log; 826 QTAILQ_ENTRY(SpaprEventLogEntry) next; 827 }; 828 829 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 830 void spapr_events_init(SpaprMachineState *sm); 831 void spapr_dt_events(SpaprMachineState *sm, void *fdt); 832 void close_htab_fd(SpaprMachineState *spapr); 833 void spapr_setup_hpt(SpaprMachineState *spapr); 834 void spapr_free_hpt(SpaprMachineState *spapr); 835 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 836 void spapr_tce_table_enable(SpaprTceTable *tcet, 837 uint32_t page_shift, uint64_t bus_offset, 838 uint32_t nb_table); 839 void spapr_tce_table_disable(SpaprTceTable *tcet); 840 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 841 842 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 843 int spapr_dma_dt(void *fdt, int node_off, const char *propname, 844 uint32_t liobn, uint64_t window, uint32_t size); 845 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 846 SpaprTceTable *tcet); 847 void spapr_pci_switch_vga(bool big_endian); 848 void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 849 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 850 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 851 uint32_t count); 852 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 853 uint32_t count); 854 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 855 uint32_t count, uint32_t index); 856 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 857 uint32_t count, uint32_t index); 858 int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 859 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, 860 Error **errp); 861 void spapr_clear_pending_events(SpaprMachineState *spapr); 862 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 863 int spapr_max_server_number(SpaprMachineState *spapr); 864 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 865 uint64_t pte0, uint64_t pte1); 866 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 867 868 /* DRC callbacks. */ 869 void spapr_core_release(DeviceState *dev); 870 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 871 void *fdt, int *fdt_start_offset, Error **errp); 872 void spapr_lmb_release(DeviceState *dev); 873 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 874 void *fdt, int *fdt_start_offset, Error **errp); 875 void spapr_phb_release(DeviceState *dev); 876 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 877 void *fdt, int *fdt_start_offset, Error **errp); 878 879 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 880 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 881 882 #define TYPE_SPAPR_RNG "spapr-rng" 883 884 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 885 886 /* 887 * This defines the maximum number of DIMM slots we can have for sPAPR 888 * guest. This is not defined by sPAPR but we are defining it to 32 slots 889 * based on default number of slots provided by PowerPC kernel. 890 */ 891 #define SPAPR_MAX_RAM_SLOTS 32 892 893 /* 1GB alignment for hotplug memory region */ 894 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 895 896 /* 897 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 898 * property under ibm,dynamic-reconfiguration-memory node. 899 */ 900 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 901 902 /* 903 * Defines for flag value in ibm,dynamic-memory property under 904 * ibm,dynamic-reconfiguration-memory node. 905 */ 906 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 907 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 908 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080 909 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 910 911 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 912 913 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 914 915 int spapr_get_vcpu_id(PowerPCCPU *cpu); 916 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 917 PowerPCCPU *spapr_find_cpu(int vcpu_id); 918 919 int spapr_caps_pre_load(void *opaque); 920 int spapr_caps_pre_save(void *opaque); 921 922 /* 923 * Handling of optional capabilities 924 */ 925 extern const VMStateDescription vmstate_spapr_cap_htm; 926 extern const VMStateDescription vmstate_spapr_cap_vsx; 927 extern const VMStateDescription vmstate_spapr_cap_dfp; 928 extern const VMStateDescription vmstate_spapr_cap_cfpc; 929 extern const VMStateDescription vmstate_spapr_cap_sbbc; 930 extern const VMStateDescription vmstate_spapr_cap_ibs; 931 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 932 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 933 extern const VMStateDescription vmstate_spapr_cap_large_decr; 934 extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 935 extern const VMStateDescription vmstate_spapr_cap_fwnmi; 936 937 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 938 { 939 return spapr->eff.caps[cap]; 940 } 941 942 void spapr_caps_init(SpaprMachineState *spapr); 943 void spapr_caps_apply(SpaprMachineState *spapr); 944 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 945 void spapr_caps_add_properties(SpaprMachineClass *smc); 946 int spapr_caps_post_migration(SpaprMachineState *spapr); 947 948 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 949 Error **errp); 950 /* 951 * XIVE definitions 952 */ 953 #define SPAPR_OV5_XIVE_LEGACY 0x0 954 #define SPAPR_OV5_XIVE_EXPLOIT 0x40 955 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 956 957 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 958 hwaddr spapr_get_rtas_addr(void); 959 #endif /* HW_SPAPR_H */ 960