1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Authors: Stafford Horne <shorne@gmail.com> 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "hw/irq.h" 14 #include "hw/qdev-properties.h" 15 #include "hw/sysbus.h" 16 #include "migration/vmstate.h" 17 #include "exec/memory.h" 18 #include "qom/object.h" 19 20 #define TYPE_OR1K_OMPIC "or1k-ompic" 21 typedef struct OR1KOMPICState OR1KOMPICState; 22 #define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC) 23 24 #define OMPIC_CTRL_IRQ_ACK (1 << 31) 25 #define OMPIC_CTRL_IRQ_GEN (1 << 30) 26 #define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff) 27 28 #define OMPIC_REG(addr) (((addr) >> 2) & 0x1) 29 #define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f) 30 #define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f) 31 32 #define OMPIC_STATUS_IRQ_PENDING (1 << 30) 33 #define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16) 34 #define OMPIC_STATUS_DATA(data) ((data) & 0xffff) 35 36 #define OMPIC_CONTROL 0 37 #define OMPIC_STATUS 1 38 39 #define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */ 40 #define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */ 41 42 typedef struct OR1KOMPICCPUState OR1KOMPICCPUState; 43 44 struct OR1KOMPICCPUState { 45 qemu_irq irq; 46 uint32_t status; 47 uint32_t control; 48 }; 49 50 struct OR1KOMPICState { 51 SysBusDevice parent_obj; 52 MemoryRegion mr; 53 54 OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS]; 55 56 uint32_t num_cpus; 57 }; 58 59 static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size) 60 { 61 OR1KOMPICState *s = opaque; 62 int src_cpu = OMPIC_SRC_CPU(addr); 63 64 /* We can only write to control control, write control + update status */ 65 if (OMPIC_REG(addr) == OMPIC_CONTROL) { 66 return s->cpus[src_cpu].control; 67 } else { 68 return s->cpus[src_cpu].status; 69 } 70 71 } 72 73 static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) 74 { 75 OR1KOMPICState *s = opaque; 76 /* We can only write to control control, write control + update status */ 77 if (OMPIC_REG(addr) == OMPIC_CONTROL) { 78 int src_cpu = OMPIC_SRC_CPU(addr); 79 80 s->cpus[src_cpu].control = data; 81 82 if (data & OMPIC_CTRL_IRQ_GEN) { 83 int dst_cpu = OMPIC_CTRL_DST(data); 84 85 s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING | 86 OMPIC_STATUS_SRC(src_cpu) | 87 OMPIC_STATUS_DATA(data); 88 89 qemu_irq_raise(s->cpus[dst_cpu].irq); 90 } 91 if (data & OMPIC_CTRL_IRQ_ACK) { 92 s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING; 93 qemu_irq_lower(s->cpus[src_cpu].irq); 94 } 95 } 96 } 97 98 static const MemoryRegionOps ompic_ops = { 99 .read = ompic_read, 100 .write = ompic_write, 101 .endianness = DEVICE_NATIVE_ENDIAN, 102 .impl = { 103 .max_access_size = 8, 104 }, 105 }; 106 107 static void or1k_ompic_init(Object *obj) 108 { 109 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 110 OR1KOMPICState *s = OR1K_OMPIC(obj); 111 112 memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s, 113 "or1k-ompic", OMPIC_ADDRSPACE_SZ); 114 sysbus_init_mmio(sbd, &s->mr); 115 } 116 117 static void or1k_ompic_realize(DeviceState *dev, Error **errp) 118 { 119 OR1KOMPICState *s = OR1K_OMPIC(dev); 120 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 121 int i; 122 123 if (s->num_cpus > OMPIC_MAX_CPUS) { 124 error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus); 125 return; 126 } 127 /* Init IRQ sources for all CPUs */ 128 for (i = 0; i < s->num_cpus; i++) { 129 sysbus_init_irq(sbd, &s->cpus[i].irq); 130 } 131 } 132 133 static Property or1k_ompic_properties[] = { 134 DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1), 135 DEFINE_PROP_END_OF_LIST(), 136 }; 137 138 static const VMStateDescription vmstate_or1k_ompic_cpu = { 139 .name = "or1k_ompic_cpu", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .fields = (VMStateField[]) { 143 VMSTATE_UINT32(status, OR1KOMPICCPUState), 144 VMSTATE_UINT32(control, OR1KOMPICCPUState), 145 VMSTATE_END_OF_LIST() 146 } 147 }; 148 149 static const VMStateDescription vmstate_or1k_ompic = { 150 .name = TYPE_OR1K_OMPIC, 151 .version_id = 1, 152 .minimum_version_id = 1, 153 .fields = (VMStateField[]) { 154 VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1, 155 vmstate_or1k_ompic_cpu, OR1KOMPICCPUState), 156 VMSTATE_UINT32(num_cpus, OR1KOMPICState), 157 VMSTATE_END_OF_LIST() 158 } 159 }; 160 161 static void or1k_ompic_class_init(ObjectClass *klass, void *data) 162 { 163 DeviceClass *dc = DEVICE_CLASS(klass); 164 165 device_class_set_props(dc, or1k_ompic_properties); 166 dc->realize = or1k_ompic_realize; 167 dc->vmsd = &vmstate_or1k_ompic; 168 } 169 170 static const TypeInfo or1k_ompic_info = { 171 .name = TYPE_OR1K_OMPIC, 172 .parent = TYPE_SYS_BUS_DEVICE, 173 .instance_size = sizeof(OR1KOMPICState), 174 .instance_init = or1k_ompic_init, 175 .class_init = or1k_ompic_class_init, 176 }; 177 178 static void or1k_ompic_register_types(void) 179 { 180 type_register_static(&or1k_ompic_info); 181 } 182 183 type_init(or1k_ompic_register_types) 184