xref: /qemu/target/sh4/cpu-qom.h (revision db1015e92e04835c9eb50c29625fe566d1202dbd)
1 /*
2  * QEMU SuperH CPU
3  *
4  * Copyright (c) 2012 SUSE LINUX Products GmbH
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 #ifndef QEMU_SUPERH_CPU_QOM_H
21 #define QEMU_SUPERH_CPU_QOM_H
22 
23 #include "hw/core/cpu.h"
24 #include "qom/object.h"
25 
26 #define TYPE_SUPERH_CPU "superh-cpu"
27 
28 #define TYPE_SH7750R_CPU SUPERH_CPU_TYPE_NAME("sh7750r")
29 #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
30 #define TYPE_SH7785_CPU  SUPERH_CPU_TYPE_NAME("sh7785")
31 
32 typedef struct SuperHCPU SuperHCPU;
33 typedef struct SuperHCPUClass SuperHCPUClass;
34 #define SUPERH_CPU_CLASS(klass) \
35     OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
36 #define SUPERH_CPU(obj) \
37     OBJECT_CHECK(SuperHCPU, (obj), TYPE_SUPERH_CPU)
38 #define SUPERH_CPU_GET_CLASS(obj) \
39     OBJECT_GET_CLASS(SuperHCPUClass, (obj), TYPE_SUPERH_CPU)
40 
41 /**
42  * SuperHCPUClass:
43  * @parent_realize: The parent class' realize handler.
44  * @parent_reset: The parent class' reset handler.
45  * @pvr: Processor Version Register
46  * @prr: Processor Revision Register
47  * @cvr: Cache Version Register
48  *
49  * A SuperH CPU model.
50  */
51 struct SuperHCPUClass {
52     /*< private >*/
53     CPUClass parent_class;
54     /*< public >*/
55 
56     DeviceRealize parent_realize;
57     DeviceReset parent_reset;
58 
59     uint32_t pvr;
60     uint32_t prr;
61     uint32_t cvr;
62 };
63 
64 
65 #endif
66