1 /* 2 * ARM V2M MPS2 board emulation. 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * We model the following FPGA images: 17 * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 18 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 19 * 20 * Links to the TRM for the board itself and to the various Application 21 * Notes which document the FPGA images can be found here: 22 * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/cutils.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "hw/arm/boot.h" 31 #include "hw/arm/armv7m.h" 32 #include "hw/or-irq.h" 33 #include "hw/boards.h" 34 #include "exec/address-spaces.h" 35 #include "sysemu/sysemu.h" 36 #include "hw/misc/unimp.h" 37 #include "hw/char/cmsdk-apb-uart.h" 38 #include "hw/timer/cmsdk-apb-timer.h" 39 #include "hw/timer/cmsdk-apb-dualtimer.h" 40 #include "hw/misc/mps2-scc.h" 41 #include "hw/misc/mps2-fpgaio.h" 42 #include "hw/ssi/pl022.h" 43 #include "hw/i2c/arm_sbcon_i2c.h" 44 #include "hw/net/lan9118.h" 45 #include "net/net.h" 46 #include "hw/watchdog/cmsdk-apb-watchdog.h" 47 #include "qom/object.h" 48 49 typedef enum MPS2FPGAType { 50 FPGA_AN385, 51 FPGA_AN511, 52 } MPS2FPGAType; 53 54 struct MPS2MachineClass { 55 MachineClass parent; 56 MPS2FPGAType fpga_type; 57 uint32_t scc_id; 58 }; 59 typedef struct MPS2MachineClass MPS2MachineClass; 60 61 struct MPS2MachineState { 62 MachineState parent; 63 64 ARMv7MState armv7m; 65 MemoryRegion ssram1; 66 MemoryRegion ssram1_m; 67 MemoryRegion ssram23; 68 MemoryRegion ssram23_m; 69 MemoryRegion blockram; 70 MemoryRegion blockram_m1; 71 MemoryRegion blockram_m2; 72 MemoryRegion blockram_m3; 73 MemoryRegion sram; 74 /* FPGA APB subsystem */ 75 MPS2SCC scc; 76 MPS2FPGAIO fpgaio; 77 /* CMSDK APB subsystem */ 78 CMSDKAPBDualTimer dualtimer; 79 CMSDKAPBWatchdog watchdog; 80 }; 81 typedef struct MPS2MachineState MPS2MachineState; 82 83 #define TYPE_MPS2_MACHINE "mps2" 84 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") 85 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") 86 87 #define MPS2_MACHINE(obj) \ 88 OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE) 89 #define MPS2_MACHINE_GET_CLASS(obj) \ 90 OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE) 91 #define MPS2_MACHINE_CLASS(klass) \ 92 OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE) 93 94 /* Main SYSCLK frequency in Hz */ 95 #define SYSCLK_FRQ 25000000 96 97 /* Initialize the auxiliary RAM region @mr and map it into 98 * the memory map at @base. 99 */ 100 static void make_ram(MemoryRegion *mr, const char *name, 101 hwaddr base, hwaddr size) 102 { 103 memory_region_init_ram(mr, NULL, name, size, &error_fatal); 104 memory_region_add_subregion(get_system_memory(), base, mr); 105 } 106 107 /* Create an alias of an entire original MemoryRegion @orig 108 * located at @base in the memory map. 109 */ 110 static void make_ram_alias(MemoryRegion *mr, const char *name, 111 MemoryRegion *orig, hwaddr base) 112 { 113 memory_region_init_alias(mr, NULL, name, orig, 0, 114 memory_region_size(orig)); 115 memory_region_add_subregion(get_system_memory(), base, mr); 116 } 117 118 static void mps2_common_init(MachineState *machine) 119 { 120 MPS2MachineState *mms = MPS2_MACHINE(machine); 121 MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); 122 MemoryRegion *system_memory = get_system_memory(); 123 MachineClass *mc = MACHINE_GET_CLASS(machine); 124 DeviceState *armv7m, *sccdev; 125 int i; 126 127 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 128 error_report("This board can only be used with CPU %s", 129 mc->default_cpu_type); 130 exit(1); 131 } 132 133 if (machine->ram_size != mc->default_ram_size) { 134 char *sz = size_to_str(mc->default_ram_size); 135 error_report("Invalid RAM size, should be %s", sz); 136 g_free(sz); 137 exit(EXIT_FAILURE); 138 } 139 140 /* The FPGA images have an odd combination of different RAMs, 141 * because in hardware they are different implementations and 142 * connected to different buses, giving varying performance/size 143 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 144 * call the 16MB our "system memory", as it's the largest lump. 145 * 146 * Common to both boards: 147 * 0x21000000..0x21ffffff : PSRAM (16MB) 148 * AN385 only: 149 * 0x00000000 .. 0x003fffff : ZBT SSRAM1 150 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 151 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 152 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 153 * 0x01000000 .. 0x01003fff : block RAM (16K) 154 * 0x01004000 .. 0x01007fff : mirror of above 155 * 0x01008000 .. 0x0100bfff : mirror of above 156 * 0x0100c000 .. 0x0100ffff : mirror of above 157 * AN511 only: 158 * 0x00000000 .. 0x0003ffff : FPGA block RAM 159 * 0x00400000 .. 0x007fffff : ZBT SSRAM1 160 * 0x20000000 .. 0x2001ffff : SRAM 161 * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 162 * 163 * The AN385 has a feature where the lowest 16K can be mapped 164 * either to the bottom of the ZBT SSRAM1 or to the block RAM. 165 * This is of no use for QEMU so we don't implement it (as if 166 * zbt_boot_ctrl is always zero). 167 */ 168 memory_region_add_subregion(system_memory, 0x21000000, machine->ram); 169 170 switch (mmc->fpga_type) { 171 case FPGA_AN385: 172 make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); 173 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); 174 make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); 175 make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", 176 &mms->ssram23, 0x20400000); 177 make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); 178 make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", 179 &mms->blockram, 0x01004000); 180 make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", 181 &mms->blockram, 0x01008000); 182 make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", 183 &mms->blockram, 0x0100c000); 184 break; 185 case FPGA_AN511: 186 make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); 187 make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); 188 make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); 189 make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); 190 break; 191 default: 192 g_assert_not_reached(); 193 } 194 195 object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); 196 armv7m = DEVICE(&mms->armv7m); 197 switch (mmc->fpga_type) { 198 case FPGA_AN385: 199 qdev_prop_set_uint32(armv7m, "num-irq", 32); 200 break; 201 case FPGA_AN511: 202 qdev_prop_set_uint32(armv7m, "num-irq", 64); 203 break; 204 default: 205 g_assert_not_reached(); 206 } 207 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); 208 qdev_prop_set_bit(armv7m, "enable-bitband", true); 209 object_property_set_link(OBJECT(&mms->armv7m), "memory", 210 OBJECT(system_memory), &error_abort); 211 sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); 212 213 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); 214 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); 215 create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); 216 create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); 217 create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); 218 create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); 219 /* These three ranges all cover multiple devices; we may implement 220 * some of them below (in which case the real device takes precedence 221 * over the unimplemented-region mapping). 222 */ 223 create_unimplemented_device("CMSDK APB peripheral region @0x40000000", 224 0x40000000, 0x00010000); 225 create_unimplemented_device("CMSDK AHB peripheral region @0x40010000", 226 0x40010000, 0x00010000); 227 create_unimplemented_device("Extra peripheral region @0x40020000", 228 0x40020000, 0x00010000); 229 230 create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); 231 create_unimplemented_device("VGA", 0x41000000, 0x0200000); 232 233 switch (mmc->fpga_type) { 234 case FPGA_AN385: 235 { 236 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. 237 * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. 238 */ 239 Object *orgate; 240 DeviceState *orgate_dev; 241 242 orgate = object_new(TYPE_OR_IRQ); 243 object_property_set_int(orgate, "num-lines", 6, &error_fatal); 244 qdev_realize(DEVICE(orgate), NULL, &error_fatal); 245 orgate_dev = DEVICE(orgate); 246 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); 247 248 for (i = 0; i < 5; i++) { 249 static const hwaddr uartbase[] = {0x40004000, 0x40005000, 250 0x40006000, 0x40007000, 251 0x40009000}; 252 /* RX irq number; TX irq is always one greater */ 253 static const int uartirq[] = {0, 2, 4, 18, 20}; 254 qemu_irq txovrint = NULL, rxovrint = NULL; 255 256 if (i < 3) { 257 txovrint = qdev_get_gpio_in(orgate_dev, i * 2); 258 rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); 259 } 260 261 cmsdk_apb_uart_create(uartbase[i], 262 qdev_get_gpio_in(armv7m, uartirq[i] + 1), 263 qdev_get_gpio_in(armv7m, uartirq[i]), 264 txovrint, rxovrint, 265 NULL, 266 serial_hd(i), SYSCLK_FRQ); 267 } 268 break; 269 } 270 case FPGA_AN511: 271 { 272 /* The overflow IRQs for all UARTs are ORed together. 273 * Tx and Rx IRQs for each UART are ORed together. 274 */ 275 Object *orgate; 276 DeviceState *orgate_dev; 277 278 orgate = object_new(TYPE_OR_IRQ); 279 object_property_set_int(orgate, "num-lines", 10, &error_fatal); 280 qdev_realize(DEVICE(orgate), NULL, &error_fatal); 281 orgate_dev = DEVICE(orgate); 282 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); 283 284 for (i = 0; i < 5; i++) { 285 /* system irq numbers for the combined tx/rx for each UART */ 286 static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; 287 static const hwaddr uartbase[] = {0x40004000, 0x40005000, 288 0x4002c000, 0x4002d000, 289 0x4002e000}; 290 Object *txrx_orgate; 291 DeviceState *txrx_orgate_dev; 292 293 txrx_orgate = object_new(TYPE_OR_IRQ); 294 object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal); 295 qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal); 296 txrx_orgate_dev = DEVICE(txrx_orgate); 297 qdev_connect_gpio_out(txrx_orgate_dev, 0, 298 qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); 299 cmsdk_apb_uart_create(uartbase[i], 300 qdev_get_gpio_in(txrx_orgate_dev, 0), 301 qdev_get_gpio_in(txrx_orgate_dev, 1), 302 qdev_get_gpio_in(orgate_dev, i * 2), 303 qdev_get_gpio_in(orgate_dev, i * 2 + 1), 304 NULL, 305 serial_hd(i), SYSCLK_FRQ); 306 } 307 break; 308 } 309 default: 310 g_assert_not_reached(); 311 } 312 for (i = 0; i < 4; i++) { 313 static const hwaddr gpiobase[] = {0x40010000, 0x40011000, 314 0x40012000, 0x40013000}; 315 create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); 316 } 317 318 /* CMSDK APB subsystem */ 319 cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); 320 cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); 321 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, 322 TYPE_CMSDK_APB_DUALTIMER); 323 qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); 324 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); 325 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, 326 qdev_get_gpio_in(armv7m, 10)); 327 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); 328 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, 329 TYPE_CMSDK_APB_WATCHDOG); 330 qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); 331 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); 332 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, 333 qdev_get_gpio_in_named(armv7m, "NMI", 0)); 334 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000); 335 336 /* FPGA APB subsystem */ 337 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); 338 sccdev = DEVICE(&mms->scc); 339 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 340 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 341 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 342 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); 343 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); 344 object_initialize_child(OBJECT(mms), "fpgaio", 345 &mms->fpgaio, TYPE_MPS2_FPGAIO); 346 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); 347 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); 348 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); 349 sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */ 350 qdev_get_gpio_in(armv7m, 22)); 351 for (i = 0; i < 2; i++) { 352 static const int spi_irqno[] = {11, 24}; 353 static const hwaddr spibase[] = {0x40020000, /* APB */ 354 0x40021000, /* LCD */ 355 0x40026000, /* Shield0 */ 356 0x40027000}; /* Shield1 */ 357 DeviceState *orgate_dev; 358 Object *orgate; 359 int j; 360 361 orgate = object_new(TYPE_OR_IRQ); 362 object_property_set_int(orgate, "num-lines", 2, &error_fatal); 363 orgate_dev = DEVICE(orgate); 364 qdev_realize(orgate_dev, NULL, &error_fatal); 365 qdev_connect_gpio_out(orgate_dev, 0, 366 qdev_get_gpio_in(armv7m, spi_irqno[i])); 367 for (j = 0; j < 2; j++) { 368 sysbus_create_simple(TYPE_PL022, spibase[2 * i + j], 369 qdev_get_gpio_in(orgate_dev, j)); 370 } 371 } 372 for (i = 0; i < 4; i++) { 373 static const hwaddr i2cbase[] = {0x40022000, /* Touch */ 374 0x40023000, /* Audio */ 375 0x40029000, /* Shield0 */ 376 0x4002a000}; /* Shield1 */ 377 sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); 378 } 379 create_unimplemented_device("i2s", 0x40024000, 0x400); 380 381 /* In hardware this is a LAN9220; the LAN9118 is software compatible 382 * except that it doesn't support the checksum-offload feature. 383 */ 384 lan9118_init(&nd_table[0], 0x40200000, 385 qdev_get_gpio_in(armv7m, 386 mmc->fpga_type == FPGA_AN385 ? 13 : 47)); 387 388 system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; 389 390 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 391 0x400000); 392 } 393 394 static void mps2_class_init(ObjectClass *oc, void *data) 395 { 396 MachineClass *mc = MACHINE_CLASS(oc); 397 398 mc->init = mps2_common_init; 399 mc->max_cpus = 1; 400 mc->default_ram_size = 16 * MiB; 401 mc->default_ram_id = "mps.ram"; 402 } 403 404 static void mps2_an385_class_init(ObjectClass *oc, void *data) 405 { 406 MachineClass *mc = MACHINE_CLASS(oc); 407 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 408 409 mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; 410 mmc->fpga_type = FPGA_AN385; 411 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 412 mmc->scc_id = 0x41043850; 413 } 414 415 static void mps2_an511_class_init(ObjectClass *oc, void *data) 416 { 417 MachineClass *mc = MACHINE_CLASS(oc); 418 MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); 419 420 mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; 421 mmc->fpga_type = FPGA_AN511; 422 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); 423 mmc->scc_id = 0x41045110; 424 } 425 426 static const TypeInfo mps2_info = { 427 .name = TYPE_MPS2_MACHINE, 428 .parent = TYPE_MACHINE, 429 .abstract = true, 430 .instance_size = sizeof(MPS2MachineState), 431 .class_size = sizeof(MPS2MachineClass), 432 .class_init = mps2_class_init, 433 }; 434 435 static const TypeInfo mps2_an385_info = { 436 .name = TYPE_MPS2_AN385_MACHINE, 437 .parent = TYPE_MPS2_MACHINE, 438 .class_init = mps2_an385_class_init, 439 }; 440 441 static const TypeInfo mps2_an511_info = { 442 .name = TYPE_MPS2_AN511_MACHINE, 443 .parent = TYPE_MPS2_MACHINE, 444 .class_init = mps2_an511_class_init, 445 }; 446 447 static void mps2_machine_init(void) 448 { 449 type_register_static(&mps2_info); 450 type_register_static(&mps2_an385_info); 451 type_register_static(&mps2_an511_info); 452 } 453 454 type_init(mps2_machine_init); 455