1 /* 2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images 3 * 4 * Copyright (c) 2017 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger 13 * FPGA but is otherwise the same as the 2). Since the CPU itself 14 * and most of the devices are in the FPGA, the details of the board 15 * as seen by the guest depend significantly on the FPGA image. 16 * This source file covers the following FPGA images, for TrustZone cores: 17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 19 * 20 * Links to the TRM for the board itself and to the various Application 21 * Notes which document the FPGA images can be found here: 22 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 23 * 24 * Board TRM: 25 * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf 26 * Application Note AN505: 27 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html 28 * Application Note AN521: 29 * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html 30 * 31 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide 32 * (ARM ECM0601256) for the details of some of the device layout: 33 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 34 * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines 35 * most of the device layout: 36 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 37 * 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/units.h" 42 #include "qemu/cutils.h" 43 #include "qapi/error.h" 44 #include "qemu/error-report.h" 45 #include "hw/arm/boot.h" 46 #include "hw/arm/armv7m.h" 47 #include "hw/or-irq.h" 48 #include "hw/boards.h" 49 #include "exec/address-spaces.h" 50 #include "sysemu/sysemu.h" 51 #include "hw/misc/unimp.h" 52 #include "hw/char/cmsdk-apb-uart.h" 53 #include "hw/timer/cmsdk-apb-timer.h" 54 #include "hw/misc/mps2-scc.h" 55 #include "hw/misc/mps2-fpgaio.h" 56 #include "hw/misc/tz-mpc.h" 57 #include "hw/misc/tz-msc.h" 58 #include "hw/arm/armsse.h" 59 #include "hw/dma/pl080.h" 60 #include "hw/ssi/pl022.h" 61 #include "hw/i2c/arm_sbcon_i2c.h" 62 #include "hw/net/lan9118.h" 63 #include "net/net.h" 64 #include "hw/core/split-irq.h" 65 #include "qom/object.h" 66 67 #define MPS2TZ_NUMIRQ 92 68 69 typedef enum MPS2TZFPGAType { 70 FPGA_AN505, 71 FPGA_AN521, 72 } MPS2TZFPGAType; 73 74 struct MPS2TZMachineClass { 75 MachineClass parent; 76 MPS2TZFPGAType fpga_type; 77 uint32_t scc_id; 78 const char *armsse_type; 79 }; 80 typedef struct MPS2TZMachineClass MPS2TZMachineClass; 81 82 struct MPS2TZMachineState { 83 MachineState parent; 84 85 ARMSSE iotkit; 86 MemoryRegion ssram[3]; 87 MemoryRegion ssram1_m; 88 MPS2SCC scc; 89 MPS2FPGAIO fpgaio; 90 TZPPC ppc[5]; 91 TZMPC ssram_mpc[3]; 92 PL022State spi[5]; 93 ArmSbconI2CState i2c[4]; 94 UnimplementedDeviceState i2s_audio; 95 UnimplementedDeviceState gpio[4]; 96 UnimplementedDeviceState gfx; 97 PL080State dma[4]; 98 TZMSC msc[4]; 99 CMSDKAPBUART uart[5]; 100 SplitIRQ sec_resp_splitter; 101 qemu_or_irq uart_irq_orgate; 102 DeviceState *lan9118; 103 SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; 104 }; 105 typedef struct MPS2TZMachineState MPS2TZMachineState; 106 107 #define TYPE_MPS2TZ_MACHINE "mps2tz" 108 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") 109 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") 110 111 #define MPS2TZ_MACHINE(obj) \ 112 OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) 113 #define MPS2TZ_MACHINE_GET_CLASS(obj) \ 114 OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) 115 #define MPS2TZ_MACHINE_CLASS(klass) \ 116 OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) 117 118 /* Main SYSCLK frequency in Hz */ 119 #define SYSCLK_FRQ 20000000 120 121 /* Create an alias of an entire original MemoryRegion @orig 122 * located at @base in the memory map. 123 */ 124 static void make_ram_alias(MemoryRegion *mr, const char *name, 125 MemoryRegion *orig, hwaddr base) 126 { 127 memory_region_init_alias(mr, NULL, name, orig, 0, 128 memory_region_size(orig)); 129 memory_region_add_subregion(get_system_memory(), base, mr); 130 } 131 132 static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) 133 { 134 /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ 135 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 136 137 assert(irqno < MPS2TZ_NUMIRQ); 138 139 switch (mmc->fpga_type) { 140 case FPGA_AN505: 141 return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); 142 case FPGA_AN521: 143 return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); 144 default: 145 g_assert_not_reached(); 146 } 147 } 148 149 /* Most of the devices in the AN505 FPGA image sit behind 150 * Peripheral Protection Controllers. These data structures 151 * define the layout of which devices sit behind which PPCs. 152 * The devfn for each port is a function which creates, configures 153 * and initializes the device, returning the MemoryRegion which 154 * needs to be plugged into the downstream end of the PPC port. 155 */ 156 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, 157 const char *name, hwaddr size); 158 159 typedef struct PPCPortInfo { 160 const char *name; 161 MakeDevFn *devfn; 162 void *opaque; 163 hwaddr addr; 164 hwaddr size; 165 } PPCPortInfo; 166 167 typedef struct PPCInfo { 168 const char *name; 169 PPCPortInfo ports[TZ_NUM_PORTS]; 170 } PPCInfo; 171 172 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, 173 void *opaque, 174 const char *name, hwaddr size) 175 { 176 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, 177 * and return a pointer to its MemoryRegion. 178 */ 179 UnimplementedDeviceState *uds = opaque; 180 181 object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 182 qdev_prop_set_string(DEVICE(uds), "name", name); 183 qdev_prop_set_uint64(DEVICE(uds), "size", size); 184 sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 185 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 186 } 187 188 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, 189 const char *name, hwaddr size) 190 { 191 CMSDKAPBUART *uart = opaque; 192 int i = uart - &mms->uart[0]; 193 int rxirqno = i * 2; 194 int txirqno = i * 2 + 1; 195 int combirqno = i + 10; 196 SysBusDevice *s; 197 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 198 199 object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 200 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 201 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 202 sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 203 s = SYS_BUS_DEVICE(uart); 204 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); 205 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); 206 sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); 207 sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); 208 sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); 209 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); 210 } 211 212 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, 213 const char *name, hwaddr size) 214 { 215 MPS2SCC *scc = opaque; 216 DeviceState *sccdev; 217 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 218 219 object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 220 sccdev = DEVICE(scc); 221 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 222 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 223 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 224 sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 225 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 226 } 227 228 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, 229 const char *name, hwaddr size) 230 { 231 MPS2FPGAIO *fpgaio = opaque; 232 233 object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 234 sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 235 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 236 } 237 238 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, 239 const char *name, hwaddr size) 240 { 241 SysBusDevice *s; 242 NICInfo *nd = &nd_table[0]; 243 244 /* In hardware this is a LAN9220; the LAN9118 is software compatible 245 * except that it doesn't support the checksum-offload feature. 246 */ 247 qemu_check_nic_model(nd, "lan9118"); 248 mms->lan9118 = qdev_new(TYPE_LAN9118); 249 qdev_set_nic_properties(mms->lan9118, nd); 250 251 s = SYS_BUS_DEVICE(mms->lan9118); 252 sysbus_realize_and_unref(s, &error_fatal); 253 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); 254 return sysbus_mmio_get_region(s, 0); 255 } 256 257 static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, 258 const char *name, hwaddr size) 259 { 260 TZMPC *mpc = opaque; 261 int i = mpc - &mms->ssram_mpc[0]; 262 MemoryRegion *ssram = &mms->ssram[i]; 263 MemoryRegion *upstream; 264 char *mpcname = g_strdup_printf("%s-mpc", name); 265 static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; 266 static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; 267 268 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 269 270 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 271 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), 272 &error_fatal); 273 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 274 /* Map the upstream end of the MPC into system memory */ 275 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 276 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); 277 /* and connect its interrupt to the IoTKit */ 278 qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, 279 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 280 "mpcexp_status", i)); 281 282 /* The first SSRAM is a special case as it has an alias; accesses to 283 * the alias region at 0x00400000 must also go to the MPC upstream. 284 */ 285 if (i == 0) { 286 make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); 287 } 288 289 g_free(mpcname); 290 /* Return the register interface MR for our caller to map behind the PPC */ 291 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); 292 } 293 294 static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, 295 const char *name, hwaddr size) 296 { 297 PL080State *dma = opaque; 298 int i = dma - &mms->dma[0]; 299 SysBusDevice *s; 300 char *mscname = g_strdup_printf("%s-msc", name); 301 TZMSC *msc = &mms->msc[i]; 302 DeviceState *iotkitdev = DEVICE(&mms->iotkit); 303 MemoryRegion *msc_upstream; 304 MemoryRegion *msc_downstream; 305 306 /* 307 * Each DMA device is a PL081 whose transaction master interface 308 * is guarded by a Master Security Controller. The downstream end of 309 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 310 * DMA devices can see all devices and memory that the CPU does. 311 */ 312 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 313 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 314 object_property_set_link(OBJECT(msc), "downstream", 315 OBJECT(msc_downstream), &error_fatal); 316 object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 317 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 318 319 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 320 qdev_get_gpio_in_named(iotkitdev, 321 "mscexp_status", i)); 322 qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, 323 qdev_get_gpio_in_named(DEVICE(msc), 324 "irq_clear", 0)); 325 qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, 326 qdev_get_gpio_in_named(DEVICE(msc), 327 "cfg_nonsec", 0)); 328 qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), 329 ARRAY_SIZE(mms->ppc) + i, 330 qdev_get_gpio_in_named(DEVICE(msc), 331 "cfg_sec_resp", 0)); 332 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 333 334 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 335 object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 336 &error_fatal); 337 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 338 339 s = SYS_BUS_DEVICE(dma); 340 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ 341 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); 342 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); 343 sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); 344 345 g_free(mscname); 346 return sysbus_mmio_get_region(s, 0); 347 } 348 349 static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, 350 const char *name, hwaddr size) 351 { 352 /* 353 * The AN505 has five PL022 SPI controllers. 354 * One of these should have the LCD controller behind it; the others 355 * are connected only to the FPGA's "general purpose SPI connector" 356 * or "shield" expansion connectors. 357 * Note that if we do implement devices behind SPI, the chip select 358 * lines are set via the "MISC" register in the MPS2 FPGAIO device. 359 */ 360 PL022State *spi = opaque; 361 int i = spi - &mms->spi[0]; 362 SysBusDevice *s; 363 364 object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 365 sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 366 s = SYS_BUS_DEVICE(spi); 367 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); 368 return sysbus_mmio_get_region(s, 0); 369 } 370 371 static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, 372 const char *name, hwaddr size) 373 { 374 ArmSbconI2CState *i2c = opaque; 375 SysBusDevice *s; 376 377 object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); 378 s = SYS_BUS_DEVICE(i2c); 379 sysbus_realize(s, &error_fatal); 380 return sysbus_mmio_get_region(s, 0); 381 } 382 383 static void mps2tz_common_init(MachineState *machine) 384 { 385 MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); 386 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 387 MachineClass *mc = MACHINE_GET_CLASS(machine); 388 MemoryRegion *system_memory = get_system_memory(); 389 DeviceState *iotkitdev; 390 DeviceState *dev_splitter; 391 int i; 392 393 if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { 394 error_report("This board can only be used with CPU %s", 395 mc->default_cpu_type); 396 exit(1); 397 } 398 399 if (machine->ram_size != mc->default_ram_size) { 400 char *sz = size_to_str(mc->default_ram_size); 401 error_report("Invalid RAM size, should be %s", sz); 402 g_free(sz); 403 exit(EXIT_FAILURE); 404 } 405 406 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 407 mmc->armsse_type); 408 iotkitdev = DEVICE(&mms->iotkit); 409 object_property_set_link(OBJECT(&mms->iotkit), "memory", 410 OBJECT(system_memory), &error_abort); 411 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); 412 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 413 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 414 415 /* 416 * The AN521 needs us to create splitters to feed the IRQ inputs 417 * for each CPU in the SSE-200 from each device in the board. 418 */ 419 if (mmc->fpga_type == FPGA_AN521) { 420 for (i = 0; i < MPS2TZ_NUMIRQ; i++) { 421 char *name = g_strdup_printf("mps2-irq-splitter%d", i); 422 SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; 423 424 object_initialize_child_with_props(OBJECT(machine), name, 425 splitter, sizeof(*splitter), 426 TYPE_SPLIT_IRQ, &error_fatal, 427 NULL); 428 g_free(name); 429 430 object_property_set_int(OBJECT(splitter), "num-lines", 2, 431 &error_fatal); 432 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 433 qdev_connect_gpio_out(DEVICE(splitter), 0, 434 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 435 "EXP_IRQ", i)); 436 qdev_connect_gpio_out(DEVICE(splitter), 1, 437 qdev_get_gpio_in_named(DEVICE(&mms->iotkit), 438 "EXP_CPU1_IRQ", i)); 439 } 440 } 441 442 /* The sec_resp_cfg output from the IoTKit must be split into multiple 443 * lines, one for each of the PPCs we create here, plus one per MSC. 444 */ 445 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 446 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 447 object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 448 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 449 &error_fatal); 450 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 451 dev_splitter = DEVICE(&mms->sec_resp_splitter); 452 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, 453 qdev_get_gpio_in(dev_splitter, 0)); 454 455 /* The IoTKit sets up much of the memory layout, including 456 * the aliases between secure and non-secure regions in the 457 * address space. The FPGA itself contains: 458 * 459 * 0x00000000..0x003fffff SSRAM1 460 * 0x00400000..0x007fffff alias of SSRAM1 461 * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 462 * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices 463 * 0x80000000..0x80ffffff 16MB PSRAM 464 */ 465 466 /* The FPGA images have an odd combination of different RAMs, 467 * because in hardware they are different implementations and 468 * connected to different buses, giving varying performance/size 469 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 470 * call the 16MB our "system memory", as it's the largest lump. 471 */ 472 memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 473 474 /* The overflow IRQs for all UARTs are ORed together. 475 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. 476 * Create the OR gate for this. 477 */ 478 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 479 &mms->uart_irq_orgate, TYPE_OR_IRQ); 480 object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, 481 &error_fatal); 482 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 483 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, 484 get_sse_irq_in(mms, 15)); 485 486 /* Most of the devices in the FPGA are behind Peripheral Protection 487 * Controllers. The required order for initializing things is: 488 * + initialize the PPC 489 * + initialize, configure and realize downstream devices 490 * + connect downstream device MemoryRegions to the PPC 491 * + realize the PPC 492 * + map the PPC's MemoryRegions to the places in the address map 493 * where the downstream devices should appear 494 * + wire up the PPC's control lines to the IoTKit object 495 */ 496 497 const PPCInfo ppcs[] = { { 498 .name = "apb_ppcexp0", 499 .ports = { 500 { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, 501 { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, 502 { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, 503 }, 504 }, { 505 .name = "apb_ppcexp1", 506 .ports = { 507 { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, 508 { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, 509 { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, 510 { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, 511 { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, 512 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, 513 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, 514 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, 515 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, 516 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, 517 { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, 518 { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, 519 { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, 520 { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, 521 }, 522 }, { 523 .name = "apb_ppcexp2", 524 .ports = { 525 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, 526 { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 527 0x40301000, 0x1000 }, 528 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, 529 }, 530 }, { 531 .name = "ahb_ppcexp0", 532 .ports = { 533 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, 534 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, 535 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, 536 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, 537 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, 538 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, 539 }, 540 }, { 541 .name = "ahb_ppcexp1", 542 .ports = { 543 { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, 544 { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, 545 { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, 546 { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, 547 }, 548 }, 549 }; 550 551 for (i = 0; i < ARRAY_SIZE(ppcs); i++) { 552 const PPCInfo *ppcinfo = &ppcs[i]; 553 TZPPC *ppc = &mms->ppc[i]; 554 DeviceState *ppcdev; 555 int port; 556 char *gpioname; 557 558 object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 559 TYPE_TZ_PPC); 560 ppcdev = DEVICE(ppc); 561 562 for (port = 0; port < TZ_NUM_PORTS; port++) { 563 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 564 MemoryRegion *mr; 565 char *portname; 566 567 if (!pinfo->devfn) { 568 continue; 569 } 570 571 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 572 portname = g_strdup_printf("port[%d]", port); 573 object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 574 &error_fatal); 575 g_free(portname); 576 } 577 578 sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 579 580 for (port = 0; port < TZ_NUM_PORTS; port++) { 581 const PPCPortInfo *pinfo = &ppcinfo->ports[port]; 582 583 if (!pinfo->devfn) { 584 continue; 585 } 586 sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); 587 588 gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); 589 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 590 qdev_get_gpio_in_named(ppcdev, 591 "cfg_nonsec", 592 port)); 593 g_free(gpioname); 594 gpioname = g_strdup_printf("%s_ap", ppcinfo->name); 595 qdev_connect_gpio_out_named(iotkitdev, gpioname, port, 596 qdev_get_gpio_in_named(ppcdev, 597 "cfg_ap", port)); 598 g_free(gpioname); 599 } 600 601 gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); 602 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 603 qdev_get_gpio_in_named(ppcdev, 604 "irq_enable", 0)); 605 g_free(gpioname); 606 gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); 607 qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, 608 qdev_get_gpio_in_named(ppcdev, 609 "irq_clear", 0)); 610 g_free(gpioname); 611 gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); 612 qdev_connect_gpio_out_named(ppcdev, "irq", 0, 613 qdev_get_gpio_in_named(iotkitdev, 614 gpioname, 0)); 615 g_free(gpioname); 616 617 qdev_connect_gpio_out(dev_splitter, i, 618 qdev_get_gpio_in_named(ppcdev, 619 "cfg_sec_resp", 0)); 620 } 621 622 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); 623 624 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); 625 } 626 627 static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, 628 int *iregion, bool *exempt, bool *ns, bool *nsc) 629 { 630 /* 631 * The MPS2 TZ FPGA images have IDAUs in them which are connected to 632 * the Master Security Controllers. Thes have the same logic as 633 * is used by the IoTKit for the IDAU connected to the CPU, except 634 * that MSCs don't care about the NSC attribute. 635 */ 636 int region = extract32(address, 28, 4); 637 638 *ns = !(region & 1); 639 *nsc = false; 640 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 641 *exempt = (address & 0xeff00000) == 0xe0000000; 642 *iregion = region; 643 } 644 645 static void mps2tz_class_init(ObjectClass *oc, void *data) 646 { 647 MachineClass *mc = MACHINE_CLASS(oc); 648 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); 649 650 mc->init = mps2tz_common_init; 651 iic->check = mps2_tz_idau_check; 652 mc->default_ram_size = 16 * MiB; 653 mc->default_ram_id = "mps.ram"; 654 } 655 656 static void mps2tz_an505_class_init(ObjectClass *oc, void *data) 657 { 658 MachineClass *mc = MACHINE_CLASS(oc); 659 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 660 661 mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; 662 mc->default_cpus = 1; 663 mc->min_cpus = mc->default_cpus; 664 mc->max_cpus = mc->default_cpus; 665 mmc->fpga_type = FPGA_AN505; 666 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 667 mmc->scc_id = 0x41045050; 668 mmc->armsse_type = TYPE_IOTKIT; 669 } 670 671 static void mps2tz_an521_class_init(ObjectClass *oc, void *data) 672 { 673 MachineClass *mc = MACHINE_CLASS(oc); 674 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); 675 676 mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; 677 mc->default_cpus = 2; 678 mc->min_cpus = mc->default_cpus; 679 mc->max_cpus = mc->default_cpus; 680 mmc->fpga_type = FPGA_AN521; 681 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); 682 mmc->scc_id = 0x41045210; 683 mmc->armsse_type = TYPE_SSE200; 684 } 685 686 static const TypeInfo mps2tz_info = { 687 .name = TYPE_MPS2TZ_MACHINE, 688 .parent = TYPE_MACHINE, 689 .abstract = true, 690 .instance_size = sizeof(MPS2TZMachineState), 691 .class_size = sizeof(MPS2TZMachineClass), 692 .class_init = mps2tz_class_init, 693 .interfaces = (InterfaceInfo[]) { 694 { TYPE_IDAU_INTERFACE }, 695 { } 696 }, 697 }; 698 699 static const TypeInfo mps2tz_an505_info = { 700 .name = TYPE_MPS2TZ_AN505_MACHINE, 701 .parent = TYPE_MPS2TZ_MACHINE, 702 .class_init = mps2tz_an505_class_init, 703 }; 704 705 static const TypeInfo mps2tz_an521_info = { 706 .name = TYPE_MPS2TZ_AN521_MACHINE, 707 .parent = TYPE_MPS2TZ_MACHINE, 708 .class_init = mps2tz_an521_class_init, 709 }; 710 711 static void mps2tz_machine_init(void) 712 { 713 type_register_static(&mps2tz_info); 714 type_register_static(&mps2tz_an505_info); 715 type_register_static(&mps2tz_an521_info); 716 } 717 718 type_init(mps2tz_machine_init); 719