1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 #include "qom/object.h" 31 32 //#define DEBUG_SONIC 33 34 #define SONIC_PROM_SIZE 0x1000 35 36 #ifdef DEBUG_SONIC 37 #define DPRINTF(fmt, ...) \ 38 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 39 static const char* reg_names[] = { 40 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 41 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 42 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 43 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 44 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 45 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 46 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 47 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 48 #else 49 #define DPRINTF(fmt, ...) do {} while (0) 50 #endif 51 52 #define SONIC_ERROR(fmt, ...) \ 53 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 54 55 #define SONIC_CR 0x00 56 #define SONIC_DCR 0x01 57 #define SONIC_RCR 0x02 58 #define SONIC_TCR 0x03 59 #define SONIC_IMR 0x04 60 #define SONIC_ISR 0x05 61 #define SONIC_UTDA 0x06 62 #define SONIC_CTDA 0x07 63 #define SONIC_TPS 0x08 64 #define SONIC_TFC 0x09 65 #define SONIC_TSA0 0x0a 66 #define SONIC_TSA1 0x0b 67 #define SONIC_TFS 0x0c 68 #define SONIC_URDA 0x0d 69 #define SONIC_CRDA 0x0e 70 #define SONIC_CRBA0 0x0f 71 #define SONIC_CRBA1 0x10 72 #define SONIC_RBWC0 0x11 73 #define SONIC_RBWC1 0x12 74 #define SONIC_EOBC 0x13 75 #define SONIC_URRA 0x14 76 #define SONIC_RSA 0x15 77 #define SONIC_REA 0x16 78 #define SONIC_RRP 0x17 79 #define SONIC_RWP 0x18 80 #define SONIC_TRBA0 0x19 81 #define SONIC_TRBA1 0x1a 82 #define SONIC_LLFA 0x1f 83 #define SONIC_TTDA 0x20 84 #define SONIC_CEP 0x21 85 #define SONIC_CAP2 0x22 86 #define SONIC_CAP1 0x23 87 #define SONIC_CAP0 0x24 88 #define SONIC_CE 0x25 89 #define SONIC_CDP 0x26 90 #define SONIC_CDC 0x27 91 #define SONIC_SR 0x28 92 #define SONIC_WT0 0x29 93 #define SONIC_WT1 0x2a 94 #define SONIC_RSC 0x2b 95 #define SONIC_CRCT 0x2c 96 #define SONIC_FAET 0x2d 97 #define SONIC_MPT 0x2e 98 #define SONIC_MDT 0x2f 99 #define SONIC_DCR2 0x3f 100 101 #define SONIC_CR_HTX 0x0001 102 #define SONIC_CR_TXP 0x0002 103 #define SONIC_CR_RXDIS 0x0004 104 #define SONIC_CR_RXEN 0x0008 105 #define SONIC_CR_STP 0x0010 106 #define SONIC_CR_ST 0x0020 107 #define SONIC_CR_RST 0x0080 108 #define SONIC_CR_RRRA 0x0100 109 #define SONIC_CR_LCAM 0x0200 110 #define SONIC_CR_MASK 0x03bf 111 112 #define SONIC_DCR_DW 0x0020 113 #define SONIC_DCR_LBR 0x2000 114 #define SONIC_DCR_EXBUS 0x8000 115 116 #define SONIC_RCR_PRX 0x0001 117 #define SONIC_RCR_LBK 0x0002 118 #define SONIC_RCR_FAER 0x0004 119 #define SONIC_RCR_CRCR 0x0008 120 #define SONIC_RCR_CRS 0x0020 121 #define SONIC_RCR_LPKT 0x0040 122 #define SONIC_RCR_BC 0x0080 123 #define SONIC_RCR_MC 0x0100 124 #define SONIC_RCR_LB0 0x0200 125 #define SONIC_RCR_LB1 0x0400 126 #define SONIC_RCR_AMC 0x0800 127 #define SONIC_RCR_PRO 0x1000 128 #define SONIC_RCR_BRD 0x2000 129 #define SONIC_RCR_RNT 0x4000 130 131 #define SONIC_TCR_PTX 0x0001 132 #define SONIC_TCR_BCM 0x0002 133 #define SONIC_TCR_FU 0x0004 134 #define SONIC_TCR_EXC 0x0040 135 #define SONIC_TCR_CRSL 0x0080 136 #define SONIC_TCR_NCRS 0x0100 137 #define SONIC_TCR_EXD 0x0400 138 #define SONIC_TCR_CRCI 0x2000 139 #define SONIC_TCR_PINT 0x8000 140 141 #define SONIC_ISR_RBAE 0x0010 142 #define SONIC_ISR_RBE 0x0020 143 #define SONIC_ISR_RDE 0x0040 144 #define SONIC_ISR_TC 0x0080 145 #define SONIC_ISR_TXDN 0x0200 146 #define SONIC_ISR_PKTRX 0x0400 147 #define SONIC_ISR_PINT 0x0800 148 #define SONIC_ISR_LCD 0x1000 149 150 #define SONIC_DESC_EOL 0x0001 151 #define SONIC_DESC_ADDR 0xFFFE 152 153 #define TYPE_DP8393X "dp8393x" 154 typedef struct dp8393xState dp8393xState; 155 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 156 157 struct dp8393xState { 158 SysBusDevice parent_obj; 159 160 /* Hardware */ 161 uint8_t it_shift; 162 bool big_endian; 163 bool last_rba_is_full; 164 qemu_irq irq; 165 #ifdef DEBUG_SONIC 166 int irq_level; 167 #endif 168 QEMUTimer *watchdog; 169 int64_t wt_last_update; 170 NICConf conf; 171 NICState *nic; 172 MemoryRegion mmio; 173 MemoryRegion prom; 174 175 /* Registers */ 176 uint8_t cam[16][6]; 177 uint16_t regs[0x40]; 178 179 /* Temporaries */ 180 uint8_t tx_buffer[0x10000]; 181 uint16_t data[12]; 182 int loopback_packet; 183 184 /* Memory access */ 185 MemoryRegion *dma_mr; 186 AddressSpace as; 187 }; 188 189 /* Accessor functions for values which are formed by 190 * concatenating two 16 bit device registers. By putting these 191 * in their own functions with a uint32_t return type we avoid the 192 * pitfall of implicit sign extension where ((x << 16) | y) is a 193 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 194 */ 195 static uint32_t dp8393x_cdp(dp8393xState *s) 196 { 197 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 198 } 199 200 static uint32_t dp8393x_crba(dp8393xState *s) 201 { 202 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 203 } 204 205 static uint32_t dp8393x_crda(dp8393xState *s) 206 { 207 return (s->regs[SONIC_URDA] << 16) | 208 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 209 } 210 211 static uint32_t dp8393x_rbwc(dp8393xState *s) 212 { 213 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 214 } 215 216 static uint32_t dp8393x_rrp(dp8393xState *s) 217 { 218 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 219 } 220 221 static uint32_t dp8393x_tsa(dp8393xState *s) 222 { 223 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 224 } 225 226 static uint32_t dp8393x_ttda(dp8393xState *s) 227 { 228 return (s->regs[SONIC_UTDA] << 16) | 229 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 230 } 231 232 static uint32_t dp8393x_wt(dp8393xState *s) 233 { 234 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 235 } 236 237 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 238 { 239 uint16_t val; 240 241 if (s->big_endian) { 242 val = be16_to_cpu(s->data[offset * width + width - 1]); 243 } else { 244 val = le16_to_cpu(s->data[offset * width]); 245 } 246 return val; 247 } 248 249 static void dp8393x_put(dp8393xState *s, int width, int offset, 250 uint16_t val) 251 { 252 if (s->big_endian) { 253 if (width == 2) { 254 s->data[offset * 2] = 0; 255 s->data[offset * 2 + 1] = cpu_to_be16(val); 256 } else { 257 s->data[offset] = cpu_to_be16(val); 258 } 259 } else { 260 if (width == 2) { 261 s->data[offset * 2] = cpu_to_le16(val); 262 s->data[offset * 2 + 1] = 0; 263 } else { 264 s->data[offset] = cpu_to_le16(val); 265 } 266 } 267 } 268 269 static void dp8393x_update_irq(dp8393xState *s) 270 { 271 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 272 273 #ifdef DEBUG_SONIC 274 if (level != s->irq_level) { 275 s->irq_level = level; 276 if (level) { 277 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 278 } else { 279 DPRINTF("lower irq\n"); 280 } 281 } 282 #endif 283 284 qemu_set_irq(s->irq, level); 285 } 286 287 static void dp8393x_do_load_cam(dp8393xState *s) 288 { 289 int width, size; 290 uint16_t index = 0; 291 292 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 293 size = sizeof(uint16_t) * 4 * width; 294 295 while (s->regs[SONIC_CDC] & 0x1f) { 296 /* Fill current entry */ 297 address_space_read(&s->as, dp8393x_cdp(s), 298 MEMTXATTRS_UNSPECIFIED, s->data, size); 299 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 300 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 301 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 302 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 303 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 304 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 305 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 306 s->cam[index][0], s->cam[index][1], s->cam[index][2], 307 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 308 /* Move to next entry */ 309 s->regs[SONIC_CDC]--; 310 s->regs[SONIC_CDP] += size; 311 index++; 312 } 313 314 /* Read CAM enable */ 315 address_space_read(&s->as, dp8393x_cdp(s), 316 MEMTXATTRS_UNSPECIFIED, s->data, size); 317 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 318 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 319 320 /* Done */ 321 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 322 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 323 dp8393x_update_irq(s); 324 } 325 326 static void dp8393x_do_read_rra(dp8393xState *s) 327 { 328 int width, size; 329 330 /* Read memory */ 331 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 332 size = sizeof(uint16_t) * 4 * width; 333 address_space_read(&s->as, dp8393x_rrp(s), 334 MEMTXATTRS_UNSPECIFIED, s->data, size); 335 336 /* Update SONIC registers */ 337 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 338 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 339 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 340 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 341 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 342 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 343 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 344 345 /* Go to next entry */ 346 s->regs[SONIC_RRP] += size; 347 348 /* Handle wrap */ 349 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 350 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 351 } 352 353 /* Warn the host if CRBA now has the last available resource */ 354 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 355 { 356 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 357 dp8393x_update_irq(s); 358 } 359 360 /* Allow packet reception */ 361 s->last_rba_is_full = false; 362 } 363 364 static void dp8393x_do_software_reset(dp8393xState *s) 365 { 366 timer_del(s->watchdog); 367 368 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 369 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 370 } 371 372 static void dp8393x_set_next_tick(dp8393xState *s) 373 { 374 uint32_t ticks; 375 int64_t delay; 376 377 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 378 timer_del(s->watchdog); 379 return; 380 } 381 382 ticks = dp8393x_wt(s); 383 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 384 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 385 timer_mod(s->watchdog, s->wt_last_update + delay); 386 } 387 388 static void dp8393x_update_wt_regs(dp8393xState *s) 389 { 390 int64_t elapsed; 391 uint32_t val; 392 393 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 394 timer_del(s->watchdog); 395 return; 396 } 397 398 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 399 val = dp8393x_wt(s); 400 val -= elapsed / 5000000; 401 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 402 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 403 dp8393x_set_next_tick(s); 404 405 } 406 407 static void dp8393x_do_start_timer(dp8393xState *s) 408 { 409 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 410 dp8393x_set_next_tick(s); 411 } 412 413 static void dp8393x_do_stop_timer(dp8393xState *s) 414 { 415 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 416 dp8393x_update_wt_regs(s); 417 } 418 419 static bool dp8393x_can_receive(NetClientState *nc); 420 421 static void dp8393x_do_receiver_enable(dp8393xState *s) 422 { 423 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 424 if (dp8393x_can_receive(s->nic->ncs)) { 425 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 426 } 427 } 428 429 static void dp8393x_do_receiver_disable(dp8393xState *s) 430 { 431 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 432 } 433 434 static void dp8393x_do_transmit_packets(dp8393xState *s) 435 { 436 NetClientState *nc = qemu_get_queue(s->nic); 437 int width, size; 438 int tx_len, len; 439 uint16_t i; 440 441 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 442 443 while (1) { 444 /* Read memory */ 445 size = sizeof(uint16_t) * 6 * width; 446 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 447 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 448 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 449 MEMTXATTRS_UNSPECIFIED, s->data, size); 450 tx_len = 0; 451 452 /* Update registers */ 453 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 454 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 455 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 456 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 457 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 458 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 459 460 /* Handle programmable interrupt */ 461 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 462 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 463 } else { 464 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 465 } 466 467 for (i = 0; i < s->regs[SONIC_TFC]; ) { 468 /* Append fragment */ 469 len = s->regs[SONIC_TFS]; 470 if (tx_len + len > sizeof(s->tx_buffer)) { 471 len = sizeof(s->tx_buffer) - tx_len; 472 } 473 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 474 &s->tx_buffer[tx_len], len); 475 tx_len += len; 476 477 i++; 478 if (i != s->regs[SONIC_TFC]) { 479 /* Read next fragment details */ 480 size = sizeof(uint16_t) * 3 * width; 481 address_space_read(&s->as, 482 dp8393x_ttda(s) 483 + sizeof(uint16_t) * width * (4 + 3 * i), 484 MEMTXATTRS_UNSPECIFIED, s->data, 485 size); 486 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 487 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 488 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 489 } 490 } 491 492 /* Handle Ethernet checksum */ 493 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 494 /* Don't append FCS there, to look like slirp packets 495 * which don't have one */ 496 } else { 497 /* Remove existing FCS */ 498 tx_len -= 4; 499 } 500 501 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 502 /* Loopback */ 503 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 504 if (nc->info->can_receive(nc)) { 505 s->loopback_packet = 1; 506 nc->info->receive(nc, s->tx_buffer, tx_len); 507 } 508 } else { 509 /* Transmit packet */ 510 qemu_send_packet(nc, s->tx_buffer, tx_len); 511 } 512 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 513 514 /* Write status */ 515 dp8393x_put(s, width, 0, 516 s->regs[SONIC_TCR] & 0x0fff); /* status */ 517 size = sizeof(uint16_t) * width; 518 address_space_write(&s->as, dp8393x_ttda(s), 519 MEMTXATTRS_UNSPECIFIED, s->data, size); 520 521 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 522 /* Read footer of packet */ 523 size = sizeof(uint16_t) * width; 524 address_space_read(&s->as, 525 dp8393x_ttda(s) 526 + sizeof(uint16_t) * width 527 * (4 + 3 * s->regs[SONIC_TFC]), 528 MEMTXATTRS_UNSPECIFIED, s->data, 529 size); 530 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0); 531 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) { 532 /* EOL detected */ 533 break; 534 } 535 } 536 } 537 538 /* Done */ 539 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 540 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 541 dp8393x_update_irq(s); 542 } 543 544 static void dp8393x_do_halt_transmission(dp8393xState *s) 545 { 546 /* Nothing to do */ 547 } 548 549 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 550 { 551 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 552 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 553 return; 554 } 555 556 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 557 558 if (command & SONIC_CR_HTX) 559 dp8393x_do_halt_transmission(s); 560 if (command & SONIC_CR_TXP) 561 dp8393x_do_transmit_packets(s); 562 if (command & SONIC_CR_RXDIS) 563 dp8393x_do_receiver_disable(s); 564 if (command & SONIC_CR_RXEN) 565 dp8393x_do_receiver_enable(s); 566 if (command & SONIC_CR_STP) 567 dp8393x_do_stop_timer(s); 568 if (command & SONIC_CR_ST) 569 dp8393x_do_start_timer(s); 570 if (command & SONIC_CR_RST) 571 dp8393x_do_software_reset(s); 572 if (command & SONIC_CR_RRRA) { 573 dp8393x_do_read_rra(s); 574 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 575 } 576 if (command & SONIC_CR_LCAM) 577 dp8393x_do_load_cam(s); 578 } 579 580 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 581 { 582 dp8393xState *s = opaque; 583 int reg = addr >> s->it_shift; 584 uint16_t val = 0; 585 586 switch (reg) { 587 /* Update data before reading it */ 588 case SONIC_WT0: 589 case SONIC_WT1: 590 dp8393x_update_wt_regs(s); 591 val = s->regs[reg]; 592 break; 593 /* Accept read to some registers only when in reset mode */ 594 case SONIC_CAP2: 595 case SONIC_CAP1: 596 case SONIC_CAP0: 597 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 598 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 599 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 600 } 601 break; 602 /* All other registers have no special contrainst */ 603 default: 604 val = s->regs[reg]; 605 } 606 607 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 608 609 return s->big_endian ? val << 16 : val; 610 } 611 612 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 613 unsigned int size) 614 { 615 dp8393xState *s = opaque; 616 int reg = addr >> s->it_shift; 617 uint32_t val = s->big_endian ? data >> 16 : data; 618 619 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); 620 621 switch (reg) { 622 /* Command register */ 623 case SONIC_CR: 624 dp8393x_do_command(s, val); 625 break; 626 /* Prevent write to read-only registers */ 627 case SONIC_CAP2: 628 case SONIC_CAP1: 629 case SONIC_CAP0: 630 case SONIC_SR: 631 case SONIC_MDT: 632 DPRINTF("writing to reg %d invalid\n", reg); 633 break; 634 /* Accept write to some registers only when in reset mode */ 635 case SONIC_DCR: 636 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 637 s->regs[reg] = val & 0xbfff; 638 } else { 639 DPRINTF("writing to DCR invalid\n"); 640 } 641 break; 642 case SONIC_DCR2: 643 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 644 s->regs[reg] = val & 0xf017; 645 } else { 646 DPRINTF("writing to DCR2 invalid\n"); 647 } 648 break; 649 /* 12 lower bytes are Read Only */ 650 case SONIC_TCR: 651 s->regs[reg] = val & 0xf000; 652 break; 653 /* 9 lower bytes are Read Only */ 654 case SONIC_RCR: 655 s->regs[reg] = val & 0xffe0; 656 break; 657 /* Ignore most significant bit */ 658 case SONIC_IMR: 659 s->regs[reg] = val & 0x7fff; 660 dp8393x_update_irq(s); 661 break; 662 /* Clear bits by writing 1 to them */ 663 case SONIC_ISR: 664 val &= s->regs[reg]; 665 s->regs[reg] &= ~val; 666 if (val & SONIC_ISR_RBE) { 667 dp8393x_do_read_rra(s); 668 } 669 dp8393x_update_irq(s); 670 break; 671 /* The guest is required to store aligned pointers here */ 672 case SONIC_RSA: 673 case SONIC_REA: 674 case SONIC_RRP: 675 case SONIC_RWP: 676 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 677 s->regs[reg] = val & 0xfffc; 678 } else { 679 s->regs[reg] = val & 0xfffe; 680 } 681 break; 682 /* Invert written value for some registers */ 683 case SONIC_CRCT: 684 case SONIC_FAET: 685 case SONIC_MPT: 686 s->regs[reg] = val ^ 0xffff; 687 break; 688 /* All other registers have no special contrainst */ 689 default: 690 s->regs[reg] = val; 691 } 692 693 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 694 dp8393x_set_next_tick(s); 695 } 696 } 697 698 static const MemoryRegionOps dp8393x_ops = { 699 .read = dp8393x_read, 700 .write = dp8393x_write, 701 .impl.min_access_size = 4, 702 .impl.max_access_size = 4, 703 .endianness = DEVICE_NATIVE_ENDIAN, 704 }; 705 706 static void dp8393x_watchdog(void *opaque) 707 { 708 dp8393xState *s = opaque; 709 710 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 711 return; 712 } 713 714 s->regs[SONIC_WT1] = 0xffff; 715 s->regs[SONIC_WT0] = 0xffff; 716 dp8393x_set_next_tick(s); 717 718 /* Signal underflow */ 719 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 720 dp8393x_update_irq(s); 721 } 722 723 static bool dp8393x_can_receive(NetClientState *nc) 724 { 725 dp8393xState *s = qemu_get_nic_opaque(nc); 726 727 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN); 728 } 729 730 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 731 int size) 732 { 733 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 734 int i; 735 736 /* Check promiscuous mode */ 737 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 738 return 0; 739 } 740 741 /* Check multicast packets */ 742 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 743 return SONIC_RCR_MC; 744 } 745 746 /* Check broadcast */ 747 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 748 return SONIC_RCR_BC; 749 } 750 751 /* Check CAM */ 752 for (i = 0; i < 16; i++) { 753 if (s->regs[SONIC_CE] & (1 << i)) { 754 /* Entry enabled */ 755 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 756 return 0; 757 } 758 } 759 } 760 761 return -1; 762 } 763 764 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 765 size_t pkt_size) 766 { 767 dp8393xState *s = qemu_get_nic_opaque(nc); 768 int packet_type; 769 uint32_t available, address; 770 int width, rx_len, padded_len; 771 uint32_t checksum; 772 int size; 773 774 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 775 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 776 777 if (s->last_rba_is_full) { 778 return pkt_size; 779 } 780 781 rx_len = pkt_size + sizeof(checksum); 782 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 783 width = 2; 784 padded_len = ((rx_len - 1) | 3) + 1; 785 } else { 786 width = 1; 787 padded_len = ((rx_len - 1) | 1) + 1; 788 } 789 790 if (padded_len > dp8393x_rbwc(s) * 2) { 791 DPRINTF("oversize packet, pkt_size is %d\n", pkt_size); 792 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE; 793 dp8393x_update_irq(s); 794 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 795 goto done; 796 } 797 798 packet_type = dp8393x_receive_filter(s, buf, pkt_size); 799 if (packet_type < 0) { 800 DPRINTF("packet not for netcard\n"); 801 return -1; 802 } 803 804 /* Check for EOL */ 805 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 806 /* Are we still in resource exhaustion? */ 807 size = sizeof(uint16_t) * 1 * width; 808 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 809 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 810 s->data, size); 811 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 812 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 813 /* Still EOL ; stop reception */ 814 return -1; 815 } 816 /* Link has been updated by host */ 817 818 /* Clear in_use */ 819 size = sizeof(uint16_t) * width; 820 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 821 dp8393x_put(s, width, 0, 0); 822 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 823 (uint8_t *)s->data, size, 1); 824 825 /* Move to next descriptor */ 826 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 827 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 828 } 829 830 /* Save current position */ 831 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 832 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 833 834 /* Calculate the ethernet checksum */ 835 checksum = cpu_to_le32(crc32(0, buf, pkt_size)); 836 837 /* Put packet into RBA */ 838 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 839 address = dp8393x_crba(s); 840 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 841 buf, pkt_size); 842 address += pkt_size; 843 844 /* Put frame checksum into RBA */ 845 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 846 &checksum, sizeof(checksum)); 847 address += sizeof(checksum); 848 849 /* Pad short packets to keep pointers aligned */ 850 if (rx_len < padded_len) { 851 size = padded_len - rx_len; 852 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 853 (uint8_t *)"\xFF\xFF\xFF", size, 1); 854 address += size; 855 } 856 857 s->regs[SONIC_CRBA1] = address >> 16; 858 s->regs[SONIC_CRBA0] = address & 0xffff; 859 available = dp8393x_rbwc(s); 860 available -= padded_len >> 1; 861 s->regs[SONIC_RBWC1] = available >> 16; 862 s->regs[SONIC_RBWC0] = available & 0xffff; 863 864 /* Update status */ 865 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 866 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 867 } 868 s->regs[SONIC_RCR] |= packet_type; 869 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 870 if (s->loopback_packet) { 871 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 872 s->loopback_packet = 0; 873 } 874 875 /* Write status to memory */ 876 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 877 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 878 dp8393x_put(s, width, 1, rx_len); /* byte count */ 879 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 880 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 881 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 882 size = sizeof(uint16_t) * 5 * width; 883 address_space_write(&s->as, dp8393x_crda(s), 884 MEMTXATTRS_UNSPECIFIED, 885 s->data, size); 886 887 /* Check link field */ 888 size = sizeof(uint16_t) * width; 889 address_space_read(&s->as, 890 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 891 MEMTXATTRS_UNSPECIFIED, s->data, size); 892 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 893 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 894 /* EOL detected */ 895 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 896 } else { 897 /* Clear in_use */ 898 size = sizeof(uint16_t) * width; 899 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 900 dp8393x_put(s, width, 0, 0); 901 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 902 s->data, size); 903 904 /* Move to next descriptor */ 905 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 906 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 907 } 908 909 dp8393x_update_irq(s); 910 911 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | 912 ((s->regs[SONIC_RSC] + 1) & 0x00ff); 913 914 done: 915 916 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 917 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) { 918 /* Stop packet reception */ 919 s->last_rba_is_full = true; 920 } else { 921 /* Read next resource */ 922 dp8393x_do_read_rra(s); 923 } 924 } 925 926 return pkt_size; 927 } 928 929 static void dp8393x_reset(DeviceState *dev) 930 { 931 dp8393xState *s = DP8393X(dev); 932 timer_del(s->watchdog); 933 934 memset(s->regs, 0, sizeof(s->regs)); 935 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */ 936 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 937 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 938 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 939 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 940 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 941 s->regs[SONIC_IMR] = 0; 942 s->regs[SONIC_ISR] = 0; 943 s->regs[SONIC_DCR2] = 0; 944 s->regs[SONIC_EOBC] = 0x02F8; 945 s->regs[SONIC_RSC] = 0; 946 s->regs[SONIC_CE] = 0; 947 s->regs[SONIC_RSC] = 0; 948 949 /* Network cable is connected */ 950 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 951 952 dp8393x_update_irq(s); 953 } 954 955 static NetClientInfo net_dp83932_info = { 956 .type = NET_CLIENT_DRIVER_NIC, 957 .size = sizeof(NICState), 958 .can_receive = dp8393x_can_receive, 959 .receive = dp8393x_receive, 960 }; 961 962 static void dp8393x_instance_init(Object *obj) 963 { 964 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 965 dp8393xState *s = DP8393X(obj); 966 967 sysbus_init_mmio(sbd, &s->mmio); 968 sysbus_init_mmio(sbd, &s->prom); 969 sysbus_init_irq(sbd, &s->irq); 970 } 971 972 static void dp8393x_realize(DeviceState *dev, Error **errp) 973 { 974 dp8393xState *s = DP8393X(dev); 975 int i, checksum; 976 uint8_t *prom; 977 Error *local_err = NULL; 978 979 address_space_init(&s->as, s->dma_mr, "dp8393x"); 980 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 981 "dp8393x-regs", 0x40 << s->it_shift); 982 983 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 984 object_get_typename(OBJECT(dev)), dev->id, s); 985 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 986 987 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 988 989 memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom", 990 SONIC_PROM_SIZE, &local_err); 991 if (local_err) { 992 error_propagate(errp, local_err); 993 return; 994 } 995 prom = memory_region_get_ram_ptr(&s->prom); 996 checksum = 0; 997 for (i = 0; i < 6; i++) { 998 prom[i] = s->conf.macaddr.a[i]; 999 checksum += prom[i]; 1000 if (checksum > 0xff) { 1001 checksum = (checksum + 1) & 0xff; 1002 } 1003 } 1004 prom[7] = 0xff - checksum; 1005 } 1006 1007 static const VMStateDescription vmstate_dp8393x = { 1008 .name = "dp8393x", 1009 .version_id = 0, 1010 .minimum_version_id = 0, 1011 .fields = (VMStateField []) { 1012 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 1013 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 1014 VMSTATE_END_OF_LIST() 1015 } 1016 }; 1017 1018 static Property dp8393x_properties[] = { 1019 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 1020 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 1021 TYPE_MEMORY_REGION, MemoryRegion *), 1022 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 1023 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 1024 DEFINE_PROP_END_OF_LIST(), 1025 }; 1026 1027 static void dp8393x_class_init(ObjectClass *klass, void *data) 1028 { 1029 DeviceClass *dc = DEVICE_CLASS(klass); 1030 1031 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1032 dc->realize = dp8393x_realize; 1033 dc->reset = dp8393x_reset; 1034 dc->vmsd = &vmstate_dp8393x; 1035 device_class_set_props(dc, dp8393x_properties); 1036 } 1037 1038 static const TypeInfo dp8393x_info = { 1039 .name = TYPE_DP8393X, 1040 .parent = TYPE_SYS_BUS_DEVICE, 1041 .instance_size = sizeof(dp8393xState), 1042 .instance_init = dp8393x_instance_init, 1043 .class_init = dp8393x_class_init, 1044 }; 1045 1046 static void dp8393x_register_types(void) 1047 { 1048 type_register_static(&dp8393x_info); 1049 } 1050 1051 type_init(dp8393x_register_types) 1052