1 /* 2 * ARM Versatile Express emulation. 3 * 4 * Copyright (c) 2010 - 2011 B Labs Ltd. 5 * Copyright (c) 2011 Linaro Limited 6 * Written by Bahadir Balban, Amit Mahajan, Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * Contributions after 2012-01-13 are licensed under the terms of the 21 * GNU GPL, version 2 or (at your option) any later version. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/arm/boot.h" 30 #include "hw/arm/primecell.h" 31 #include "hw/net/lan9118.h" 32 #include "hw/i2c/i2c.h" 33 #include "net/net.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/boards.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "hw/block/flash.h" 39 #include "sysemu/device_tree.h" 40 #include "qemu/error-report.h" 41 #include <libfdt.h> 42 #include "hw/char/pl011.h" 43 #include "hw/cpu/a9mpcore.h" 44 #include "hw/cpu/a15mpcore.h" 45 #include "hw/i2c/arm_sbcon_i2c.h" 46 #include "hw/sd/sd.h" 47 #include "qom/object.h" 48 49 #define VEXPRESS_BOARD_ID 0x8e0 50 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) 51 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) 52 53 /* Number of virtio transports to create (0..8; limited by 54 * number of available IRQ lines). 55 */ 56 #define NUM_VIRTIO_TRANSPORTS 4 57 58 /* Address maps for peripherals: 59 * the Versatile Express motherboard has two possible maps, 60 * the "legacy" one (used for A9) and the "Cortex-A Series" 61 * map (used for newer cores). 62 * Individual daughterboards can also have different maps for 63 * their peripherals. 64 */ 65 66 enum { 67 VE_SYSREGS, 68 VE_SP810, 69 VE_SERIALPCI, 70 VE_PL041, 71 VE_MMCI, 72 VE_KMI0, 73 VE_KMI1, 74 VE_UART0, 75 VE_UART1, 76 VE_UART2, 77 VE_UART3, 78 VE_WDT, 79 VE_TIMER01, 80 VE_TIMER23, 81 VE_SERIALDVI, 82 VE_RTC, 83 VE_COMPACTFLASH, 84 VE_CLCD, 85 VE_NORFLASH0, 86 VE_NORFLASH1, 87 VE_NORFLASHALIAS, 88 VE_SRAM, 89 VE_VIDEORAM, 90 VE_ETHERNET, 91 VE_USB, 92 VE_DAPROM, 93 VE_VIRTIO, 94 }; 95 96 static hwaddr motherboard_legacy_map[] = { 97 [VE_NORFLASHALIAS] = 0, 98 /* CS7: 0x10000000 .. 0x10020000 */ 99 [VE_SYSREGS] = 0x10000000, 100 [VE_SP810] = 0x10001000, 101 [VE_SERIALPCI] = 0x10002000, 102 [VE_PL041] = 0x10004000, 103 [VE_MMCI] = 0x10005000, 104 [VE_KMI0] = 0x10006000, 105 [VE_KMI1] = 0x10007000, 106 [VE_UART0] = 0x10009000, 107 [VE_UART1] = 0x1000a000, 108 [VE_UART2] = 0x1000b000, 109 [VE_UART3] = 0x1000c000, 110 [VE_WDT] = 0x1000f000, 111 [VE_TIMER01] = 0x10011000, 112 [VE_TIMER23] = 0x10012000, 113 [VE_VIRTIO] = 0x10013000, 114 [VE_SERIALDVI] = 0x10016000, 115 [VE_RTC] = 0x10017000, 116 [VE_COMPACTFLASH] = 0x1001a000, 117 [VE_CLCD] = 0x1001f000, 118 /* CS0: 0x40000000 .. 0x44000000 */ 119 [VE_NORFLASH0] = 0x40000000, 120 /* CS1: 0x44000000 .. 0x48000000 */ 121 [VE_NORFLASH1] = 0x44000000, 122 /* CS2: 0x48000000 .. 0x4a000000 */ 123 [VE_SRAM] = 0x48000000, 124 /* CS3: 0x4c000000 .. 0x50000000 */ 125 [VE_VIDEORAM] = 0x4c000000, 126 [VE_ETHERNET] = 0x4e000000, 127 [VE_USB] = 0x4f000000, 128 }; 129 130 static hwaddr motherboard_aseries_map[] = { 131 [VE_NORFLASHALIAS] = 0, 132 /* CS0: 0x08000000 .. 0x0c000000 */ 133 [VE_NORFLASH0] = 0x08000000, 134 /* CS4: 0x0c000000 .. 0x10000000 */ 135 [VE_NORFLASH1] = 0x0c000000, 136 /* CS5: 0x10000000 .. 0x14000000 */ 137 /* CS1: 0x14000000 .. 0x18000000 */ 138 [VE_SRAM] = 0x14000000, 139 /* CS2: 0x18000000 .. 0x1c000000 */ 140 [VE_VIDEORAM] = 0x18000000, 141 [VE_ETHERNET] = 0x1a000000, 142 [VE_USB] = 0x1b000000, 143 /* CS3: 0x1c000000 .. 0x20000000 */ 144 [VE_DAPROM] = 0x1c000000, 145 [VE_SYSREGS] = 0x1c010000, 146 [VE_SP810] = 0x1c020000, 147 [VE_SERIALPCI] = 0x1c030000, 148 [VE_PL041] = 0x1c040000, 149 [VE_MMCI] = 0x1c050000, 150 [VE_KMI0] = 0x1c060000, 151 [VE_KMI1] = 0x1c070000, 152 [VE_UART0] = 0x1c090000, 153 [VE_UART1] = 0x1c0a0000, 154 [VE_UART2] = 0x1c0b0000, 155 [VE_UART3] = 0x1c0c0000, 156 [VE_WDT] = 0x1c0f0000, 157 [VE_TIMER01] = 0x1c110000, 158 [VE_TIMER23] = 0x1c120000, 159 [VE_VIRTIO] = 0x1c130000, 160 [VE_SERIALDVI] = 0x1c160000, 161 [VE_RTC] = 0x1c170000, 162 [VE_COMPACTFLASH] = 0x1c1a0000, 163 [VE_CLCD] = 0x1c1f0000, 164 }; 165 166 /* Structure defining the peculiarities of a specific daughterboard */ 167 168 typedef struct VEDBoardInfo VEDBoardInfo; 169 170 struct VexpressMachineClass { 171 MachineClass parent; 172 VEDBoardInfo *daughterboard; 173 }; 174 typedef struct VexpressMachineClass VexpressMachineClass; 175 176 struct VexpressMachineState { 177 MachineState parent; 178 bool secure; 179 bool virt; 180 }; 181 typedef struct VexpressMachineState VexpressMachineState; 182 183 #define TYPE_VEXPRESS_MACHINE "vexpress" 184 #define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9") 185 #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") 186 #define VEXPRESS_MACHINE(obj) \ 187 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE) 188 #define VEXPRESS_MACHINE_GET_CLASS(obj) \ 189 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE) 190 #define VEXPRESS_MACHINE_CLASS(klass) \ 191 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE) 192 193 typedef void DBoardInitFn(const VexpressMachineState *machine, 194 ram_addr_t ram_size, 195 const char *cpu_type, 196 qemu_irq *pic); 197 198 struct VEDBoardInfo { 199 struct arm_boot_info bootinfo; 200 const hwaddr *motherboard_map; 201 hwaddr loader_start; 202 const hwaddr gic_cpu_if_addr; 203 uint32_t proc_id; 204 uint32_t num_voltage_sensors; 205 const uint32_t *voltages; 206 uint32_t num_clocks; 207 const uint32_t *clocks; 208 DBoardInitFn *init; 209 }; 210 211 static void init_cpus(MachineState *ms, const char *cpu_type, 212 const char *privdev, hwaddr periphbase, 213 qemu_irq *pic, bool secure, bool virt) 214 { 215 DeviceState *dev; 216 SysBusDevice *busdev; 217 int n; 218 unsigned int smp_cpus = ms->smp.cpus; 219 220 /* Create the actual CPUs */ 221 for (n = 0; n < smp_cpus; n++) { 222 Object *cpuobj = object_new(cpu_type); 223 224 if (!secure) { 225 object_property_set_bool(cpuobj, "has_el3", false, NULL); 226 } 227 if (!virt) { 228 if (object_property_find(cpuobj, "has_el2", NULL)) { 229 object_property_set_bool(cpuobj, "has_el2", false, NULL); 230 } 231 } 232 233 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 234 object_property_set_int(cpuobj, "reset-cbar", periphbase, 235 &error_abort); 236 } 237 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 238 } 239 240 /* Create the private peripheral devices (including the GIC); 241 * this must happen after the CPUs are created because a15mpcore_priv 242 * wires itself up to the CPU's generic_timer gpio out lines. 243 */ 244 dev = qdev_new(privdev); 245 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 246 busdev = SYS_BUS_DEVICE(dev); 247 sysbus_realize_and_unref(busdev, &error_fatal); 248 sysbus_mmio_map(busdev, 0, periphbase); 249 250 /* Interrupts [42:0] are from the motherboard; 251 * [47:43] are reserved; [63:48] are daughterboard 252 * peripherals. Note that some documentation numbers 253 * external interrupts starting from 32 (because there 254 * are internal interrupts 0..31). 255 */ 256 for (n = 0; n < 64; n++) { 257 pic[n] = qdev_get_gpio_in(dev, n); 258 } 259 260 /* Connect the CPUs to the GIC */ 261 for (n = 0; n < smp_cpus; n++) { 262 DeviceState *cpudev = DEVICE(qemu_get_cpu(n)); 263 264 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 265 sysbus_connect_irq(busdev, n + smp_cpus, 266 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 267 sysbus_connect_irq(busdev, n + 2 * smp_cpus, 268 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 269 sysbus_connect_irq(busdev, n + 3 * smp_cpus, 270 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 271 } 272 } 273 274 static void a9_daughterboard_init(const VexpressMachineState *vms, 275 ram_addr_t ram_size, 276 const char *cpu_type, 277 qemu_irq *pic) 278 { 279 MachineState *machine = MACHINE(vms); 280 MemoryRegion *sysmem = get_system_memory(); 281 MemoryRegion *lowram = g_new(MemoryRegion, 1); 282 ram_addr_t low_ram_size; 283 284 if (ram_size > 0x40000000) { 285 /* 1GB is the maximum the address space permits */ 286 error_report("vexpress-a9: cannot model more than 1GB RAM"); 287 exit(1); 288 } 289 290 low_ram_size = ram_size; 291 if (low_ram_size > 0x4000000) { 292 low_ram_size = 0x4000000; 293 } 294 /* RAM is from 0x60000000 upwards. The bottom 64MB of the 295 * address space should in theory be remappable to various 296 * things including ROM or RAM; we always map the RAM there. 297 */ 298 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram, 299 0, low_ram_size); 300 memory_region_add_subregion(sysmem, 0x0, lowram); 301 memory_region_add_subregion(sysmem, 0x60000000, machine->ram); 302 303 /* 0x1e000000 A9MPCore (SCU) private memory region */ 304 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, 305 vms->secure, vms->virt); 306 307 /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ 308 309 /* 0x10020000 PL111 CLCD (daughterboard) */ 310 sysbus_create_simple("pl111", 0x10020000, pic[44]); 311 312 /* 0x10060000 AXI RAM */ 313 /* 0x100e0000 PL341 Dynamic Memory Controller */ 314 /* 0x100e1000 PL354 Static Memory Controller */ 315 /* 0x100e2000 System Configuration Controller */ 316 317 sysbus_create_simple("sp804", 0x100e4000, pic[48]); 318 /* 0x100e5000 SP805 Watchdog module */ 319 /* 0x100e6000 BP147 TrustZone Protection Controller */ 320 /* 0x100e9000 PL301 'Fast' AXI matrix */ 321 /* 0x100ea000 PL301 'Slow' AXI matrix */ 322 /* 0x100ec000 TrustZone Address Space Controller */ 323 /* 0x10200000 CoreSight debug APB */ 324 /* 0x1e00a000 PL310 L2 Cache Controller */ 325 sysbus_create_varargs("l2x0", 0x1e00a000, NULL); 326 } 327 328 /* Voltage values for SYS_CFG_VOLT daughterboard registers; 329 * values are in microvolts. 330 */ 331 static const uint32_t a9_voltages[] = { 332 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ 333 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ 334 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ 335 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ 336 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ 337 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ 338 }; 339 340 /* Reset values for daughterboard oscillators (in Hz) */ 341 static const uint32_t a9_clocks[] = { 342 45000000, /* AMBA AXI ACLK: 45MHz */ 343 23750000, /* daughterboard CLCD clock: 23.75MHz */ 344 66670000, /* Test chip reference clock: 66.67MHz */ 345 }; 346 347 static VEDBoardInfo a9_daughterboard = { 348 .motherboard_map = motherboard_legacy_map, 349 .loader_start = 0x60000000, 350 .gic_cpu_if_addr = 0x1e000100, 351 .proc_id = 0x0c000191, 352 .num_voltage_sensors = ARRAY_SIZE(a9_voltages), 353 .voltages = a9_voltages, 354 .num_clocks = ARRAY_SIZE(a9_clocks), 355 .clocks = a9_clocks, 356 .init = a9_daughterboard_init, 357 }; 358 359 static void a15_daughterboard_init(const VexpressMachineState *vms, 360 ram_addr_t ram_size, 361 const char *cpu_type, 362 qemu_irq *pic) 363 { 364 MachineState *machine = MACHINE(vms); 365 MemoryRegion *sysmem = get_system_memory(); 366 MemoryRegion *sram = g_new(MemoryRegion, 1); 367 368 { 369 /* We have to use a separate 64 bit variable here to avoid the gcc 370 * "comparison is always false due to limited range of data type" 371 * warning if we are on a host where ram_addr_t is 32 bits. 372 */ 373 uint64_t rsz = ram_size; 374 if (rsz > (30ULL * 1024 * 1024 * 1024)) { 375 error_report("vexpress-a15: cannot model more than 30GB RAM"); 376 exit(1); 377 } 378 } 379 380 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 381 memory_region_add_subregion(sysmem, 0x80000000, machine->ram); 382 383 /* 0x2c000000 A15MPCore private memory region (GIC) */ 384 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, 385 0x2c000000, pic, vms->secure, vms->virt); 386 387 /* A15 daughterboard peripherals: */ 388 389 /* 0x20000000: CoreSight interfaces: not modelled */ 390 /* 0x2a000000: PL301 AXI interconnect: not modelled */ 391 /* 0x2a420000: SCC: not modelled */ 392 /* 0x2a430000: system counter: not modelled */ 393 /* 0x2b000000: HDLCD controller: not modelled */ 394 /* 0x2b060000: SP805 watchdog: not modelled */ 395 /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ 396 /* 0x2e000000: system SRAM */ 397 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, 398 &error_fatal); 399 memory_region_add_subregion(sysmem, 0x2e000000, sram); 400 401 /* 0x7ffb0000: DMA330 DMA controller: not modelled */ 402 /* 0x7ffd0000: PL354 static memory controller: not modelled */ 403 } 404 405 static const uint32_t a15_voltages[] = { 406 900000, /* Vcore: 0.9V : CPU core voltage */ 407 }; 408 409 static const uint32_t a15_clocks[] = { 410 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ 411 0, /* OSCCLK1: reserved */ 412 0, /* OSCCLK2: reserved */ 413 0, /* OSCCLK3: reserved */ 414 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ 415 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ 416 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ 417 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ 418 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ 419 }; 420 421 static VEDBoardInfo a15_daughterboard = { 422 .motherboard_map = motherboard_aseries_map, 423 .loader_start = 0x80000000, 424 .gic_cpu_if_addr = 0x2c002000, 425 .proc_id = 0x14000237, 426 .num_voltage_sensors = ARRAY_SIZE(a15_voltages), 427 .voltages = a15_voltages, 428 .num_clocks = ARRAY_SIZE(a15_clocks), 429 .clocks = a15_clocks, 430 .init = a15_daughterboard_init, 431 }; 432 433 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, 434 hwaddr addr, hwaddr size, uint32_t intc, 435 int irq) 436 { 437 /* Add a virtio_mmio node to the device tree blob: 438 * virtio_mmio@ADDRESS { 439 * compatible = "virtio,mmio"; 440 * reg = <ADDRESS, SIZE>; 441 * interrupt-parent = <&intc>; 442 * interrupts = <0, irq, 1>; 443 * } 444 * (Note that the format of the interrupts property is dependent on the 445 * interrupt controller that interrupt-parent points to; these are for 446 * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.) 447 */ 448 int rc; 449 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr); 450 451 rc = qemu_fdt_add_subnode(fdt, nodename); 452 rc |= qemu_fdt_setprop_string(fdt, nodename, 453 "compatible", "virtio,mmio"); 454 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", 455 acells, addr, scells, size); 456 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); 457 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); 458 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 459 g_free(nodename); 460 if (rc) { 461 return -1; 462 } 463 return 0; 464 } 465 466 static uint32_t find_int_controller(void *fdt) 467 { 468 /* Find the FDT node corresponding to the interrupt controller 469 * for virtio-mmio devices. We do this by scanning the fdt for 470 * a node with the right compatibility, since we know there is 471 * only one GIC on a vexpress board. 472 * We return the phandle of the node, or 0 if none was found. 473 */ 474 const char *compat = "arm,cortex-a9-gic"; 475 int offset; 476 477 offset = fdt_node_offset_by_compatible(fdt, -1, compat); 478 if (offset >= 0) { 479 return fdt_get_phandle(fdt, offset); 480 } 481 return 0; 482 } 483 484 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) 485 { 486 uint32_t acells, scells, intc; 487 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info; 488 489 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells", 490 NULL, &error_fatal); 491 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells", 492 NULL, &error_fatal); 493 intc = find_int_controller(fdt); 494 if (!intc) { 495 /* Not fatal, we just won't provide virtio. This will 496 * happen with older device tree blobs. 497 */ 498 warn_report("couldn't find interrupt controller in " 499 "dtb; will not include virtio-mmio devices in the dtb"); 500 } else { 501 int i; 502 const hwaddr *map = daughterboard->motherboard_map; 503 504 /* We iterate backwards here because adding nodes 505 * to the dtb puts them in last-first. 506 */ 507 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 508 add_virtio_mmio_node(fdt, acells, scells, 509 map[VE_VIRTIO] + 0x200 * i, 510 0x200, intc, 40 + i); 511 } 512 } 513 } 514 515 516 /* Open code a private version of pflash registration since we 517 * need to set non-default device width for VExpress platform. 518 */ 519 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 520 DriveInfo *di) 521 { 522 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 523 524 if (di) { 525 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); 526 } 527 528 qdev_prop_set_uint32(dev, "num-blocks", 529 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE); 530 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE); 531 qdev_prop_set_uint8(dev, "width", 4); 532 qdev_prop_set_uint8(dev, "device-width", 2); 533 qdev_prop_set_bit(dev, "big-endian", false); 534 qdev_prop_set_uint16(dev, "id0", 0x89); 535 qdev_prop_set_uint16(dev, "id1", 0x18); 536 qdev_prop_set_uint16(dev, "id2", 0x00); 537 qdev_prop_set_uint16(dev, "id3", 0x00); 538 qdev_prop_set_string(dev, "name", name); 539 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 540 541 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 542 return PFLASH_CFI01(dev); 543 } 544 545 static void vexpress_common_init(MachineState *machine) 546 { 547 VexpressMachineState *vms = VEXPRESS_MACHINE(machine); 548 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine); 549 VEDBoardInfo *daughterboard = vmc->daughterboard; 550 DeviceState *dev, *sysctl, *pl041; 551 qemu_irq pic[64]; 552 uint32_t sys_id; 553 DriveInfo *dinfo; 554 PFlashCFI01 *pflash0; 555 I2CBus *i2c; 556 ram_addr_t vram_size, sram_size; 557 MemoryRegion *sysmem = get_system_memory(); 558 MemoryRegion *vram = g_new(MemoryRegion, 1); 559 MemoryRegion *sram = g_new(MemoryRegion, 1); 560 MemoryRegion *flashalias = g_new(MemoryRegion, 1); 561 MemoryRegion *flash0mem; 562 const hwaddr *map = daughterboard->motherboard_map; 563 int i; 564 565 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic); 566 567 /* 568 * If a bios file was provided, attempt to map it into memory 569 */ 570 if (bios_name) { 571 char *fn; 572 int image_size; 573 574 if (drive_get(IF_PFLASH, 0, 0)) { 575 error_report("The contents of the first flash device may be " 576 "specified with -bios or with -drive if=pflash... " 577 "but you cannot use both options at once"); 578 exit(1); 579 } 580 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 581 if (!fn) { 582 error_report("Could not find ROM image '%s'", bios_name); 583 exit(1); 584 } 585 image_size = load_image_targphys(fn, map[VE_NORFLASH0], 586 VEXPRESS_FLASH_SIZE); 587 g_free(fn); 588 if (image_size < 0) { 589 error_report("Could not load ROM image '%s'", bios_name); 590 exit(1); 591 } 592 } 593 594 /* Motherboard peripherals: the wiring is the same but the 595 * addresses vary between the legacy and A-Series memory maps. 596 */ 597 598 sys_id = 0x1190f500; 599 600 sysctl = qdev_new("realview_sysctl"); 601 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 602 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 603 qdev_prop_set_uint32(sysctl, "len-db-voltage", 604 daughterboard->num_voltage_sensors); 605 for (i = 0; i < daughterboard->num_voltage_sensors; i++) { 606 char *propname = g_strdup_printf("db-voltage[%d]", i); 607 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); 608 g_free(propname); 609 } 610 qdev_prop_set_uint32(sysctl, "len-db-clock", 611 daughterboard->num_clocks); 612 for (i = 0; i < daughterboard->num_clocks; i++) { 613 char *propname = g_strdup_printf("db-clock[%d]", i); 614 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 615 g_free(propname); 616 } 617 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 618 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 619 620 /* VE_SP810: not modelled */ 621 /* VE_SERIALPCI: not modelled */ 622 623 pl041 = qdev_new("pl041"); 624 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 625 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 626 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 627 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 628 629 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); 630 /* Wire up MMC card detect and read-only signals */ 631 qdev_connect_gpio_out_named(dev, "card-read-only", 0, 632 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); 633 qdev_connect_gpio_out_named(dev, "card-inserted", 0, 634 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); 635 dinfo = drive_get_next(IF_SD); 636 if (dinfo) { 637 DeviceState *card; 638 639 card = qdev_new(TYPE_SD_CARD); 640 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 641 &error_fatal); 642 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"), 643 &error_fatal); 644 } 645 646 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); 647 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); 648 649 pl011_create(map[VE_UART0], pic[5], serial_hd(0)); 650 pl011_create(map[VE_UART1], pic[6], serial_hd(1)); 651 pl011_create(map[VE_UART2], pic[7], serial_hd(2)); 652 pl011_create(map[VE_UART3], pic[8], serial_hd(3)); 653 654 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); 655 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); 656 657 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL); 658 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 659 i2c_slave_create_simple(i2c, "sii9022", 0x39); 660 661 sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ 662 663 /* VE_COMPACTFLASH: not modelled */ 664 665 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); 666 667 dinfo = drive_get_next(IF_PFLASH); 668 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", 669 dinfo); 670 if (!pflash0) { 671 error_report("vexpress: error registering flash 0"); 672 exit(1); 673 } 674 675 if (map[VE_NORFLASHALIAS] != -1) { 676 /* Map flash 0 as an alias into low memory */ 677 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); 678 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", 679 flash0mem, 0, VEXPRESS_FLASH_SIZE); 680 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); 681 } 682 683 dinfo = drive_get_next(IF_PFLASH); 684 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", 685 dinfo)) { 686 error_report("vexpress: error registering flash 1"); 687 exit(1); 688 } 689 690 sram_size = 0x2000000; 691 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, 692 &error_fatal); 693 memory_region_add_subregion(sysmem, map[VE_SRAM], sram); 694 695 vram_size = 0x800000; 696 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, 697 &error_fatal); 698 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); 699 700 /* 0x4e000000 LAN9118 Ethernet */ 701 if (nd_table[0].used) { 702 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); 703 } 704 705 /* VE_USB: not modelled */ 706 707 /* VE_DAPROM: not modelled */ 708 709 /* Create mmio transports, so the user can create virtio backends 710 * (which will be automatically plugged in to the transports). If 711 * no backend is created the transport will just sit harmlessly idle. 712 */ 713 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 714 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i, 715 pic[40 + i]); 716 } 717 718 daughterboard->bootinfo.ram_size = machine->ram_size; 719 daughterboard->bootinfo.nb_cpus = machine->smp.cpus; 720 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; 721 daughterboard->bootinfo.loader_start = daughterboard->loader_start; 722 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; 723 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; 724 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; 725 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; 726 /* When booting Linux we should be in secure state if the CPU has one. */ 727 daughterboard->bootinfo.secure_boot = vms->secure; 728 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo); 729 } 730 731 static bool vexpress_get_secure(Object *obj, Error **errp) 732 { 733 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 734 735 return vms->secure; 736 } 737 738 static void vexpress_set_secure(Object *obj, bool value, Error **errp) 739 { 740 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 741 742 vms->secure = value; 743 } 744 745 static bool vexpress_get_virt(Object *obj, Error **errp) 746 { 747 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 748 749 return vms->virt; 750 } 751 752 static void vexpress_set_virt(Object *obj, bool value, Error **errp) 753 { 754 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 755 756 vms->virt = value; 757 } 758 759 static void vexpress_instance_init(Object *obj) 760 { 761 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 762 763 /* EL3 is enabled by default on vexpress */ 764 vms->secure = true; 765 object_property_add_bool(obj, "secure", vexpress_get_secure, 766 vexpress_set_secure); 767 object_property_set_description(obj, "secure", 768 "Set on/off to enable/disable the ARM " 769 "Security Extensions (TrustZone)"); 770 } 771 772 static void vexpress_a15_instance_init(Object *obj) 773 { 774 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 775 776 /* 777 * For the vexpress-a15, EL2 is by default enabled if EL3 is, 778 * but can also be specifically set to on or off. 779 */ 780 vms->virt = true; 781 object_property_add_bool(obj, "virtualization", vexpress_get_virt, 782 vexpress_set_virt); 783 object_property_set_description(obj, "virtualization", 784 "Set on/off to enable/disable the ARM " 785 "Virtualization Extensions " 786 "(defaults to same as 'secure')"); 787 } 788 789 static void vexpress_a9_instance_init(Object *obj) 790 { 791 VexpressMachineState *vms = VEXPRESS_MACHINE(obj); 792 793 /* The A9 doesn't have the virt extensions */ 794 vms->virt = false; 795 } 796 797 static void vexpress_class_init(ObjectClass *oc, void *data) 798 { 799 MachineClass *mc = MACHINE_CLASS(oc); 800 801 mc->desc = "ARM Versatile Express"; 802 mc->init = vexpress_common_init; 803 mc->max_cpus = 4; 804 mc->ignore_memory_transaction_failures = true; 805 mc->default_ram_id = "vexpress.highmem"; 806 } 807 808 static void vexpress_a9_class_init(ObjectClass *oc, void *data) 809 { 810 MachineClass *mc = MACHINE_CLASS(oc); 811 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 812 813 mc->desc = "ARM Versatile Express for Cortex-A9"; 814 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 815 816 vmc->daughterboard = &a9_daughterboard; 817 } 818 819 static void vexpress_a15_class_init(ObjectClass *oc, void *data) 820 { 821 MachineClass *mc = MACHINE_CLASS(oc); 822 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); 823 824 mc->desc = "ARM Versatile Express for Cortex-A15"; 825 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 826 827 vmc->daughterboard = &a15_daughterboard; 828 } 829 830 static const TypeInfo vexpress_info = { 831 .name = TYPE_VEXPRESS_MACHINE, 832 .parent = TYPE_MACHINE, 833 .abstract = true, 834 .instance_size = sizeof(VexpressMachineState), 835 .instance_init = vexpress_instance_init, 836 .class_size = sizeof(VexpressMachineClass), 837 .class_init = vexpress_class_init, 838 }; 839 840 static const TypeInfo vexpress_a9_info = { 841 .name = TYPE_VEXPRESS_A9_MACHINE, 842 .parent = TYPE_VEXPRESS_MACHINE, 843 .class_init = vexpress_a9_class_init, 844 .instance_init = vexpress_a9_instance_init, 845 }; 846 847 static const TypeInfo vexpress_a15_info = { 848 .name = TYPE_VEXPRESS_A15_MACHINE, 849 .parent = TYPE_VEXPRESS_MACHINE, 850 .class_init = vexpress_a15_class_init, 851 .instance_init = vexpress_a15_instance_init, 852 }; 853 854 static void vexpress_machine_init(void) 855 { 856 type_register_static(&vexpress_info); 857 type_register_static(&vexpress_a9_info); 858 type_register_static(&vexpress_a15_info); 859 } 860 861 type_init(vexpress_machine_init); 862