1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2015 Imagination Technologies 7 * 8 */ 9 10 #ifndef MIPS_CMGCR_H 11 #define MIPS_CMGCR_H 12 13 #include "hw/sysbus.h" 14 #include "qom/object.h" 15 16 #define TYPE_MIPS_GCR "mips-gcr" 17 typedef struct MIPSGCRState MIPSGCRState; 18 #define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR) 19 20 #define GCR_BASE_ADDR 0x1fbf8000ULL 21 #define GCR_ADDRSPACE_SZ 0x8000 22 23 /* Offsets to register blocks */ 24 #define MIPS_GCB_OFS 0x0000 /* Global Control Block */ 25 #define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */ 26 #define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */ 27 #define MIPS_GDB_OFS 0x6000 /* Global Debug Block */ 28 29 /* Global Control Block Register Map */ 30 #define GCR_CONFIG_OFS 0x0000 31 #define GCR_BASE_OFS 0x0008 32 #define GCR_REV_OFS 0x0030 33 #define GCR_GIC_BASE_OFS 0x0080 34 #define GCR_CPC_BASE_OFS 0x0088 35 #define GCR_GIC_STATUS_OFS 0x00D0 36 #define GCR_CPC_STATUS_OFS 0x00F0 37 #define GCR_L2_CONFIG_OFS 0x0130 38 39 /* Core Local and Core Other Block Register Map */ 40 #define GCR_CL_CONFIG_OFS 0x0010 41 #define GCR_CL_OTHER_OFS 0x0018 42 #define GCR_CL_RESETBASE_OFS 0x0020 43 44 /* GCR_L2_CONFIG register fields */ 45 #define GCR_L2_CONFIG_BYPASS_SHF 20 46 #define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF) 47 48 /* GCR_BASE register fields */ 49 #define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL 50 51 /* GCR_GIC_BASE register fields */ 52 #define GCR_GIC_BASE_GICEN_MSK 1 53 #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL 54 #define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK) 55 56 /* GCR_CPC_BASE register fields */ 57 #define GCR_CPC_BASE_CPCEN_MSK 1 58 #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL 59 #define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK) 60 61 /* GCR_CL_OTHER_OFS register fields */ 62 #define GCR_CL_OTHER_VPOTHER_MSK 0x7 63 #define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK 64 65 /* GCR_CL_RESETBASE_OFS register fields */ 66 #define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U 67 #define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK 68 69 typedef struct MIPSGCRVPState MIPSGCRVPState; 70 struct MIPSGCRVPState { 71 uint32_t other; 72 uint64_t reset_base; 73 }; 74 75 struct MIPSGCRState { 76 SysBusDevice parent_obj; 77 78 int32_t gcr_rev; 79 int32_t num_vps; 80 hwaddr gcr_base; 81 MemoryRegion iomem; 82 MemoryRegion *cpc_mr; 83 MemoryRegion *gic_mr; 84 85 uint64_t cpc_base; 86 uint64_t gic_base; 87 88 /* VP Local/Other Registers */ 89 MIPSGCRVPState *vps; 90 }; 91 92 #endif /* MIPS_CMGCR_H */ 93