1 /* 2 * Arm PrimeCell PL061 General Purpose IO with additional 3 * Luminary Micro Stellaris bits. 4 * 5 * Copyright (c) 2007 CodeSourcery. 6 * Written by Paul Brook 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "hw/irq.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "qom/object.h" 18 19 //#define DEBUG_PL061 1 20 21 #ifdef DEBUG_PL061 22 #define DPRINTF(fmt, ...) \ 23 do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) 24 #define BADF(fmt, ...) \ 25 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) 26 #else 27 #define DPRINTF(fmt, ...) do {} while(0) 28 #define BADF(fmt, ...) \ 29 do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) 30 #endif 31 32 static const uint8_t pl061_id[12] = 33 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; 34 static const uint8_t pl061_id_luminary[12] = 35 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; 36 37 #define TYPE_PL061 "pl061" 38 typedef struct PL061State PL061State; 39 #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) 40 41 #define N_GPIOS 8 42 43 struct PL061State { 44 SysBusDevice parent_obj; 45 46 MemoryRegion iomem; 47 uint32_t locked; 48 uint32_t data; 49 uint32_t old_out_data; 50 uint32_t old_in_data; 51 uint32_t dir; 52 uint32_t isense; 53 uint32_t ibe; 54 uint32_t iev; 55 uint32_t im; 56 uint32_t istate; 57 uint32_t afsel; 58 uint32_t dr2r; 59 uint32_t dr4r; 60 uint32_t dr8r; 61 uint32_t odr; 62 uint32_t pur; 63 uint32_t pdr; 64 uint32_t slr; 65 uint32_t den; 66 uint32_t cr; 67 uint32_t amsel; 68 qemu_irq irq; 69 qemu_irq out[N_GPIOS]; 70 const unsigned char *id; 71 uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ 72 }; 73 74 static const VMStateDescription vmstate_pl061 = { 75 .name = "pl061", 76 .version_id = 4, 77 .minimum_version_id = 4, 78 .fields = (VMStateField[]) { 79 VMSTATE_UINT32(locked, PL061State), 80 VMSTATE_UINT32(data, PL061State), 81 VMSTATE_UINT32(old_out_data, PL061State), 82 VMSTATE_UINT32(old_in_data, PL061State), 83 VMSTATE_UINT32(dir, PL061State), 84 VMSTATE_UINT32(isense, PL061State), 85 VMSTATE_UINT32(ibe, PL061State), 86 VMSTATE_UINT32(iev, PL061State), 87 VMSTATE_UINT32(im, PL061State), 88 VMSTATE_UINT32(istate, PL061State), 89 VMSTATE_UINT32(afsel, PL061State), 90 VMSTATE_UINT32(dr2r, PL061State), 91 VMSTATE_UINT32(dr4r, PL061State), 92 VMSTATE_UINT32(dr8r, PL061State), 93 VMSTATE_UINT32(odr, PL061State), 94 VMSTATE_UINT32(pur, PL061State), 95 VMSTATE_UINT32(pdr, PL061State), 96 VMSTATE_UINT32(slr, PL061State), 97 VMSTATE_UINT32(den, PL061State), 98 VMSTATE_UINT32(cr, PL061State), 99 VMSTATE_UINT32_V(amsel, PL061State, 2), 100 VMSTATE_END_OF_LIST() 101 } 102 }; 103 104 static void pl061_update(PL061State *s) 105 { 106 uint8_t changed; 107 uint8_t mask; 108 uint8_t out; 109 int i; 110 111 DPRINTF("dir = %d, data = %d\n", s->dir, s->data); 112 113 /* Outputs float high. */ 114 /* FIXME: This is board dependent. */ 115 out = (s->data & s->dir) | ~s->dir; 116 changed = s->old_out_data ^ out; 117 if (changed) { 118 s->old_out_data = out; 119 for (i = 0; i < N_GPIOS; i++) { 120 mask = 1 << i; 121 if (changed & mask) { 122 DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); 123 qemu_set_irq(s->out[i], (out & mask) != 0); 124 } 125 } 126 } 127 128 /* Inputs */ 129 changed = (s->old_in_data ^ s->data) & ~s->dir; 130 if (changed) { 131 s->old_in_data = s->data; 132 for (i = 0; i < N_GPIOS; i++) { 133 mask = 1 << i; 134 if (changed & mask) { 135 DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); 136 137 if (!(s->isense & mask)) { 138 /* Edge interrupt */ 139 if (s->ibe & mask) { 140 /* Any edge triggers the interrupt */ 141 s->istate |= mask; 142 } else { 143 /* Edge is selected by IEV */ 144 s->istate |= ~(s->data ^ s->iev) & mask; 145 } 146 } 147 } 148 } 149 } 150 151 /* Level interrupt */ 152 s->istate |= ~(s->data ^ s->iev) & s->isense; 153 154 DPRINTF("istate = %02X\n", s->istate); 155 156 qemu_set_irq(s->irq, (s->istate & s->im) != 0); 157 } 158 159 static uint64_t pl061_read(void *opaque, hwaddr offset, 160 unsigned size) 161 { 162 PL061State *s = (PL061State *)opaque; 163 164 if (offset < 0x400) { 165 return s->data & (offset >> 2); 166 } 167 if (offset >= s->rsvd_start && offset <= 0xfcc) { 168 goto err_out; 169 } 170 if (offset >= 0xfd0 && offset < 0x1000) { 171 return s->id[(offset - 0xfd0) >> 2]; 172 } 173 switch (offset) { 174 case 0x400: /* Direction */ 175 return s->dir; 176 case 0x404: /* Interrupt sense */ 177 return s->isense; 178 case 0x408: /* Interrupt both edges */ 179 return s->ibe; 180 case 0x40c: /* Interrupt event */ 181 return s->iev; 182 case 0x410: /* Interrupt mask */ 183 return s->im; 184 case 0x414: /* Raw interrupt status */ 185 return s->istate; 186 case 0x418: /* Masked interrupt status */ 187 return s->istate & s->im; 188 case 0x420: /* Alternate function select */ 189 return s->afsel; 190 case 0x500: /* 2mA drive */ 191 return s->dr2r; 192 case 0x504: /* 4mA drive */ 193 return s->dr4r; 194 case 0x508: /* 8mA drive */ 195 return s->dr8r; 196 case 0x50c: /* Open drain */ 197 return s->odr; 198 case 0x510: /* Pull-up */ 199 return s->pur; 200 case 0x514: /* Pull-down */ 201 return s->pdr; 202 case 0x518: /* Slew rate control */ 203 return s->slr; 204 case 0x51c: /* Digital enable */ 205 return s->den; 206 case 0x520: /* Lock */ 207 return s->locked; 208 case 0x524: /* Commit */ 209 return s->cr; 210 case 0x528: /* Analog mode select */ 211 return s->amsel; 212 default: 213 break; 214 } 215 err_out: 216 qemu_log_mask(LOG_GUEST_ERROR, 217 "pl061_read: Bad offset %x\n", (int)offset); 218 return 0; 219 } 220 221 static void pl061_write(void *opaque, hwaddr offset, 222 uint64_t value, unsigned size) 223 { 224 PL061State *s = (PL061State *)opaque; 225 uint8_t mask; 226 227 if (offset < 0x400) { 228 mask = (offset >> 2) & s->dir; 229 s->data = (s->data & ~mask) | (value & mask); 230 pl061_update(s); 231 return; 232 } 233 if (offset >= s->rsvd_start) { 234 goto err_out; 235 } 236 switch (offset) { 237 case 0x400: /* Direction */ 238 s->dir = value & 0xff; 239 break; 240 case 0x404: /* Interrupt sense */ 241 s->isense = value & 0xff; 242 break; 243 case 0x408: /* Interrupt both edges */ 244 s->ibe = value & 0xff; 245 break; 246 case 0x40c: /* Interrupt event */ 247 s->iev = value & 0xff; 248 break; 249 case 0x410: /* Interrupt mask */ 250 s->im = value & 0xff; 251 break; 252 case 0x41c: /* Interrupt clear */ 253 s->istate &= ~value; 254 break; 255 case 0x420: /* Alternate function select */ 256 mask = s->cr; 257 s->afsel = (s->afsel & ~mask) | (value & mask); 258 break; 259 case 0x500: /* 2mA drive */ 260 s->dr2r = value & 0xff; 261 break; 262 case 0x504: /* 4mA drive */ 263 s->dr4r = value & 0xff; 264 break; 265 case 0x508: /* 8mA drive */ 266 s->dr8r = value & 0xff; 267 break; 268 case 0x50c: /* Open drain */ 269 s->odr = value & 0xff; 270 break; 271 case 0x510: /* Pull-up */ 272 s->pur = value & 0xff; 273 break; 274 case 0x514: /* Pull-down */ 275 s->pdr = value & 0xff; 276 break; 277 case 0x518: /* Slew rate control */ 278 s->slr = value & 0xff; 279 break; 280 case 0x51c: /* Digital enable */ 281 s->den = value & 0xff; 282 break; 283 case 0x520: /* Lock */ 284 s->locked = (value != 0xacce551); 285 break; 286 case 0x524: /* Commit */ 287 if (!s->locked) 288 s->cr = value & 0xff; 289 break; 290 case 0x528: 291 s->amsel = value & 0xff; 292 break; 293 default: 294 goto err_out; 295 } 296 pl061_update(s); 297 return; 298 err_out: 299 qemu_log_mask(LOG_GUEST_ERROR, 300 "pl061_write: Bad offset %x\n", (int)offset); 301 } 302 303 static void pl061_reset(DeviceState *dev) 304 { 305 PL061State *s = PL061(dev); 306 307 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ 308 s->data = 0; 309 s->old_out_data = 0; 310 s->old_in_data = 0; 311 s->dir = 0; 312 s->isense = 0; 313 s->ibe = 0; 314 s->iev = 0; 315 s->im = 0; 316 s->istate = 0; 317 s->afsel = 0; 318 s->dr2r = 0xff; 319 s->dr4r = 0; 320 s->dr8r = 0; 321 s->odr = 0; 322 s->pur = 0; 323 s->pdr = 0; 324 s->slr = 0; 325 s->den = 0; 326 s->locked = 1; 327 s->cr = 0xff; 328 s->amsel = 0; 329 } 330 331 static void pl061_set_irq(void * opaque, int irq, int level) 332 { 333 PL061State *s = (PL061State *)opaque; 334 uint8_t mask; 335 336 mask = 1 << irq; 337 if ((s->dir & mask) == 0) { 338 s->data &= ~mask; 339 if (level) 340 s->data |= mask; 341 pl061_update(s); 342 } 343 } 344 345 static const MemoryRegionOps pl061_ops = { 346 .read = pl061_read, 347 .write = pl061_write, 348 .endianness = DEVICE_NATIVE_ENDIAN, 349 }; 350 351 static void pl061_luminary_init(Object *obj) 352 { 353 PL061State *s = PL061(obj); 354 355 s->id = pl061_id_luminary; 356 s->rsvd_start = 0x52c; 357 } 358 359 static void pl061_init(Object *obj) 360 { 361 PL061State *s = PL061(obj); 362 DeviceState *dev = DEVICE(obj); 363 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 364 365 s->id = pl061_id; 366 s->rsvd_start = 0x424; 367 368 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); 369 sysbus_init_mmio(sbd, &s->iomem); 370 sysbus_init_irq(sbd, &s->irq); 371 qdev_init_gpio_in(dev, pl061_set_irq, N_GPIOS); 372 qdev_init_gpio_out(dev, s->out, N_GPIOS); 373 } 374 375 static void pl061_class_init(ObjectClass *klass, void *data) 376 { 377 DeviceClass *dc = DEVICE_CLASS(klass); 378 379 dc->vmsd = &vmstate_pl061; 380 dc->reset = &pl061_reset; 381 } 382 383 static const TypeInfo pl061_info = { 384 .name = TYPE_PL061, 385 .parent = TYPE_SYS_BUS_DEVICE, 386 .instance_size = sizeof(PL061State), 387 .instance_init = pl061_init, 388 .class_init = pl061_class_init, 389 }; 390 391 static const TypeInfo pl061_luminary_info = { 392 .name = "pl061_luminary", 393 .parent = TYPE_PL061, 394 .instance_init = pl061_luminary_init, 395 }; 396 397 static void pl061_register_types(void) 398 { 399 type_register_static(&pl061_info); 400 type_register_static(&pl061_luminary_info); 401 } 402 403 type_init(pl061_register_types) 404