1 /* 2 * QEMU PowerPC XIVE interrupt controller model 3 * 4 * Copyright (c) 2017-2019, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PPC_PNV_XIVE_H 11 #define PPC_PNV_XIVE_H 12 13 #include "hw/ppc/xive.h" 14 #include "qom/object.h" 15 16 struct PnvChip; 17 18 #define TYPE_PNV_XIVE "pnv-xive" 19 typedef struct PnvXive PnvXive; 20 typedef struct PnvXiveClass PnvXiveClass; 21 #define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE) 22 #define PNV_XIVE_CLASS(klass) \ 23 OBJECT_CLASS_CHECK(PnvXiveClass, (klass), TYPE_PNV_XIVE) 24 #define PNV_XIVE_GET_CLASS(obj) \ 25 OBJECT_GET_CLASS(PnvXiveClass, (obj), TYPE_PNV_XIVE) 26 27 #define XIVE_BLOCK_MAX 16 28 29 #define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */ 30 #define XIVE_TABLE_MIG_MAX 16 /* Migration Register Table (1-15) */ 31 #define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */ 32 #define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */ 33 34 struct PnvXive { 35 XiveRouter parent_obj; 36 37 /* Owning chip */ 38 struct PnvChip *chip; 39 40 /* XSCOM addresses giving access to the controller registers */ 41 MemoryRegion xscom_regs; 42 43 /* Main MMIO regions that can be configured by FW */ 44 MemoryRegion ic_mmio; 45 MemoryRegion ic_reg_mmio; 46 MemoryRegion ic_notify_mmio; 47 MemoryRegion ic_lsi_mmio; 48 MemoryRegion tm_indirect_mmio; 49 MemoryRegion vc_mmio; 50 MemoryRegion pc_mmio; 51 MemoryRegion tm_mmio; 52 53 /* 54 * IPI and END address spaces modeling the EDT segmentation in the 55 * VC region 56 */ 57 AddressSpace ipi_as; 58 MemoryRegion ipi_mmio; 59 MemoryRegion ipi_edt_mmio; 60 61 AddressSpace end_as; 62 MemoryRegion end_mmio; 63 MemoryRegion end_edt_mmio; 64 65 /* Shortcut values for the Main MMIO regions */ 66 hwaddr ic_base; 67 uint32_t ic_shift; 68 hwaddr vc_base; 69 uint32_t vc_shift; 70 hwaddr pc_base; 71 uint32_t pc_shift; 72 hwaddr tm_base; 73 uint32_t tm_shift; 74 75 /* Our XIVE source objects for IPIs and ENDs */ 76 XiveSource ipi_source; 77 XiveENDSource end_source; 78 79 /* Interrupt controller registers */ 80 uint64_t regs[0x300]; 81 82 /* 83 * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ 84 * These are in a SRAM protected by ECC. 85 */ 86 uint64_t vsds[5][XIVE_BLOCK_MAX]; 87 88 /* Translation tables */ 89 uint64_t blk[XIVE_TABLE_BLK_MAX]; 90 uint64_t mig[XIVE_TABLE_MIG_MAX]; 91 uint64_t vdt[XIVE_TABLE_VDT_MAX]; 92 uint64_t edt[XIVE_TABLE_EDT_MAX]; 93 }; 94 95 struct PnvXiveClass { 96 XiveRouterClass parent_class; 97 98 DeviceRealize parent_realize; 99 }; 100 101 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon); 102 103 #endif /* PPC_PNV_XIVE_H */ 104