1 /* 2 * ARM Generic Interrupt Controller using KVM in-kernel support 3 * 4 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 5 * Written by Pavel Fedin 6 * Based on vGICv2 code by Peter Maydell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/intc/arm_gicv3_common.h" 25 #include "hw/sysbus.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/runstate.h" 30 #include "kvm_arm.h" 31 #include "gicv3_internal.h" 32 #include "vgic_common.h" 33 #include "migration/blocker.h" 34 #include "qom/object.h" 35 36 #ifdef DEBUG_GICV3_KVM 37 #define DPRINTF(fmt, ...) \ 38 do { fprintf(stderr, "kvm_gicv3: " fmt, ## __VA_ARGS__); } while (0) 39 #else 40 #define DPRINTF(fmt, ...) \ 41 do { } while (0) 42 #endif 43 44 #define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3" 45 typedef struct KVMARMGICv3Class KVMARMGICv3Class; 46 #define KVM_ARM_GICV3(obj) \ 47 OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3) 48 #define KVM_ARM_GICV3_CLASS(klass) \ 49 OBJECT_CLASS_CHECK(KVMARMGICv3Class, (klass), TYPE_KVM_ARM_GICV3) 50 #define KVM_ARM_GICV3_GET_CLASS(obj) \ 51 OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3) 52 53 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ 54 (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 55 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 56 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 57 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 58 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 59 60 #define ICC_PMR_EL1 \ 61 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0) 62 #define ICC_BPR0_EL1 \ 63 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3) 64 #define ICC_AP0R_EL1(n) \ 65 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n) 66 #define ICC_AP1R_EL1(n) \ 67 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n) 68 #define ICC_BPR1_EL1 \ 69 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) 70 #define ICC_CTLR_EL1 \ 71 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) 72 #define ICC_SRE_EL1 \ 73 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) 74 #define ICC_IGRPEN0_EL1 \ 75 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) 76 #define ICC_IGRPEN1_EL1 \ 77 KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7) 78 79 struct KVMARMGICv3Class { 80 ARMGICv3CommonClass parent_class; 81 DeviceRealize parent_realize; 82 void (*parent_reset)(DeviceState *dev); 83 }; 84 85 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) 86 { 87 GICv3State *s = (GICv3State *)opaque; 88 89 kvm_arm_gic_set_irq(s->num_irq, irq, level); 90 } 91 92 #define KVM_VGIC_ATTR(reg, typer) \ 93 ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg)) 94 95 static inline void kvm_gicd_access(GICv3State *s, int offset, 96 uint32_t *val, bool write) 97 { 98 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 99 KVM_VGIC_ATTR(offset, 0), 100 val, write, &error_abort); 101 } 102 103 static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, 104 uint32_t *val, bool write) 105 { 106 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, 107 KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), 108 val, write, &error_abort); 109 } 110 111 static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, 112 uint64_t *val, bool write) 113 { 114 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 115 KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), 116 val, write, &error_abort); 117 } 118 119 static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, 120 uint32_t *val, bool write) 121 { 122 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, 123 KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | 124 (VGIC_LEVEL_INFO_LINE_LEVEL << 125 KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), 126 val, write, &error_abort); 127 } 128 129 /* Loop through each distributor IRQ related register; since bits 130 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing 131 * is enabled, we skip those. 132 */ 133 #define for_each_dist_irq_reg(_irq, _max, _field_width) \ 134 for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width)) 135 136 static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 137 { 138 uint32_t reg, *field; 139 int irq; 140 141 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 142 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 143 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 144 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 145 * offset. 146 */ 147 field = (uint32_t *)(bmp + GIC_INTERNAL); 148 offset += (GIC_INTERNAL * 8) / 8; 149 for_each_dist_irq_reg(irq, s->num_irq, 8) { 150 kvm_gicd_access(s, offset, ®, false); 151 *field = reg; 152 offset += 4; 153 field++; 154 } 155 } 156 157 static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) 158 { 159 uint32_t reg, *field; 160 int irq; 161 162 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 163 * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding 164 * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to 165 * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and 166 * offset. 167 */ 168 field = (uint32_t *)(bmp + GIC_INTERNAL); 169 offset += (GIC_INTERNAL * 8) / 8; 170 for_each_dist_irq_reg(irq, s->num_irq, 8) { 171 reg = *field; 172 kvm_gicd_access(s, offset, ®, true); 173 offset += 4; 174 field++; 175 } 176 } 177 178 static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset, 179 uint32_t *bmp) 180 { 181 uint32_t reg; 182 int irq; 183 184 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 185 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 186 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 187 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 188 * This matches the for_each_dist_irq_reg() macro which also skips the 189 * first GIC_INTERNAL irqs. 190 */ 191 offset += (GIC_INTERNAL * 2) / 8; 192 for_each_dist_irq_reg(irq, s->num_irq, 2) { 193 kvm_gicd_access(s, offset, ®, false); 194 reg = half_unshuffle32(reg >> 1); 195 if (irq % 32 != 0) { 196 reg = (reg << 16); 197 } 198 *gic_bmp_ptr32(bmp, irq) |= reg; 199 offset += 4; 200 } 201 } 202 203 static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset, 204 uint32_t *bmp) 205 { 206 uint32_t reg; 207 int irq; 208 209 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 210 * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding 211 * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync 212 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 213 * This matches the for_each_dist_irq_reg() macro which also skips the 214 * first GIC_INTERNAL irqs. 215 */ 216 offset += (GIC_INTERNAL * 2) / 8; 217 for_each_dist_irq_reg(irq, s->num_irq, 2) { 218 reg = *gic_bmp_ptr32(bmp, irq); 219 if (irq % 32 != 0) { 220 reg = (reg & 0xffff0000) >> 16; 221 } else { 222 reg = reg & 0xffff; 223 } 224 reg = half_shuffle32(reg) << 1; 225 kvm_gicd_access(s, offset, ®, true); 226 offset += 4; 227 } 228 } 229 230 static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp) 231 { 232 uint32_t reg; 233 int irq; 234 235 for_each_dist_irq_reg(irq, s->num_irq, 1) { 236 kvm_gic_line_level_access(s, irq, 0, ®, false); 237 *gic_bmp_ptr32(bmp, irq) = reg; 238 } 239 } 240 241 static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp) 242 { 243 uint32_t reg; 244 int irq; 245 246 for_each_dist_irq_reg(irq, s->num_irq, 1) { 247 reg = *gic_bmp_ptr32(bmp, irq); 248 kvm_gic_line_level_access(s, irq, 0, ®, true); 249 } 250 } 251 252 /* Read a bitmap register group from the kernel VGIC. */ 253 static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp) 254 { 255 uint32_t reg; 256 int irq; 257 258 /* For the KVM GICv3, affinity routing is always enabled, and the 259 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 260 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 261 * functionality is replaced by the GICR registers. It doesn't need to sync 262 * them. So it should increase the offset to skip GIC_INTERNAL irqs. 263 * This matches the for_each_dist_irq_reg() macro which also skips the 264 * first GIC_INTERNAL irqs. 265 */ 266 offset += (GIC_INTERNAL * 1) / 8; 267 for_each_dist_irq_reg(irq, s->num_irq, 1) { 268 kvm_gicd_access(s, offset, ®, false); 269 *gic_bmp_ptr32(bmp, irq) = reg; 270 offset += 4; 271 } 272 } 273 274 static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, 275 uint32_t clroffset, uint32_t *bmp) 276 { 277 uint32_t reg; 278 int irq; 279 280 /* For the KVM GICv3, affinity routing is always enabled, and the 281 * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ 282 * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding 283 * functionality is replaced by the GICR registers. It doesn't need to sync 284 * them. So it should increase the offset and clroffset to skip GIC_INTERNAL 285 * irqs. This matches the for_each_dist_irq_reg() macro which also skips the 286 * first GIC_INTERNAL irqs. 287 */ 288 offset += (GIC_INTERNAL * 1) / 8; 289 if (clroffset != 0) { 290 clroffset += (GIC_INTERNAL * 1) / 8; 291 } 292 293 for_each_dist_irq_reg(irq, s->num_irq, 1) { 294 /* If this bitmap is a set/clear register pair, first write to the 295 * clear-reg to clear all bits before using the set-reg to write 296 * the 1 bits. 297 */ 298 if (clroffset != 0) { 299 reg = 0; 300 kvm_gicd_access(s, clroffset, ®, true); 301 clroffset += 4; 302 } 303 reg = *gic_bmp_ptr32(bmp, irq); 304 kvm_gicd_access(s, offset, ®, true); 305 offset += 4; 306 } 307 } 308 309 static void kvm_arm_gicv3_check(GICv3State *s) 310 { 311 uint32_t reg; 312 uint32_t num_irq; 313 314 /* Sanity checking s->num_irq */ 315 kvm_gicd_access(s, GICD_TYPER, ®, false); 316 num_irq = ((reg & 0x1f) + 1) * 32; 317 318 if (num_irq < s->num_irq) { 319 error_report("Model requests %u IRQs, but kernel supports max %u", 320 s->num_irq, num_irq); 321 abort(); 322 } 323 } 324 325 static void kvm_arm_gicv3_put(GICv3State *s) 326 { 327 uint32_t regl, regh, reg; 328 uint64_t reg64, redist_typer; 329 int ncpu, i; 330 331 kvm_arm_gicv3_check(s); 332 333 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 334 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 335 redist_typer = ((uint64_t)regh << 32) | regl; 336 337 reg = s->gicd_ctlr; 338 kvm_gicd_access(s, GICD_CTLR, ®, true); 339 340 if (redist_typer & GICR_TYPER_PLPIS) { 341 /* 342 * Restore base addresses before LPIs are potentially enabled by 343 * GICR_CTLR write 344 */ 345 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 346 GICv3CPUState *c = &s->cpu[ncpu]; 347 348 reg64 = c->gicr_propbaser; 349 regl = (uint32_t)reg64; 350 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, true); 351 regh = (uint32_t)(reg64 >> 32); 352 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, true); 353 354 reg64 = c->gicr_pendbaser; 355 regl = (uint32_t)reg64; 356 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, true); 357 regh = (uint32_t)(reg64 >> 32); 358 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, true); 359 } 360 } 361 362 /* Redistributor state (one per CPU) */ 363 364 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 365 GICv3CPUState *c = &s->cpu[ncpu]; 366 367 reg = c->gicr_ctlr; 368 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, true); 369 370 reg = c->gicr_statusr[GICV3_NS]; 371 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, true); 372 373 reg = c->gicr_waker; 374 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, true); 375 376 reg = c->gicr_igroupr0; 377 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, true); 378 379 reg = ~0; 380 kvm_gicr_access(s, GICR_ICENABLER0, ncpu, ®, true); 381 reg = c->gicr_ienabler0; 382 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, true); 383 384 /* Restore config before pending so we treat level/edge correctly */ 385 reg = half_shuffle32(c->edge_trigger >> 16) << 1; 386 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, true); 387 388 reg = c->level; 389 kvm_gic_line_level_access(s, 0, ncpu, ®, true); 390 391 reg = ~0; 392 kvm_gicr_access(s, GICR_ICPENDR0, ncpu, ®, true); 393 reg = c->gicr_ipendr0; 394 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, true); 395 396 reg = ~0; 397 kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, ®, true); 398 reg = c->gicr_iactiver0; 399 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); 400 401 for (i = 0; i < GIC_INTERNAL; i += 4) { 402 reg = c->gicr_ipriorityr[i] | 403 (c->gicr_ipriorityr[i + 1] << 8) | 404 (c->gicr_ipriorityr[i + 2] << 16) | 405 (c->gicr_ipriorityr[i + 3] << 24); 406 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, true); 407 } 408 } 409 410 /* Distributor state (shared between all CPUs */ 411 reg = s->gicd_statusr[GICV3_NS]; 412 kvm_gicd_access(s, GICD_STATUSR, ®, true); 413 414 /* s->enable bitmap -> GICD_ISENABLERn */ 415 kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled); 416 417 /* s->group bitmap -> GICD_IGROUPRn */ 418 kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group); 419 420 /* Restore targets before pending to ensure the pending state is set on 421 * the appropriate CPU interfaces in the kernel 422 */ 423 424 /* s->gicd_irouter[irq] -> GICD_IROUTERn 425 * We can't use kvm_dist_put() here because the registers are 64-bit 426 */ 427 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 428 uint32_t offset; 429 430 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 431 reg = (uint32_t)s->gicd_irouter[i]; 432 kvm_gicd_access(s, offset, ®, true); 433 434 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 435 reg = (uint32_t)(s->gicd_irouter[i] >> 32); 436 kvm_gicd_access(s, offset, ®, true); 437 } 438 439 /* s->trigger bitmap -> GICD_ICFGRn 440 * (restore configuration registers before pending IRQs so we treat 441 * level/edge correctly) 442 */ 443 kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 444 445 /* s->level bitmap -> line_level */ 446 kvm_gic_put_line_level_bmp(s, s->level); 447 448 /* s->pending bitmap -> GICD_ISPENDRn */ 449 kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending); 450 451 /* s->active bitmap -> GICD_ISACTIVERn */ 452 kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active); 453 454 /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */ 455 kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 456 457 /* CPU Interface state (one per CPU) */ 458 459 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 460 GICv3CPUState *c = &s->cpu[ncpu]; 461 int num_pri_bits; 462 463 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); 464 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 465 &c->icc_ctlr_el1[GICV3_NS], true); 466 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 467 &c->icc_igrpen[GICV3_G0], true); 468 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 469 &c->icc_igrpen[GICV3_G1NS], true); 470 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true); 471 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true); 472 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true); 473 474 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 475 ICC_CTLR_EL1_PRIBITS_MASK) >> 476 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 477 478 switch (num_pri_bits) { 479 case 7: 480 reg64 = c->icc_apr[GICV3_G0][3]; 481 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, true); 482 reg64 = c->icc_apr[GICV3_G0][2]; 483 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, true); 484 case 6: 485 reg64 = c->icc_apr[GICV3_G0][1]; 486 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, true); 487 default: 488 reg64 = c->icc_apr[GICV3_G0][0]; 489 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, true); 490 } 491 492 switch (num_pri_bits) { 493 case 7: 494 reg64 = c->icc_apr[GICV3_G1NS][3]; 495 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, true); 496 reg64 = c->icc_apr[GICV3_G1NS][2]; 497 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, true); 498 case 6: 499 reg64 = c->icc_apr[GICV3_G1NS][1]; 500 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, true); 501 default: 502 reg64 = c->icc_apr[GICV3_G1NS][0]; 503 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, true); 504 } 505 } 506 } 507 508 static void kvm_arm_gicv3_get(GICv3State *s) 509 { 510 uint32_t regl, regh, reg; 511 uint64_t reg64, redist_typer; 512 int ncpu, i; 513 514 kvm_arm_gicv3_check(s); 515 516 kvm_gicr_access(s, GICR_TYPER, 0, ®l, false); 517 kvm_gicr_access(s, GICR_TYPER + 4, 0, ®h, false); 518 redist_typer = ((uint64_t)regh << 32) | regl; 519 520 kvm_gicd_access(s, GICD_CTLR, ®, false); 521 s->gicd_ctlr = reg; 522 523 /* Redistributor state (one per CPU) */ 524 525 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 526 GICv3CPUState *c = &s->cpu[ncpu]; 527 528 kvm_gicr_access(s, GICR_CTLR, ncpu, ®, false); 529 c->gicr_ctlr = reg; 530 531 kvm_gicr_access(s, GICR_STATUSR, ncpu, ®, false); 532 c->gicr_statusr[GICV3_NS] = reg; 533 534 kvm_gicr_access(s, GICR_WAKER, ncpu, ®, false); 535 c->gicr_waker = reg; 536 537 kvm_gicr_access(s, GICR_IGROUPR0, ncpu, ®, false); 538 c->gicr_igroupr0 = reg; 539 kvm_gicr_access(s, GICR_ISENABLER0, ncpu, ®, false); 540 c->gicr_ienabler0 = reg; 541 kvm_gicr_access(s, GICR_ICFGR1, ncpu, ®, false); 542 c->edge_trigger = half_unshuffle32(reg >> 1) << 16; 543 kvm_gic_line_level_access(s, 0, ncpu, ®, false); 544 c->level = reg; 545 kvm_gicr_access(s, GICR_ISPENDR0, ncpu, ®, false); 546 c->gicr_ipendr0 = reg; 547 kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); 548 c->gicr_iactiver0 = reg; 549 550 for (i = 0; i < GIC_INTERNAL; i += 4) { 551 kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); 552 c->gicr_ipriorityr[i] = extract32(reg, 0, 8); 553 c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8); 554 c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8); 555 c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8); 556 } 557 } 558 559 if (redist_typer & GICR_TYPER_PLPIS) { 560 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 561 GICv3CPUState *c = &s->cpu[ncpu]; 562 563 kvm_gicr_access(s, GICR_PROPBASER, ncpu, ®l, false); 564 kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, ®h, false); 565 c->gicr_propbaser = ((uint64_t)regh << 32) | regl; 566 567 kvm_gicr_access(s, GICR_PENDBASER, ncpu, ®l, false); 568 kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, ®h, false); 569 c->gicr_pendbaser = ((uint64_t)regh << 32) | regl; 570 } 571 } 572 573 /* Distributor state (shared between all CPUs */ 574 575 kvm_gicd_access(s, GICD_STATUSR, ®, false); 576 s->gicd_statusr[GICV3_NS] = reg; 577 578 /* GICD_IGROUPRn -> s->group bitmap */ 579 kvm_dist_getbmp(s, GICD_IGROUPR, s->group); 580 581 /* GICD_ISENABLERn -> s->enabled bitmap */ 582 kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled); 583 584 /* Line level of irq */ 585 kvm_gic_get_line_level_bmp(s, s->level); 586 /* GICD_ISPENDRn -> s->pending bitmap */ 587 kvm_dist_getbmp(s, GICD_ISPENDR, s->pending); 588 589 /* GICD_ISACTIVERn -> s->active bitmap */ 590 kvm_dist_getbmp(s, GICD_ISACTIVER, s->active); 591 592 /* GICD_ICFGRn -> s->trigger bitmap */ 593 kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger); 594 595 /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */ 596 kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority); 597 598 /* GICD_IROUTERn -> s->gicd_irouter[irq] */ 599 for (i = GIC_INTERNAL; i < s->num_irq; i++) { 600 uint32_t offset; 601 602 offset = GICD_IROUTER + (sizeof(uint32_t) * i); 603 kvm_gicd_access(s, offset, ®l, false); 604 offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4; 605 kvm_gicd_access(s, offset, ®h, false); 606 s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl; 607 } 608 609 /***************************************************************** 610 * CPU Interface(s) State 611 */ 612 613 for (ncpu = 0; ncpu < s->num_cpu; ncpu++) { 614 GICv3CPUState *c = &s->cpu[ncpu]; 615 int num_pri_bits; 616 617 kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); 618 kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, 619 &c->icc_ctlr_el1[GICV3_NS], false); 620 kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, 621 &c->icc_igrpen[GICV3_G0], false); 622 kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, 623 &c->icc_igrpen[GICV3_G1NS], false); 624 kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false); 625 kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false); 626 kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false); 627 num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] & 628 ICC_CTLR_EL1_PRIBITS_MASK) >> 629 ICC_CTLR_EL1_PRIBITS_SHIFT) + 1; 630 631 switch (num_pri_bits) { 632 case 7: 633 kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, ®64, false); 634 c->icc_apr[GICV3_G0][3] = reg64; 635 kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, ®64, false); 636 c->icc_apr[GICV3_G0][2] = reg64; 637 case 6: 638 kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, ®64, false); 639 c->icc_apr[GICV3_G0][1] = reg64; 640 default: 641 kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, ®64, false); 642 c->icc_apr[GICV3_G0][0] = reg64; 643 } 644 645 switch (num_pri_bits) { 646 case 7: 647 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, ®64, false); 648 c->icc_apr[GICV3_G1NS][3] = reg64; 649 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, ®64, false); 650 c->icc_apr[GICV3_G1NS][2] = reg64; 651 case 6: 652 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, ®64, false); 653 c->icc_apr[GICV3_G1NS][1] = reg64; 654 default: 655 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, ®64, false); 656 c->icc_apr[GICV3_G1NS][0] = reg64; 657 } 658 } 659 } 660 661 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) 662 { 663 GICv3State *s; 664 GICv3CPUState *c; 665 666 c = (GICv3CPUState *)env->gicv3state; 667 s = c->gic; 668 669 c->icc_pmr_el1 = 0; 670 c->icc_bpr[GICV3_G0] = GIC_MIN_BPR; 671 c->icc_bpr[GICV3_G1] = GIC_MIN_BPR; 672 c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR; 673 674 c->icc_sre_el1 = 0x7; 675 memset(c->icc_apr, 0, sizeof(c->icc_apr)); 676 memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); 677 678 if (s->migration_blocker) { 679 return; 680 } 681 682 /* Initialize to actual HW supported configuration */ 683 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, 684 KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), 685 &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); 686 687 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; 688 } 689 690 static void kvm_arm_gicv3_reset(DeviceState *dev) 691 { 692 GICv3State *s = ARM_GICV3_COMMON(dev); 693 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 694 695 DPRINTF("Reset\n"); 696 697 kgc->parent_reset(dev); 698 699 if (s->migration_blocker) { 700 DPRINTF("Cannot put kernel gic state, no kernel interface\n"); 701 return; 702 } 703 704 kvm_arm_gicv3_put(s); 705 } 706 707 /* 708 * CPU interface registers of GIC needs to be reset on CPU reset. 709 * For the calling arm_gicv3_icc_reset() on CPU reset, we register 710 * below ARMCPRegInfo. As we reset the whole cpu interface under single 711 * register reset, we define only one register of CPU interface instead 712 * of defining all the registers. 713 */ 714 static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { 715 { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH, 716 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, 717 /* 718 * If ARM_CP_NOP is used, resetfn is not called, 719 * So ARM_CP_NO_RAW is appropriate type. 720 */ 721 .type = ARM_CP_NO_RAW, 722 .access = PL1_RW, 723 .readfn = arm_cp_read_zero, 724 .writefn = arm_cp_write_ignore, 725 /* 726 * We hang the whole cpu interface reset routine off here 727 * rather than parcelling it out into one little function 728 * per register 729 */ 730 .resetfn = arm_gicv3_icc_reset, 731 }, 732 REGINFO_SENTINEL 733 }; 734 735 /** 736 * vm_change_state_handler - VM change state callback aiming at flushing 737 * RDIST pending tables into guest RAM 738 * 739 * The tables get flushed to guest RAM whenever the VM gets stopped. 740 */ 741 static void vm_change_state_handler(void *opaque, int running, 742 RunState state) 743 { 744 GICv3State *s = (GICv3State *)opaque; 745 Error *err = NULL; 746 int ret; 747 748 if (running) { 749 return; 750 } 751 752 ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 753 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, 754 NULL, true, &err); 755 if (err) { 756 error_report_err(err); 757 } 758 if (ret < 0 && ret != -EFAULT) { 759 abort(); 760 } 761 } 762 763 764 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) 765 { 766 GICv3State *s = KVM_ARM_GICV3(dev); 767 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); 768 bool multiple_redist_region_allowed; 769 Error *local_err = NULL; 770 int i; 771 772 DPRINTF("kvm_arm_gicv3_realize\n"); 773 774 kgc->parent_realize(dev, &local_err); 775 if (local_err) { 776 error_propagate(errp, local_err); 777 return; 778 } 779 780 if (s->security_extn) { 781 error_setg(errp, "the in-kernel VGICv3 does not implement the " 782 "security extensions"); 783 return; 784 } 785 786 gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err); 787 if (local_err) { 788 error_propagate(errp, local_err); 789 return; 790 } 791 792 for (i = 0; i < s->num_cpu; i++) { 793 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i)); 794 795 define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); 796 } 797 798 /* Try to create the device via the device control API */ 799 s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false); 800 if (s->dev_fd < 0) { 801 error_setg_errno(errp, -s->dev_fd, "error creating in-kernel VGIC"); 802 return; 803 } 804 805 multiple_redist_region_allowed = 806 kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, 807 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); 808 809 if (!multiple_redist_region_allowed && s->nb_redist_regions > 1) { 810 error_setg(errp, "Multiple VGICv3 redistributor regions are not " 811 "supported by this host kernel"); 812 error_append_hint(errp, "A maximum of %d VCPUs can be used", 813 s->redist_region_count[0]); 814 return; 815 } 816 817 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 818 0, &s->num_irq, true, &error_abort); 819 820 /* Tell the kernel to complete VGIC initialization now */ 821 kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 822 KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); 823 824 kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, 825 KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); 826 827 if (!multiple_redist_region_allowed) { 828 kvm_arm_register_device(&s->iomem_redist[0], -1, 829 KVM_DEV_ARM_VGIC_GRP_ADDR, 830 KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0); 831 } else { 832 /* we register regions in reverse order as "devices" are inserted at 833 * the head of a QSLIST and the list is then popped from the head 834 * onwards by kvm_arm_machine_init_done() 835 */ 836 for (i = s->nb_redist_regions - 1; i >= 0; i--) { 837 /* Address mask made of the rdist region index and count */ 838 uint64_t addr_ormask = 839 i | ((uint64_t)s->redist_region_count[i] << 52); 840 841 kvm_arm_register_device(&s->iomem_redist[i], -1, 842 KVM_DEV_ARM_VGIC_GRP_ADDR, 843 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION, 844 s->dev_fd, addr_ormask); 845 } 846 } 847 848 if (kvm_has_gsi_routing()) { 849 /* set up irq routing */ 850 for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { 851 kvm_irqchip_add_irq_route(kvm_state, i, 0, i); 852 } 853 854 kvm_gsi_routing_allowed = true; 855 856 kvm_irqchip_commit_routes(kvm_state); 857 } 858 859 if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 860 GICD_CTLR)) { 861 error_setg(&s->migration_blocker, "This operating system kernel does " 862 "not support vGICv3 migration"); 863 if (migrate_add_blocker(s->migration_blocker, errp) < 0) { 864 error_free(s->migration_blocker); 865 return; 866 } 867 } 868 if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, 869 KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { 870 qemu_add_vm_change_state_handler(vm_change_state_handler, s); 871 } 872 } 873 874 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) 875 { 876 DeviceClass *dc = DEVICE_CLASS(klass); 877 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); 878 KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); 879 880 agcc->pre_save = kvm_arm_gicv3_get; 881 agcc->post_load = kvm_arm_gicv3_put; 882 device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, 883 &kgc->parent_realize); 884 device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); 885 } 886 887 static const TypeInfo kvm_arm_gicv3_info = { 888 .name = TYPE_KVM_ARM_GICV3, 889 .parent = TYPE_ARM_GICV3_COMMON, 890 .instance_size = sizeof(GICv3State), 891 .class_init = kvm_arm_gicv3_class_init, 892 .class_size = sizeof(KVMARMGICv3Class), 893 }; 894 895 static void kvm_arm_gicv3_register_types(void) 896 { 897 type_register_static(&kvm_arm_gicv3_info); 898 } 899 900 type_init(kvm_arm_gicv3_register_types) 901