1 /* 2 * QEMU VMWARE PVSCSI paravirtual SCSI bus 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Based on implementation by Paolo Bonzini 9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html 10 * 11 * Authors: 12 * Paolo Bonzini <pbonzini@redhat.com> 13 * Dmitry Fleytman <dmitry@daynix.com> 14 * Yan Vugenfirer <yan@daynix.com> 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. 17 * See the COPYING file in the top-level directory. 18 * 19 * NOTE about MSI-X: 20 * MSI-X support has been removed for the moment because it leads Windows OS 21 * to crash on startup. The crash happens because Windows driver requires 22 * MSI-X shared memory to be part of the same BAR used for rings state 23 * registers, etc. This is not supported by QEMU infrastructure so separate 24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "qemu/main-loop.h" 31 #include "qemu/module.h" 32 #include "hw/scsi/scsi.h" 33 #include "migration/vmstate.h" 34 #include "scsi/constants.h" 35 #include "hw/pci/msi.h" 36 #include "hw/qdev-properties.h" 37 #include "vmw_pvscsi.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 41 42 #define PVSCSI_USE_64BIT (true) 43 #define PVSCSI_PER_VECTOR_MASK (false) 44 45 #define PVSCSI_MAX_DEVS (64) 46 #define PVSCSI_MSIX_NUM_VECTORS (1) 47 48 #define PVSCSI_MAX_SG_ELEM 2048 49 50 #define PVSCSI_MAX_CMD_DATA_WORDS \ 51 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) 52 53 #define RS_GET_FIELD(m, field) \ 54 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ 55 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field))) 56 #define RS_SET_FIELD(m, field, val) \ 57 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ 58 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val)) 59 60 struct PVSCSIClass { 61 PCIDeviceClass parent_class; 62 DeviceRealize parent_dc_realize; 63 }; 64 typedef struct PVSCSIClass PVSCSIClass; 65 66 #define TYPE_PVSCSI "pvscsi" 67 typedef struct PVSCSIState PVSCSIState; 68 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI) 69 70 #define PVSCSI_CLASS(klass) \ 71 OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI) 72 #define PVSCSI_GET_CLASS(obj) \ 73 OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI) 74 75 /* Compatibility flags for migration */ 76 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0 77 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \ 78 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT) 79 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1 80 #define PVSCSI_COMPAT_DISABLE_PCIE \ 81 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT) 82 83 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \ 84 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION) 85 #define PVSCSI_MSI_OFFSET(s) \ 86 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c) 87 #define PVSCSI_EXP_EP_OFFSET (0x40) 88 89 typedef struct PVSCSIRingInfo { 90 uint64_t rs_pa; 91 uint32_t txr_len_mask; 92 uint32_t rxr_len_mask; 93 uint32_t msg_len_mask; 94 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 95 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 96 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES]; 97 uint64_t consumed_ptr; 98 uint64_t filled_cmp_ptr; 99 uint64_t filled_msg_ptr; 100 } PVSCSIRingInfo; 101 102 typedef struct PVSCSISGState { 103 hwaddr elemAddr; 104 hwaddr dataAddr; 105 uint32_t resid; 106 } PVSCSISGState; 107 108 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList; 109 110 struct PVSCSIState { 111 PCIDevice parent_obj; 112 MemoryRegion io_space; 113 SCSIBus bus; 114 QEMUBH *completion_worker; 115 PVSCSIRequestList pending_queue; 116 PVSCSIRequestList completion_queue; 117 118 uint64_t reg_interrupt_status; /* Interrupt status register value */ 119 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */ 120 uint64_t reg_command_status; /* Command status register value */ 121 122 /* Command data adoption mechanism */ 123 uint64_t curr_cmd; /* Last command arrived */ 124 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */ 125 126 /* Collector for current command data */ 127 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS]; 128 129 uint8_t rings_info_valid; /* Whether data rings initialized */ 130 uint8_t msg_ring_info_valid; /* Whether message ring initialized */ 131 uint8_t use_msg; /* Whether to use message ring */ 132 133 uint8_t msi_used; /* For migration compatibility */ 134 PVSCSIRingInfo rings; /* Data transfer rings manager */ 135 uint32_t resetting; /* Reset in progress */ 136 137 uint32_t compat_flags; 138 }; 139 140 typedef struct PVSCSIRequest { 141 SCSIRequest *sreq; 142 PVSCSIState *dev; 143 uint8_t sense_key; 144 uint8_t completed; 145 int lun; 146 QEMUSGList sgl; 147 PVSCSISGState sg; 148 struct PVSCSIRingReqDesc req; 149 struct PVSCSIRingCmpDesc cmp; 150 QTAILQ_ENTRY(PVSCSIRequest) next; 151 } PVSCSIRequest; 152 153 /* Integer binary logarithm */ 154 static int 155 pvscsi_log2(uint32_t input) 156 { 157 int log = 0; 158 assert(input > 0); 159 while (input >> ++log) { 160 } 161 return log; 162 } 163 164 static void 165 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri) 166 { 167 int i; 168 uint32_t txr_len_log2, rxr_len_log2; 169 uint32_t req_ring_size, cmp_ring_size; 170 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT; 171 172 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 173 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 174 txr_len_log2 = pvscsi_log2(req_ring_size - 1); 175 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1); 176 177 m->txr_len_mask = MASK(txr_len_log2); 178 m->rxr_len_mask = MASK(rxr_len_log2); 179 180 m->consumed_ptr = 0; 181 m->filled_cmp_ptr = 0; 182 183 for (i = 0; i < ri->reqRingNumPages; i++) { 184 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT; 185 } 186 187 for (i = 0; i < ri->cmpRingNumPages; i++) { 188 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT; 189 } 190 191 RS_SET_FIELD(m, reqProdIdx, 0); 192 RS_SET_FIELD(m, reqConsIdx, 0); 193 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2); 194 195 RS_SET_FIELD(m, cmpProdIdx, 0); 196 RS_SET_FIELD(m, cmpConsIdx, 0); 197 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2); 198 199 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2); 200 201 /* Flush ring state page changes */ 202 smp_wmb(); 203 } 204 205 static int 206 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri) 207 { 208 int i; 209 uint32_t len_log2; 210 uint32_t ring_size; 211 212 if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) { 213 return -1; 214 } 215 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 216 len_log2 = pvscsi_log2(ring_size - 1); 217 218 m->msg_len_mask = MASK(len_log2); 219 220 m->filled_msg_ptr = 0; 221 222 for (i = 0; i < ri->numPages; i++) { 223 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT; 224 } 225 226 RS_SET_FIELD(m, msgProdIdx, 0); 227 RS_SET_FIELD(m, msgConsIdx, 0); 228 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2); 229 230 trace_pvscsi_ring_init_msg(len_log2); 231 232 /* Flush ring state page changes */ 233 smp_wmb(); 234 235 return 0; 236 } 237 238 static void 239 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) 240 { 241 mgr->rs_pa = 0; 242 mgr->txr_len_mask = 0; 243 mgr->rxr_len_mask = 0; 244 mgr->msg_len_mask = 0; 245 mgr->consumed_ptr = 0; 246 mgr->filled_cmp_ptr = 0; 247 mgr->filled_msg_ptr = 0; 248 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa)); 249 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa)); 250 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa)); 251 } 252 253 static hwaddr 254 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) 255 { 256 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx); 257 uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING 258 * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 259 260 if (ready_ptr != mgr->consumed_ptr 261 && ready_ptr - mgr->consumed_ptr < ring_size) { 262 uint32_t next_ready_ptr = 263 mgr->consumed_ptr++ & mgr->txr_len_mask; 264 uint32_t next_ready_page = 265 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 266 uint32_t inpage_idx = 267 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 268 269 return mgr->req_ring_pages_pa[next_ready_page] + 270 inpage_idx * sizeof(PVSCSIRingReqDesc); 271 } else { 272 return 0; 273 } 274 } 275 276 static void 277 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr) 278 { 279 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr); 280 } 281 282 static hwaddr 283 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr) 284 { 285 /* 286 * According to Linux driver code it explicitly verifies that number 287 * of requests being processed by device is less then the size of 288 * completion queue, so device may omit completion queue overflow 289 * conditions check. We assume that this is true for other (Windows) 290 * drivers as well. 291 */ 292 293 uint32_t free_cmp_ptr = 294 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask; 295 uint32_t free_cmp_page = 296 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 297 uint32_t inpage_idx = 298 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 299 return mgr->cmp_ring_pages_pa[free_cmp_page] + 300 inpage_idx * sizeof(PVSCSIRingCmpDesc); 301 } 302 303 static hwaddr 304 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr) 305 { 306 uint32_t free_msg_ptr = 307 mgr->filled_msg_ptr++ & mgr->msg_len_mask; 308 uint32_t free_msg_page = 309 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 310 uint32_t inpage_idx = 311 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 312 return mgr->msg_ring_pages_pa[free_msg_page] + 313 inpage_idx * sizeof(PVSCSIRingMsgDesc); 314 } 315 316 static void 317 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) 318 { 319 /* Flush descriptor changes */ 320 smp_wmb(); 321 322 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr); 323 324 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr); 325 } 326 327 static bool 328 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) 329 { 330 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx); 331 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx); 332 333 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); 334 } 335 336 static void 337 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr) 338 { 339 /* Flush descriptor changes */ 340 smp_wmb(); 341 342 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr); 343 344 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr); 345 } 346 347 static void 348 pvscsi_reset_state(PVSCSIState *s) 349 { 350 s->curr_cmd = PVSCSI_CMD_FIRST; 351 s->curr_cmd_data_cntr = 0; 352 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 353 s->reg_interrupt_status = 0; 354 pvscsi_ring_cleanup(&s->rings); 355 s->rings_info_valid = FALSE; 356 s->msg_ring_info_valid = FALSE; 357 QTAILQ_INIT(&s->pending_queue); 358 QTAILQ_INIT(&s->completion_queue); 359 } 360 361 static void 362 pvscsi_update_irq_status(PVSCSIState *s) 363 { 364 PCIDevice *d = PCI_DEVICE(s); 365 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status; 366 367 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled, 368 s->reg_interrupt_status); 369 370 if (msi_enabled(d)) { 371 if (should_raise) { 372 trace_pvscsi_update_irq_msi(); 373 msi_notify(d, PVSCSI_VECTOR_COMPLETION); 374 } 375 return; 376 } 377 378 pci_set_irq(d, !!should_raise); 379 } 380 381 static void 382 pvscsi_raise_completion_interrupt(PVSCSIState *s) 383 { 384 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0; 385 386 /* Memory barrier to flush interrupt status register changes*/ 387 smp_wmb(); 388 389 pvscsi_update_irq_status(s); 390 } 391 392 static void 393 pvscsi_raise_message_interrupt(PVSCSIState *s) 394 { 395 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0; 396 397 /* Memory barrier to flush interrupt status register changes*/ 398 smp_wmb(); 399 400 pvscsi_update_irq_status(s); 401 } 402 403 static void 404 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) 405 { 406 hwaddr cmp_descr_pa; 407 408 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); 409 trace_pvscsi_cmp_ring_put(cmp_descr_pa); 410 cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); 411 } 412 413 static void 414 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) 415 { 416 hwaddr msg_descr_pa; 417 418 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); 419 trace_pvscsi_msg_ring_put(msg_descr_pa); 420 cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); 421 } 422 423 static void 424 pvscsi_process_completion_queue(void *opaque) 425 { 426 PVSCSIState *s = opaque; 427 PVSCSIRequest *pvscsi_req; 428 bool has_completed = false; 429 430 while (!QTAILQ_EMPTY(&s->completion_queue)) { 431 pvscsi_req = QTAILQ_FIRST(&s->completion_queue); 432 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); 433 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); 434 g_free(pvscsi_req); 435 has_completed = true; 436 } 437 438 if (has_completed) { 439 pvscsi_ring_flush_cmp(&s->rings); 440 pvscsi_raise_completion_interrupt(s); 441 } 442 } 443 444 static void 445 pvscsi_reset_adapter(PVSCSIState *s) 446 { 447 s->resetting++; 448 qbus_reset_all(BUS(&s->bus)); 449 s->resetting--; 450 pvscsi_process_completion_queue(s); 451 assert(QTAILQ_EMPTY(&s->pending_queue)); 452 pvscsi_reset_state(s); 453 } 454 455 static void 456 pvscsi_schedule_completion_processing(PVSCSIState *s) 457 { 458 /* Try putting more complete requests on the ring. */ 459 if (!QTAILQ_EMPTY(&s->completion_queue)) { 460 qemu_bh_schedule(s->completion_worker); 461 } 462 } 463 464 static void 465 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r) 466 { 467 assert(!r->completed); 468 469 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen, 470 r->sense_key); 471 if (r->sreq != NULL) { 472 scsi_req_unref(r->sreq); 473 r->sreq = NULL; 474 } 475 r->completed = 1; 476 QTAILQ_REMOVE(&s->pending_queue, r, next); 477 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next); 478 pvscsi_schedule_completion_processing(s); 479 } 480 481 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r) 482 { 483 PVSCSIRequest *req = r->hba_private; 484 485 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size); 486 487 return &req->sgl; 488 } 489 490 static void 491 pvscsi_get_next_sg_elem(PVSCSISGState *sg) 492 { 493 struct PVSCSISGElement elem; 494 495 cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); 496 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { 497 /* 498 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in 499 * header file but its value is unknown. This flag requires 500 * additional processing, so we put warning here to catch it 501 * some day and make proper implementation 502 */ 503 trace_pvscsi_get_next_sg_elem(elem.flags); 504 } 505 506 sg->elemAddr += sizeof(elem); 507 sg->dataAddr = elem.addr; 508 sg->resid = elem.length; 509 } 510 511 static void 512 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len) 513 { 514 r->cmp.senseLen = MIN(r->req.senseLen, len); 515 r->sense_key = sense[(sense[0] & 2) ? 1 : 2]; 516 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen); 517 } 518 519 static void 520 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid) 521 { 522 PVSCSIRequest *pvscsi_req = req->hba_private; 523 PVSCSIState *s; 524 525 if (!pvscsi_req) { 526 trace_pvscsi_command_complete_not_found(req->tag); 527 return; 528 } 529 s = pvscsi_req->dev; 530 531 if (resid) { 532 /* Short transfer. */ 533 trace_pvscsi_command_complete_data_run(); 534 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN; 535 } 536 537 pvscsi_req->cmp.scsiStatus = status; 538 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) { 539 uint8_t sense[SCSI_SENSE_BUF_SIZE]; 540 int sense_len = 541 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense)); 542 543 trace_pvscsi_command_complete_sense_len(sense_len); 544 pvscsi_write_sense(pvscsi_req, sense, sense_len); 545 } 546 qemu_sglist_destroy(&pvscsi_req->sgl); 547 pvscsi_complete_request(s, pvscsi_req); 548 } 549 550 static void 551 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type) 552 { 553 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { 554 PVSCSIMsgDescDevStatusChanged msg = {0}; 555 556 msg.type = msg_type; 557 msg.bus = dev->channel; 558 msg.target = dev->id; 559 msg.lun[1] = dev->lun; 560 561 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg); 562 pvscsi_ring_flush_msg(&s->rings); 563 pvscsi_raise_message_interrupt(s); 564 } 565 } 566 567 static void 568 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) 569 { 570 PVSCSIState *s = PVSCSI(hotplug_dev); 571 572 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED); 573 } 574 575 static void 576 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) 577 { 578 PVSCSIState *s = PVSCSI(hotplug_dev); 579 580 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED); 581 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp); 582 } 583 584 static void 585 pvscsi_request_cancelled(SCSIRequest *req) 586 { 587 PVSCSIRequest *pvscsi_req = req->hba_private; 588 PVSCSIState *s = pvscsi_req->dev; 589 590 if (pvscsi_req->completed) { 591 return; 592 } 593 594 if (pvscsi_req->dev->resetting) { 595 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 596 } else { 597 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 598 } 599 600 pvscsi_complete_request(s, pvscsi_req); 601 } 602 603 static SCSIDevice* 604 pvscsi_device_find(PVSCSIState *s, int channel, int target, 605 uint8_t *requested_lun, uint8_t *target_lun) 606 { 607 if (requested_lun[0] || requested_lun[2] || requested_lun[3] || 608 requested_lun[4] || requested_lun[5] || requested_lun[6] || 609 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) { 610 return NULL; 611 } else { 612 *target_lun = requested_lun[1]; 613 return scsi_device_find(&s->bus, channel, target, *target_lun); 614 } 615 } 616 617 static PVSCSIRequest * 618 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d, 619 struct PVSCSIRingReqDesc *descr) 620 { 621 PVSCSIRequest *pvscsi_req; 622 uint8_t lun; 623 624 pvscsi_req = g_malloc0(sizeof(*pvscsi_req)); 625 pvscsi_req->dev = s; 626 pvscsi_req->req = *descr; 627 pvscsi_req->cmp.context = pvscsi_req->req.context; 628 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next); 629 630 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun); 631 if (*d) { 632 pvscsi_req->lun = lun; 633 } 634 635 return pvscsi_req; 636 } 637 638 static void 639 pvscsi_convert_sglist(PVSCSIRequest *r) 640 { 641 uint32_t chunk_size, elmcnt = 0; 642 uint64_t data_length = r->req.dataLen; 643 PVSCSISGState sg = r->sg; 644 while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) { 645 while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) { 646 pvscsi_get_next_sg_elem(&sg); 647 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr, 648 r->sg.resid); 649 } 650 chunk_size = MIN(data_length, sg.resid); 651 if (chunk_size) { 652 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size); 653 } 654 655 sg.dataAddr += chunk_size; 656 data_length -= chunk_size; 657 sg.resid -= chunk_size; 658 } 659 } 660 661 static void 662 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r) 663 { 664 PCIDevice *d = PCI_DEVICE(s); 665 666 pci_dma_sglist_init(&r->sgl, d, 1); 667 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 668 pvscsi_convert_sglist(r); 669 } else { 670 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen); 671 } 672 } 673 674 static void 675 pvscsi_process_request_descriptor(PVSCSIState *s, 676 struct PVSCSIRingReqDesc *descr) 677 { 678 SCSIDevice *d; 679 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr); 680 int64_t n; 681 682 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context); 683 684 if (!d) { 685 r->cmp.hostStatus = BTSTAT_SELTIMEO; 686 trace_pvscsi_process_req_descr_unknown_device(); 687 pvscsi_complete_request(s, r); 688 return; 689 } 690 691 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 692 r->sg.elemAddr = descr->dataAddr; 693 } 694 695 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r); 696 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV && 697 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) { 698 r->cmp.hostStatus = BTSTAT_BADMSG; 699 trace_pvscsi_process_req_descr_invalid_dir(); 700 scsi_req_cancel(r->sreq); 701 return; 702 } 703 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV && 704 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) { 705 r->cmp.hostStatus = BTSTAT_BADMSG; 706 trace_pvscsi_process_req_descr_invalid_dir(); 707 scsi_req_cancel(r->sreq); 708 return; 709 } 710 711 pvscsi_build_sglist(s, r); 712 n = scsi_req_enqueue(r->sreq); 713 714 if (n) { 715 scsi_req_continue(r->sreq); 716 } 717 } 718 719 static void 720 pvscsi_process_io(PVSCSIState *s) 721 { 722 PVSCSIRingReqDesc descr; 723 hwaddr next_descr_pa; 724 725 if (!s->rings_info_valid) { 726 return; 727 } 728 729 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { 730 731 /* Only read after production index verification */ 732 smp_rmb(); 733 734 trace_pvscsi_process_io(next_descr_pa); 735 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr)); 736 pvscsi_process_request_descriptor(s, &descr); 737 } 738 739 pvscsi_ring_flush_req(&s->rings); 740 } 741 742 static void 743 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc) 744 { 745 int i; 746 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN); 747 748 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages); 749 for (i = 0; i < rc->reqRingNumPages; i++) { 750 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]); 751 } 752 753 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages); 754 for (i = 0; i < rc->cmpRingNumPages; i++) { 755 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]); 756 } 757 } 758 759 static uint64_t 760 pvscsi_on_cmd_config(PVSCSIState *s) 761 { 762 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG"); 763 return PVSCSI_COMMAND_PROCESSING_FAILED; 764 } 765 766 static uint64_t 767 pvscsi_on_cmd_unplug(PVSCSIState *s) 768 { 769 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG"); 770 return PVSCSI_COMMAND_PROCESSING_FAILED; 771 } 772 773 static uint64_t 774 pvscsi_on_issue_scsi(PVSCSIState *s) 775 { 776 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI"); 777 return PVSCSI_COMMAND_PROCESSING_FAILED; 778 } 779 780 static uint64_t 781 pvscsi_on_cmd_setup_rings(PVSCSIState *s) 782 { 783 PVSCSICmdDescSetupRings *rc = 784 (PVSCSICmdDescSetupRings *) s->curr_cmd_data; 785 786 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS"); 787 788 if (!rc->reqRingNumPages 789 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES 790 || !rc->cmpRingNumPages 791 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) { 792 return PVSCSI_COMMAND_PROCESSING_FAILED; 793 } 794 795 pvscsi_dbg_dump_tx_rings_config(rc); 796 pvscsi_ring_init_data(&s->rings, rc); 797 798 s->rings_info_valid = TRUE; 799 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 800 } 801 802 static uint64_t 803 pvscsi_on_cmd_abort(PVSCSIState *s) 804 { 805 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data; 806 PVSCSIRequest *r, *next; 807 808 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target); 809 810 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) { 811 if (r->req.context == cmd->context) { 812 break; 813 } 814 } 815 if (r) { 816 assert(!r->completed); 817 r->cmp.hostStatus = BTSTAT_ABORTQUEUE; 818 scsi_req_cancel(r->sreq); 819 } 820 821 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 822 } 823 824 static uint64_t 825 pvscsi_on_cmd_unknown(PVSCSIState *s) 826 { 827 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]); 828 return PVSCSI_COMMAND_PROCESSING_FAILED; 829 } 830 831 static uint64_t 832 pvscsi_on_cmd_reset_device(PVSCSIState *s) 833 { 834 uint8_t target_lun = 0; 835 struct PVSCSICmdDescResetDevice *cmd = 836 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data; 837 SCSIDevice *sdev; 838 839 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun); 840 841 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev); 842 843 if (sdev != NULL) { 844 s->resetting++; 845 device_legacy_reset(&sdev->qdev); 846 s->resetting--; 847 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 848 } 849 850 return PVSCSI_COMMAND_PROCESSING_FAILED; 851 } 852 853 static uint64_t 854 pvscsi_on_cmd_reset_bus(PVSCSIState *s) 855 { 856 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS"); 857 858 s->resetting++; 859 qbus_reset_all(BUS(&s->bus)); 860 s->resetting--; 861 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 862 } 863 864 static uint64_t 865 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s) 866 { 867 PVSCSICmdDescSetupMsgRing *rc = 868 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data; 869 870 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING"); 871 872 if (!s->use_msg) { 873 return PVSCSI_COMMAND_PROCESSING_FAILED; 874 } 875 876 if (s->rings_info_valid) { 877 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) { 878 return PVSCSI_COMMAND_PROCESSING_FAILED; 879 } 880 s->msg_ring_info_valid = TRUE; 881 } 882 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t); 883 } 884 885 static uint64_t 886 pvscsi_on_cmd_adapter_reset(PVSCSIState *s) 887 { 888 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET"); 889 890 pvscsi_reset_adapter(s); 891 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 892 } 893 894 static const struct { 895 int data_size; 896 uint64_t (*handler_fn)(PVSCSIState *s); 897 } pvscsi_commands[] = { 898 [PVSCSI_CMD_FIRST] = { 899 .data_size = 0, 900 .handler_fn = pvscsi_on_cmd_unknown, 901 }, 902 903 /* Not implemented, data size defined based on what arrives on windows */ 904 [PVSCSI_CMD_CONFIG] = { 905 .data_size = 6 * sizeof(uint32_t), 906 .handler_fn = pvscsi_on_cmd_config, 907 }, 908 909 /* Command not implemented, data size is unknown */ 910 [PVSCSI_CMD_ISSUE_SCSI] = { 911 .data_size = 0, 912 .handler_fn = pvscsi_on_issue_scsi, 913 }, 914 915 /* Command not implemented, data size is unknown */ 916 [PVSCSI_CMD_DEVICE_UNPLUG] = { 917 .data_size = 0, 918 .handler_fn = pvscsi_on_cmd_unplug, 919 }, 920 921 [PVSCSI_CMD_SETUP_RINGS] = { 922 .data_size = sizeof(PVSCSICmdDescSetupRings), 923 .handler_fn = pvscsi_on_cmd_setup_rings, 924 }, 925 926 [PVSCSI_CMD_RESET_DEVICE] = { 927 .data_size = sizeof(struct PVSCSICmdDescResetDevice), 928 .handler_fn = pvscsi_on_cmd_reset_device, 929 }, 930 931 [PVSCSI_CMD_RESET_BUS] = { 932 .data_size = 0, 933 .handler_fn = pvscsi_on_cmd_reset_bus, 934 }, 935 936 [PVSCSI_CMD_SETUP_MSG_RING] = { 937 .data_size = sizeof(PVSCSICmdDescSetupMsgRing), 938 .handler_fn = pvscsi_on_cmd_setup_msg_ring, 939 }, 940 941 [PVSCSI_CMD_ADAPTER_RESET] = { 942 .data_size = 0, 943 .handler_fn = pvscsi_on_cmd_adapter_reset, 944 }, 945 946 [PVSCSI_CMD_ABORT_CMD] = { 947 .data_size = sizeof(struct PVSCSICmdDescAbortCmd), 948 .handler_fn = pvscsi_on_cmd_abort, 949 }, 950 }; 951 952 static void 953 pvscsi_do_command_processing(PVSCSIState *s) 954 { 955 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 956 957 assert(s->curr_cmd < PVSCSI_CMD_LAST); 958 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) { 959 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s); 960 s->curr_cmd = PVSCSI_CMD_FIRST; 961 s->curr_cmd_data_cntr = 0; 962 } 963 } 964 965 static void 966 pvscsi_on_command_data(PVSCSIState *s, uint32_t value) 967 { 968 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 969 970 assert(bytes_arrived < sizeof(s->curr_cmd_data)); 971 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value; 972 973 pvscsi_do_command_processing(s); 974 } 975 976 static void 977 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id) 978 { 979 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) { 980 s->curr_cmd = cmd_id; 981 } else { 982 s->curr_cmd = PVSCSI_CMD_FIRST; 983 trace_pvscsi_on_cmd_unknown(cmd_id); 984 } 985 986 s->curr_cmd_data_cntr = 0; 987 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA; 988 989 pvscsi_do_command_processing(s); 990 } 991 992 static void 993 pvscsi_io_write(void *opaque, hwaddr addr, 994 uint64_t val, unsigned size) 995 { 996 PVSCSIState *s = opaque; 997 998 switch (addr) { 999 case PVSCSI_REG_OFFSET_COMMAND: 1000 pvscsi_on_command(s, val); 1001 break; 1002 1003 case PVSCSI_REG_OFFSET_COMMAND_DATA: 1004 pvscsi_on_command_data(s, (uint32_t) val); 1005 break; 1006 1007 case PVSCSI_REG_OFFSET_INTR_STATUS: 1008 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val); 1009 s->reg_interrupt_status &= ~val; 1010 pvscsi_update_irq_status(s); 1011 pvscsi_schedule_completion_processing(s); 1012 break; 1013 1014 case PVSCSI_REG_OFFSET_INTR_MASK: 1015 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val); 1016 s->reg_interrupt_enabled = val; 1017 pvscsi_update_irq_status(s); 1018 break; 1019 1020 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO: 1021 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val); 1022 pvscsi_process_io(s); 1023 break; 1024 1025 case PVSCSI_REG_OFFSET_KICK_RW_IO: 1026 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val); 1027 pvscsi_process_io(s); 1028 break; 1029 1030 case PVSCSI_REG_OFFSET_DEBUG: 1031 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val); 1032 break; 1033 1034 default: 1035 trace_pvscsi_io_write_unknown(addr, size, val); 1036 break; 1037 } 1038 1039 } 1040 1041 static uint64_t 1042 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size) 1043 { 1044 PVSCSIState *s = opaque; 1045 1046 switch (addr) { 1047 case PVSCSI_REG_OFFSET_INTR_STATUS: 1048 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS", 1049 s->reg_interrupt_status); 1050 return s->reg_interrupt_status; 1051 1052 case PVSCSI_REG_OFFSET_INTR_MASK: 1053 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK", 1054 s->reg_interrupt_status); 1055 return s->reg_interrupt_enabled; 1056 1057 case PVSCSI_REG_OFFSET_COMMAND_STATUS: 1058 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS", 1059 s->reg_interrupt_status); 1060 return s->reg_command_status; 1061 1062 default: 1063 trace_pvscsi_io_read_unknown(addr, size); 1064 return 0; 1065 } 1066 } 1067 1068 1069 static void 1070 pvscsi_init_msi(PVSCSIState *s) 1071 { 1072 int res; 1073 PCIDevice *d = PCI_DEVICE(s); 1074 1075 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS, 1076 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL); 1077 if (res < 0) { 1078 trace_pvscsi_init_msi_fail(res); 1079 s->msi_used = false; 1080 } else { 1081 s->msi_used = true; 1082 } 1083 } 1084 1085 static void 1086 pvscsi_cleanup_msi(PVSCSIState *s) 1087 { 1088 PCIDevice *d = PCI_DEVICE(s); 1089 1090 msi_uninit(d); 1091 } 1092 1093 static const MemoryRegionOps pvscsi_ops = { 1094 .read = pvscsi_io_read, 1095 .write = pvscsi_io_write, 1096 .endianness = DEVICE_LITTLE_ENDIAN, 1097 .impl = { 1098 .min_access_size = 4, 1099 .max_access_size = 4, 1100 }, 1101 }; 1102 1103 static const struct SCSIBusInfo pvscsi_scsi_info = { 1104 .tcq = true, 1105 .max_target = PVSCSI_MAX_DEVS, 1106 .max_channel = 0, 1107 .max_lun = 0, 1108 1109 .get_sg_list = pvscsi_get_sg_list, 1110 .complete = pvscsi_command_complete, 1111 .cancel = pvscsi_request_cancelled, 1112 }; 1113 1114 static void 1115 pvscsi_realizefn(PCIDevice *pci_dev, Error **errp) 1116 { 1117 PVSCSIState *s = PVSCSI(pci_dev); 1118 1119 trace_pvscsi_state("init"); 1120 1121 /* PCI subsystem ID, subsystem vendor ID, revision */ 1122 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) { 1123 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000); 1124 } else { 1125 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1126 PCI_VENDOR_ID_VMWARE); 1127 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1128 PCI_DEVICE_ID_VMWARE_PVSCSI); 1129 pci_config_set_revision(pci_dev->config, 0x2); 1130 } 1131 1132 /* PCI latency timer = 255 */ 1133 pci_dev->config[PCI_LATENCY_TIMER] = 0xff; 1134 1135 /* Interrupt pin A */ 1136 pci_config_set_interrupt_pin(pci_dev->config, 1); 1137 1138 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s, 1139 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE); 1140 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space); 1141 1142 pvscsi_init_msi(s); 1143 1144 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_get_bus(pci_dev))) { 1145 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET); 1146 } 1147 1148 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); 1149 1150 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), 1151 &pvscsi_scsi_info, NULL); 1152 /* override default SCSI bus hotplug-handler, with pvscsi's one */ 1153 qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s)); 1154 pvscsi_reset_state(s); 1155 } 1156 1157 static void 1158 pvscsi_uninit(PCIDevice *pci_dev) 1159 { 1160 PVSCSIState *s = PVSCSI(pci_dev); 1161 1162 trace_pvscsi_state("uninit"); 1163 qemu_bh_delete(s->completion_worker); 1164 1165 pvscsi_cleanup_msi(s); 1166 } 1167 1168 static void 1169 pvscsi_reset(DeviceState *dev) 1170 { 1171 PCIDevice *d = PCI_DEVICE(dev); 1172 PVSCSIState *s = PVSCSI(d); 1173 1174 trace_pvscsi_state("reset"); 1175 pvscsi_reset_adapter(s); 1176 } 1177 1178 static int 1179 pvscsi_pre_save(void *opaque) 1180 { 1181 PVSCSIState *s = (PVSCSIState *) opaque; 1182 1183 trace_pvscsi_state("presave"); 1184 1185 assert(QTAILQ_EMPTY(&s->pending_queue)); 1186 assert(QTAILQ_EMPTY(&s->completion_queue)); 1187 1188 return 0; 1189 } 1190 1191 static int 1192 pvscsi_post_load(void *opaque, int version_id) 1193 { 1194 trace_pvscsi_state("postload"); 1195 return 0; 1196 } 1197 1198 static bool pvscsi_vmstate_need_pcie_device(void *opaque) 1199 { 1200 PVSCSIState *s = PVSCSI(opaque); 1201 1202 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE); 1203 } 1204 1205 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id) 1206 { 1207 return !pvscsi_vmstate_need_pcie_device(opaque); 1208 } 1209 1210 static const VMStateDescription vmstate_pvscsi_pcie_device = { 1211 .name = "pvscsi/pcie", 1212 .needed = pvscsi_vmstate_need_pcie_device, 1213 .fields = (VMStateField[]) { 1214 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState), 1215 VMSTATE_END_OF_LIST() 1216 } 1217 }; 1218 1219 static const VMStateDescription vmstate_pvscsi = { 1220 .name = "pvscsi", 1221 .version_id = 0, 1222 .minimum_version_id = 0, 1223 .pre_save = pvscsi_pre_save, 1224 .post_load = pvscsi_post_load, 1225 .fields = (VMStateField[]) { 1226 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState, 1227 pvscsi_vmstate_test_pci_device, 0, 1228 vmstate_pci_device, PCIDevice), 1229 VMSTATE_UINT8(msi_used, PVSCSIState), 1230 VMSTATE_UINT32(resetting, PVSCSIState), 1231 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), 1232 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState), 1233 VMSTATE_UINT64(reg_command_status, PVSCSIState), 1234 VMSTATE_UINT64(curr_cmd, PVSCSIState), 1235 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState), 1236 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState, 1237 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)), 1238 VMSTATE_UINT8(rings_info_valid, PVSCSIState), 1239 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState), 1240 VMSTATE_UINT8(use_msg, PVSCSIState), 1241 1242 VMSTATE_UINT64(rings.rs_pa, PVSCSIState), 1243 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState), 1244 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState), 1245 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState, 1246 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1247 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState, 1248 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1249 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState), 1250 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState), 1251 1252 VMSTATE_END_OF_LIST() 1253 }, 1254 .subsections = (const VMStateDescription*[]) { 1255 &vmstate_pvscsi_pcie_device, 1256 NULL 1257 } 1258 }; 1259 1260 static Property pvscsi_properties[] = { 1261 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), 1262 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags, 1263 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false), 1264 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags, 1265 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false), 1266 DEFINE_PROP_END_OF_LIST(), 1267 }; 1268 1269 static void pvscsi_realize(DeviceState *qdev, Error **errp) 1270 { 1271 PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev); 1272 PCIDevice *pci_dev = PCI_DEVICE(qdev); 1273 PVSCSIState *s = PVSCSI(qdev); 1274 1275 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) { 1276 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1277 } 1278 1279 pvs_c->parent_dc_realize(qdev, errp); 1280 } 1281 1282 static void pvscsi_class_init(ObjectClass *klass, void *data) 1283 { 1284 DeviceClass *dc = DEVICE_CLASS(klass); 1285 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1286 PVSCSIClass *pvs_k = PVSCSI_CLASS(klass); 1287 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 1288 1289 k->realize = pvscsi_realizefn; 1290 k->exit = pvscsi_uninit; 1291 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1292 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; 1293 k->class_id = PCI_CLASS_STORAGE_SCSI; 1294 k->subsystem_id = 0x1000; 1295 device_class_set_parent_realize(dc, pvscsi_realize, 1296 &pvs_k->parent_dc_realize); 1297 dc->reset = pvscsi_reset; 1298 dc->vmsd = &vmstate_pvscsi; 1299 device_class_set_props(dc, pvscsi_properties); 1300 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1301 hc->unplug = pvscsi_hot_unplug; 1302 hc->plug = pvscsi_hotplug; 1303 } 1304 1305 static const TypeInfo pvscsi_info = { 1306 .name = TYPE_PVSCSI, 1307 .parent = TYPE_PCI_DEVICE, 1308 .class_size = sizeof(PVSCSIClass), 1309 .instance_size = sizeof(PVSCSIState), 1310 .class_init = pvscsi_class_init, 1311 .interfaces = (InterfaceInfo[]) { 1312 { TYPE_HOTPLUG_HANDLER }, 1313 { INTERFACE_PCIE_DEVICE }, 1314 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1315 { } 1316 } 1317 }; 1318 1319 static void 1320 pvscsi_register_types(void) 1321 { 1322 type_register_static(&pvscsi_info); 1323 } 1324 1325 type_init(pvscsi_register_types); 1326