| /linux-6.15/drivers/gpu/drm/i915/display/ |
| D | intel_display_driver.c | 5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
12 #include <drm/display/drm_dp_mst_helper.h>
83 void intel_display_driver_init_hw(struct intel_display *display) in intel_display_driver_init_hw() argument
85 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_driver_init_hw()
88 if (!HAS_DISPLAY(display)) in intel_display_driver_init_hw()
91 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); in intel_display_driver_init_hw()
93 intel_update_cdclk(display); in intel_display_driver_init_hw()
94 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
95 cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; in intel_display_driver_init_hw()
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| D | i9xx_display_sr.c | 15 static void i9xx_display_save_swf(struct intel_display *display) in i9xx_display_save_swf() argument
20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
30 } else if (HAS_GMCH(display)) { in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
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| D | intel_display_power.c | 201 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
212 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
227 * @display: display device instance
242 bool intel_display_power_is_enabled(struct intel_display *display, in intel_display_power_is_enabled() argument
245 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
249 ret = __intel_display_power_is_enabled(display, domain); in intel_display_power_is_enabled()
256 sanitize_target_dc_state(struct intel_display *display, in sanitize_target_dc_state() argument
259 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
283 * @display: display device
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| D | intel_display_power_well.c | 49 void (*sync_hw)(struct intel_display *display,
56 void (*enable)(struct intel_display *display,
62 void (*disable)(struct intel_display *display,
65 bool (*is_enabled)(struct intel_display *display,
76 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
81 for_each_power_well(display, power_well) in lookup_power_well()
88 * to abort things like display initialization sequences. Just return in lookup_power_well()
92 drm_WARN(display->drm, 1, in lookup_power_well()
95 return &display->power.domains.power_wells[0]; in lookup_power_well()
98 void intel_power_well_enable(struct intel_display *display, in intel_power_well_enable() argument
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| D | intel_fdi.c | 27 static void assert_fdi_tx(struct intel_display *display, in assert_fdi_tx() argument
32 if (HAS_DDI(display)) { in assert_fdi_tx()
40 cur_state = intel_de_read(display, in assert_fdi_tx()
41 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
43 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
45 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_fdi_tx()
50 void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe) in assert_fdi_tx_enabled() argument
52 assert_fdi_tx(display, pipe, true); in assert_fdi_tx_enabled()
55 void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe) in assert_fdi_tx_disabled() argument
57 assert_fdi_tx(display, pipe, false); in assert_fdi_tx_disabled()
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| D | intel_cdclk.c | 55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
117 void (*get_cdclk)(struct intel_display *display,
119 void (*set_cdclk)(struct intel_display *display,
126 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
132 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
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| D | intel_gmbus.c | 34 #include <drm/display/drm_hdcp_helper.h>
51 struct intel_display *display; member
152 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
155 struct drm_i915_private *i915 = to_i915(display->drm); in get_gmbus_pin()
177 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
194 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) in intel_gmbus_is_valid_pin() argument
196 return get_gmbus_pin(display, pin); in intel_gmbus_is_valid_pin()
210 intel_gmbus_reset(struct intel_display *display) in intel_gmbus_reset() argument
212 intel_de_write(display, GMBUS0(display), 0); in intel_gmbus_reset()
213 intel_de_write(display, GMBUS4(display), 0); in intel_gmbus_reset()
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| D | intel_fifo_underrun.c | 41 * The i915 driver checks for display fifo underruns using the interrupt signals
43 * debug display issues, especially watermark settings.
58 static bool ivb_can_enable_err_int(struct intel_display *display) in ivb_can_enable_err_int() argument
60 struct drm_i915_private *dev_priv = to_i915(display->drm); in ivb_can_enable_err_int()
66 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
67 crtc = intel_crtc_for_pipe(display, pipe); in ivb_can_enable_err_int()
76 static bool cpt_can_enable_serr_int(struct intel_display *display) in cpt_can_enable_serr_int() argument
78 struct drm_i915_private *dev_priv = to_i915(display->drm); in cpt_can_enable_serr_int()
84 for_each_pipe(display, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(display, pipe); in cpt_can_enable_serr_int()
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| D | intel_de.h | 16 static inline struct intel_uncore *__to_uncore(struct intel_display *display) in __to_uncore() argument
18 return to_intel_uncore(display->drm); in __to_uncore()
22 __intel_de_read(struct intel_display *display, i915_reg_t reg) in __intel_de_read() argument
26 intel_dmc_wl_get(display, reg); in __intel_de_read()
28 val = intel_uncore_read(__to_uncore(display), reg); in __intel_de_read()
30 intel_dmc_wl_put(display, reg); in __intel_de_read()
37 intel_de_read8(struct intel_display *display, i915_reg_t reg) in intel_de_read8() argument
41 intel_dmc_wl_get(display, reg); in intel_de_read8()
43 val = intel_uncore_read8(__to_uncore(display), reg); in intel_de_read8()
45 intel_dmc_wl_put(display, reg); in intel_de_read8()
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| D | intel_combo_phy.c | 56 icl_get_procmon_ref_values(struct intel_display *display, enum phy phy) in icl_get_procmon_ref_values() argument
60 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 static void icl_set_procmon_ref_values(struct intel_display *display, in icl_set_procmon_ref_values() argument
83 procmon = icl_get_procmon_ref_values(display, phy); in icl_set_procmon_ref_values()
85 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
88 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
89 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
92 static bool check_phy_reg(struct intel_display *display, in check_phy_reg() argument
96 u32 val = intel_de_read(display, reg); in check_phy_reg()
99 drm_dbg_kms(display->drm, in check_phy_reg()
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| D | intel_display_irq.c | 33 intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, in intel_display_irq_regs_init() argument
36 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_init()
37 intel_dmc_wl_get(display, regs.ier); in intel_display_irq_regs_init()
38 intel_dmc_wl_get(display, regs.iir); in intel_display_irq_regs_init()
40 gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); in intel_display_irq_regs_init()
42 intel_dmc_wl_put(display, regs.iir); in intel_display_irq_regs_init()
43 intel_dmc_wl_put(display, regs.ier); in intel_display_irq_regs_init()
44 intel_dmc_wl_put(display, regs.imr); in intel_display_irq_regs_init()
48 intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) in intel_display_irq_regs_reset() argument
50 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_reset()
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| D | intel_dmc.c | 38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
39 * engine to save and restore the state of display engine when it enter into
55 struct intel_display *display; member
73 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
75 return display->dmc.dmc; in display_to_dmc()
78 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
80 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
85 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
87 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
168 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
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| D | intel_audio.c | 43 * DOC: High Definition Audio over HDMI and Display Port
46 * HDMI and Display Port. The audio programming sequences are divided into audio
191 static bool needs_wa_14020863754(struct intel_display *display) in needs_wa_14020863754() argument
193 return DISPLAY_VERx100(display) == 3000 || in needs_wa_14020863754()
194 DISPLAY_VERx100(display) == 2000 || in needs_wa_14020863754()
195 DISPLAY_VERx100(display) == 1401; in needs_wa_14020863754()
201 struct intel_display *display = to_intel_display(crtc_state); in audio_config_hdmi_pixel_clock() local
211 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
215 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
221 drm_dbg_kms(display->drm, in audio_config_hdmi_pixel_clock()
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| D | intel_pps.c | 23 static void vlv_steal_power_sequencer(struct intel_display *display,
31 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
67 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
73 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in intel_pps_lock()
74 mutex_lock(&display->pps.mutex); in intel_pps_lock()
82 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
84 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
85 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in intel_pps_unlock()
93 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
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| D | intel_fbc.c | 28 * compressing the amount of memory used by the display. It is total
33 * and having fewer memory pages opened and accessed for refreshing the display.
95 struct intel_display *display; member
159 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
173 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
187 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
196 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
197 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
204 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride() local
209 return _intel_fbc_cfb_stride(display, cpp, width, stride); in intel_fbc_cfb_stride()
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| D | i9xx_plane.c | 112 static bool i9xx_plane_has_fbc(struct intel_display *display, in i9xx_plane_has_fbc() argument
115 if (!HAS_FBC(display)) in i9xx_plane_has_fbc()
118 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
120 else if (display->platform.ivybridge) in i9xx_plane_has_fbc()
123 else if (DISPLAY_VER(display) >= 4) in i9xx_plane_has_fbc()
129 static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, in i9xx_plane_fbc() argument
132 if (i9xx_plane_has_fbc(display, i9xx_plane)) in i9xx_plane_fbc()
133 return display->fbc[INTEL_FBC_A]; in i9xx_plane_fbc()
140 struct intel_display *display = to_intel_display(plane); in i9xx_plane_has_windowing() local
143 if (display->platform.cherryview) in i9xx_plane_has_windowing()
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| D | intel_vrr.c | 19 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
45 return HAS_VRR(display) && in intel_vrr_is_capable()
84 static int intel_vrr_extra_vblank_delay(struct intel_display *display) in intel_vrr_extra_vblank_delay() argument
94 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
99 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vblank_delay() local
102 intel_vrr_extra_vblank_delay(display); in intel_vrr_vblank_delay()
105 static int intel_vrr_flipline_offset(struct intel_display *display) in intel_vrr_flipline_offset() argument
108 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_flipline_offset()
113 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vmin_flipline() local
115 return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display); in intel_vrr_vmin_flipline()
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| D | intel_display_power.h | 170 int intel_power_domains_init(struct intel_display *display);
171 void intel_power_domains_cleanup(struct intel_display *display);
172 void intel_power_domains_init_hw(struct intel_display *display, bool resume);
173 void intel_power_domains_driver_remove(struct intel_display *display);
174 void intel_power_domains_enable(struct intel_display *display);
175 void intel_power_domains_disable(struct intel_display *display);
176 void intel_power_domains_suspend(struct intel_display *display, bool s2idle);
177 void intel_power_domains_resume(struct intel_display *display);
178 void intel_power_domains_sanitize_state(struct intel_display *display);
180 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle);
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| D | intel_hdcp.c | 16 #include <drm/display/drm_hdcp_helper.h>
40 struct intel_display *display = to_intel_display(encoder); in intel_hdcp_adjust_hdcp_line_rekeying() local
48 if (DISPLAY_VER(display) >= 30) { in intel_hdcp_adjust_hdcp_line_rekeying()
49 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
51 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || in intel_hdcp_adjust_hdcp_line_rekeying()
52 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
53 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
55 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
56 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
61 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); in intel_hdcp_adjust_hdcp_line_rekeying()
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| D | intel_dkl_phy.c | 15 * @display: display device instance
17 void intel_dkl_phy_init(struct intel_display *display) in intel_dkl_phy_init() argument
19 spin_lock_init(&display->dkl.phy_lock); in intel_dkl_phy_init()
23 dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg) in dkl_phy_set_hip_idx() argument
27 drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
29 intel_de_write(display, in dkl_phy_set_hip_idx()
36 * @display: intel_display device instance
44 intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg) in intel_dkl_phy_read() argument
48 spin_lock(&display->dkl.phy_lock); in intel_dkl_phy_read()
50 dkl_phy_set_hip_idx(display, reg); in intel_dkl_phy_read()
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| D | vlv_dsi_regs.h | 14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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| D | intel_lpe_audio.c | 80 #define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev) argument
83 lpe_audio_platdev_create(struct intel_display *display) in lpe_audio_platdev_create() argument
85 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in lpe_audio_platdev_create()
101 rsc[0].start = display->audio.lpe.irq; in lpe_audio_platdev_create()
102 rsc[0].end = display->audio.lpe.irq; in lpe_audio_platdev_create()
113 pinfo.parent = display->drm->dev; in lpe_audio_platdev_create()
122 pdata->num_pipes = INTEL_NUM_PIPES(display); in lpe_audio_platdev_create()
123 pdata->num_ports = display->platform.cherryview ? 3 : 2; /* B,C,D or B,C */ in lpe_audio_platdev_create()
134 drm_err(display->drm, in lpe_audio_platdev_create()
144 static void lpe_audio_platdev_destroy(struct intel_display *display) in lpe_audio_platdev_destroy() argument
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| /linux-6.15/drivers/gpu/drm/i915/ |
| D | Makefile | 12 # Support compiling the display code separately for both i915 and xe
222 display/hsw_ips.o \
223 display/i9xx_plane.o \
224 display/i9xx_display_sr.o \
225 display/i9xx_wm.o \
226 display/intel_alpm.o \
227 display/intel_atomic.o \
228 display/intel_atomic_plane.o \
229 display/intel_audio.o \
230 display/intel_bios.o \
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| /linux-6.15/drivers/gpu/drm/xe/ |
| D | Makefile | 162 # i915 Display compat #defines and #includes
164 -I$(src)/display/ext \
166 -I$(srctree)/drivers/gpu/drm/i915/display/ \
174 # Rule to build display code shared with i915
175 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
179 # Display code specific to xe
181 display/ext/i915_irq.o \
182 display/ext/i915_utils.o \
183 display/intel_bo.o \
184 display/intel_fb_bo.o \
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| /linux-6.15/drivers/gpu/drm/xe/display/ |
| D | xe_display.c | 41 return HAS_DISPLAY(&xe->display); in has_display()
60 * xe_display_driver_set_hooks - Add driver flags and hooks for display
64 * display IP. This sets the driver's capability of driving display, regardless
88 destroy_workqueue(xe->display.hotplug.dp_wq); in display_destroy()
92 * xe_display_create - create display struct
95 * Initialize all fields used by the display part.
98 * to the rest of xe and return it to be xe->display.
104 spin_lock_init(&xe->display.fb_tracking.lock); in xe_display_create()
106 xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0); in xe_display_create()
114 struct intel_display *display = &xe->display; in xe_display_fini_early() local
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