27 static void assert_fdi_tx(struct intel_display *display,  in assert_fdi_tx()  argument
32 	if (HAS_DDI(display)) {  in assert_fdi_tx()
40 		cur_state = intel_de_read(display,  in assert_fdi_tx()
41 					  TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;  in assert_fdi_tx()
43 		cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;  in assert_fdi_tx()
45 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,  in assert_fdi_tx()
50 void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_tx_enabled()  argument
52 	assert_fdi_tx(display, pipe, true);  in assert_fdi_tx_enabled()
55 void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_tx_disabled()  argument
57 	assert_fdi_tx(display, pipe, false);  in assert_fdi_tx_disabled()
60 static void assert_fdi_rx(struct intel_display *display,  in assert_fdi_rx()  argument
65 	cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;  in assert_fdi_rx()
66 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,  in assert_fdi_rx()
71 void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_rx_enabled()  argument
73 	assert_fdi_rx(display, pipe, true);  in assert_fdi_rx_enabled()
76 void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_rx_disabled()  argument
78 	assert_fdi_rx(display, pipe, false);  in assert_fdi_rx_disabled()
81 void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_tx_pll_enabled()  argument
86 	if (display->platform.ironlake)  in assert_fdi_tx_pll_enabled()
90 	if (HAS_DDI(display))  in assert_fdi_tx_pll_enabled()
93 	cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;  in assert_fdi_tx_pll_enabled()
94 	INTEL_DISPLAY_STATE_WARN(display, !cur_state,  in assert_fdi_tx_pll_enabled()
98 static void assert_fdi_rx_pll(struct intel_display *display,  in assert_fdi_rx_pll()  argument
103 	cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;  in assert_fdi_rx_pll()
104 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,  in assert_fdi_rx_pll()
109 void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_rx_pll_enabled()  argument
111 	assert_fdi_rx_pll(display, pipe, true);  in assert_fdi_rx_pll_enabled()
114 void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)  in assert_fdi_rx_pll_disabled()  argument
116 	assert_fdi_rx_pll(display, pipe, false);  in assert_fdi_rx_pll_disabled()
122 	struct intel_display *display = to_intel_display(crtc);  in intel_fdi_link_train()  local
124 	display->funcs.fdi->fdi_link_train(crtc, crtc_state);  in intel_fdi_link_train()
140 	struct intel_display *display = to_intel_display(state);  in intel_fdi_add_affected_crtcs()  local
145 	if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3)  in intel_fdi_add_affected_crtcs()
148 	crtc = intel_crtc_for_pipe(display, PIPE_C);  in intel_fdi_add_affected_crtcs()
160 	crtc = intel_crtc_for_pipe(display, PIPE_B);  in intel_fdi_add_affected_crtcs()
183 static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe,  in ilk_check_fdi_lanes()  argument
193 	drm_dbg_kms(display->drm,  in ilk_check_fdi_lanes()
197 		drm_dbg_kms(display->drm,  in ilk_check_fdi_lanes()
203 	if (display->platform.haswell || display->platform.broadwell) {  in ilk_check_fdi_lanes()
205 			drm_dbg_kms(display->drm,  in ilk_check_fdi_lanes()
214 	if (INTEL_NUM_PIPES(display) == 2)  in ilk_check_fdi_lanes()
225 		other_crtc = intel_crtc_for_pipe(display, PIPE_C);  in ilk_check_fdi_lanes()
232 			drm_dbg_kms(display->drm,  in ilk_check_fdi_lanes()
240 			drm_dbg_kms(display->drm,  in ilk_check_fdi_lanes()
246 		other_crtc = intel_crtc_for_pipe(display, PIPE_B);  in ilk_check_fdi_lanes()
253 			drm_dbg_kms(display->drm,  in ilk_check_fdi_lanes()
267 void intel_fdi_pll_freq_update(struct intel_display *display)  in intel_fdi_pll_freq_update()  argument
269 	if (display->platform.ironlake) {  in intel_fdi_pll_freq_update()
272 		fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;  in intel_fdi_pll_freq_update()
274 		display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000;  in intel_fdi_pll_freq_update()
275 	} else if (display->platform.sandybridge || display->platform.ivybridge) {  in intel_fdi_pll_freq_update()
276 		display->fdi.pll_freq = 270000;  in intel_fdi_pll_freq_update()
281 	drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq);  in intel_fdi_pll_freq_update()
284 int intel_fdi_link_freq(struct intel_display *display,  in intel_fdi_link_freq()  argument
287 	if (HAS_DDI(display))  in intel_fdi_link_freq()
290 		return display->fdi.pll_freq;  in intel_fdi_link_freq()
324 	struct intel_display *display = to_intel_display(crtc);  in ilk_fdi_compute_config()  local
335 	link_bw = intel_fdi_link_freq(display, pipe_config);  in ilk_fdi_compute_config()
358 	struct intel_display *display = to_intel_display(crtc);  in intel_fdi_atomic_check_bw()  local
362 	ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,  in intel_fdi_atomic_check_bw()
415 static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable)  in cpt_set_fdi_bc_bifurcation()  argument
419 	temp = intel_de_read(display, SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
423 	drm_WARN_ON(display->drm,  in cpt_set_fdi_bc_bifurcation()
424 		    intel_de_read(display, FDI_RX_CTL(PIPE_B)) &  in cpt_set_fdi_bc_bifurcation()
426 	drm_WARN_ON(display->drm,  in cpt_set_fdi_bc_bifurcation()
427 		    intel_de_read(display, FDI_RX_CTL(PIPE_C)) &  in cpt_set_fdi_bc_bifurcation()
434 	drm_dbg_kms(display->drm, "%sabling fdi C rx\n",  in cpt_set_fdi_bc_bifurcation()
436 	intel_de_write(display, SOUTH_CHICKEN1, temp);  in cpt_set_fdi_bc_bifurcation()
437 	intel_de_posting_read(display, SOUTH_CHICKEN1);  in cpt_set_fdi_bc_bifurcation()
442 	struct intel_display *display = to_intel_display(crtc_state);  in ivb_update_fdi_bc_bifurcation()  local
450 			cpt_set_fdi_bc_bifurcation(display, false);  in ivb_update_fdi_bc_bifurcation()
452 			cpt_set_fdi_bc_bifurcation(display, true);  in ivb_update_fdi_bc_bifurcation()
456 		cpt_set_fdi_bc_bifurcation(display, true);  in ivb_update_fdi_bc_bifurcation()
466 	struct intel_display *display = to_intel_display(crtc);  in intel_fdi_normal_train()  local
467 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_fdi_normal_train()
474 	temp = intel_de_read(display, reg);  in intel_fdi_normal_train()
475 	if (display->platform.ivybridge) {  in intel_fdi_normal_train()
482 	intel_de_write(display, reg, temp);  in intel_fdi_normal_train()
485 	temp = intel_de_read(display, reg);  in intel_fdi_normal_train()
493 	intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);  in intel_fdi_normal_train()
496 	intel_de_posting_read(display, reg);  in intel_fdi_normal_train()
500 	if (display->platform.ivybridge)  in intel_fdi_normal_train()
501 		intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);  in intel_fdi_normal_train()
508 	struct intel_display *display = to_intel_display(crtc);  in ilk_fdi_link_train()  local
517 	intel_de_write(display, FDI_RX_TUSIZE1(pipe),  in ilk_fdi_link_train()
518 		       intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);  in ilk_fdi_link_train()
521 	assert_transcoder_enabled(display, crtc_state->cpu_transcoder);  in ilk_fdi_link_train()
526 	temp = intel_de_read(display, reg);  in ilk_fdi_link_train()
529 	intel_de_write(display, reg, temp);  in ilk_fdi_link_train()
530 	intel_de_read(display, reg);  in ilk_fdi_link_train()
535 	temp = intel_de_read(display, reg);  in ilk_fdi_link_train()
540 	intel_de_write(display, reg, temp | FDI_TX_ENABLE);  in ilk_fdi_link_train()
543 	temp = intel_de_read(display, reg);  in ilk_fdi_link_train()
546 	intel_de_write(display, reg, temp | FDI_RX_ENABLE);  in ilk_fdi_link_train()
548 	intel_de_posting_read(display, reg);  in ilk_fdi_link_train()
552 	intel_de_write(display, FDI_RX_CHICKEN(pipe),  in ilk_fdi_link_train()
554 	intel_de_write(display, FDI_RX_CHICKEN(pipe),  in ilk_fdi_link_train()
559 		temp = intel_de_read(display, reg);  in ilk_fdi_link_train()
560 		drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);  in ilk_fdi_link_train()
563 			drm_dbg_kms(display->drm, "FDI train 1 done.\n");  in ilk_fdi_link_train()
564 			intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK);  in ilk_fdi_link_train()
569 		drm_err(display->drm, "FDI train 1 fail!\n");  in ilk_fdi_link_train()
572 	intel_de_rmw(display, FDI_TX_CTL(pipe),  in ilk_fdi_link_train()
574 	intel_de_rmw(display, FDI_RX_CTL(pipe),  in ilk_fdi_link_train()
576 	intel_de_posting_read(display, FDI_RX_CTL(pipe));  in ilk_fdi_link_train()
581 		temp = intel_de_read(display, reg);  in ilk_fdi_link_train()
582 		drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);  in ilk_fdi_link_train()
585 			intel_de_write(display, reg,  in ilk_fdi_link_train()
587 			drm_dbg_kms(display->drm, "FDI train 2 done.\n");  in ilk_fdi_link_train()
592 		drm_err(display->drm, "FDI train 2 fail!\n");  in ilk_fdi_link_train()
594 	drm_dbg_kms(display->drm, "FDI train done\n");  in ilk_fdi_link_train()
609 	struct intel_display *display = to_intel_display(crtc);  in gen6_fdi_link_train()  local
610 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in gen6_fdi_link_train()
619 	intel_de_write(display, FDI_RX_TUSIZE1(pipe),  in gen6_fdi_link_train()
620 		       intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);  in gen6_fdi_link_train()
625 	temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
628 	intel_de_write(display, reg, temp);  in gen6_fdi_link_train()
630 	intel_de_posting_read(display, reg);  in gen6_fdi_link_train()
635 	temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
643 	intel_de_write(display, reg, temp | FDI_TX_ENABLE);  in gen6_fdi_link_train()
645 	intel_de_write(display, FDI_RX_MISC(pipe),  in gen6_fdi_link_train()
649 	temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
657 	intel_de_write(display, reg, temp | FDI_RX_ENABLE);  in gen6_fdi_link_train()
659 	intel_de_posting_read(display, reg);  in gen6_fdi_link_train()
663 		intel_de_rmw(display, FDI_TX_CTL(pipe),  in gen6_fdi_link_train()
665 		intel_de_posting_read(display, FDI_TX_CTL(pipe));  in gen6_fdi_link_train()
670 			temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
671 			drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);  in gen6_fdi_link_train()
673 				intel_de_write(display, reg,  in gen6_fdi_link_train()
675 				drm_dbg_kms(display->drm,  in gen6_fdi_link_train()
685 		drm_err(display->drm, "FDI train 1 fail!\n");  in gen6_fdi_link_train()
689 	temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
692 	if (display->platform.sandybridge) {  in gen6_fdi_link_train()
697 	intel_de_write(display, reg, temp);  in gen6_fdi_link_train()
700 	temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
708 	intel_de_write(display, reg, temp);  in gen6_fdi_link_train()
710 	intel_de_posting_read(display, reg);  in gen6_fdi_link_train()
714 		intel_de_rmw(display, FDI_TX_CTL(pipe),  in gen6_fdi_link_train()
716 		intel_de_posting_read(display, FDI_TX_CTL(pipe));  in gen6_fdi_link_train()
721 			temp = intel_de_read(display, reg);  in gen6_fdi_link_train()
722 			drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);  in gen6_fdi_link_train()
724 				intel_de_write(display, reg,  in gen6_fdi_link_train()
726 				drm_dbg_kms(display->drm,  in gen6_fdi_link_train()
736 		drm_err(display->drm, "FDI train 2 fail!\n");  in gen6_fdi_link_train()
738 	drm_dbg_kms(display->drm, "FDI train done.\n");  in gen6_fdi_link_train()
745 	struct intel_display *display = to_intel_display(crtc);  in ivb_manual_fdi_link_train()  local
756 	intel_de_write(display, FDI_RX_TUSIZE1(pipe),  in ivb_manual_fdi_link_train()
757 		       intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);  in ivb_manual_fdi_link_train()
762 	temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
765 	intel_de_write(display, reg, temp);  in ivb_manual_fdi_link_train()
767 	intel_de_posting_read(display, reg);  in ivb_manual_fdi_link_train()
770 	drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n",  in ivb_manual_fdi_link_train()
771 		    intel_de_read(display, FDI_RX_IIR(pipe)));  in ivb_manual_fdi_link_train()
777 		temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
780 		intel_de_write(display, reg, temp);  in ivb_manual_fdi_link_train()
783 		temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
787 		intel_de_write(display, reg, temp);  in ivb_manual_fdi_link_train()
791 		temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
798 		intel_de_write(display, reg, temp | FDI_TX_ENABLE);  in ivb_manual_fdi_link_train()
800 		intel_de_write(display, FDI_RX_MISC(pipe),  in ivb_manual_fdi_link_train()
804 		temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
807 		intel_de_write(display, reg, temp | FDI_RX_ENABLE);  in ivb_manual_fdi_link_train()
809 		intel_de_posting_read(display, reg);  in ivb_manual_fdi_link_train()
814 			temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
815 			drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);  in ivb_manual_fdi_link_train()
818 			    (intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {  in ivb_manual_fdi_link_train()
819 				intel_de_write(display, reg,  in ivb_manual_fdi_link_train()
821 				drm_dbg_kms(display->drm,  in ivb_manual_fdi_link_train()
829 			drm_dbg_kms(display->drm,  in ivb_manual_fdi_link_train()
835 		intel_de_rmw(display, FDI_TX_CTL(pipe),  in ivb_manual_fdi_link_train()
838 		intel_de_rmw(display, FDI_RX_CTL(pipe),  in ivb_manual_fdi_link_train()
841 		intel_de_posting_read(display, FDI_RX_CTL(pipe));  in ivb_manual_fdi_link_train()
846 			temp = intel_de_read(display, reg);  in ivb_manual_fdi_link_train()
847 			drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp);  in ivb_manual_fdi_link_train()
850 			    (intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {  in ivb_manual_fdi_link_train()
851 				intel_de_write(display, reg,  in ivb_manual_fdi_link_train()
853 				drm_dbg_kms(display->drm,  in ivb_manual_fdi_link_train()
861 			drm_dbg_kms(display->drm,  in ivb_manual_fdi_link_train()
866 	drm_dbg_kms(display->drm, "FDI train done.\n");  in ivb_manual_fdi_link_train()
880 	struct intel_display *display = to_intel_display(crtc_state);  in hsw_fdi_link_train()  local
895 	intel_de_write(display, FDI_RX_MISC(PIPE_A),  in hsw_fdi_link_train()
902 	rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |  in hsw_fdi_link_train()
905 	intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
906 	intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
911 	intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
914 	drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);  in hsw_fdi_link_train()
921 		intel_de_write(display, DP_TP_CTL(PORT_E),  in hsw_fdi_link_train()
931 		intel_de_write(display, DDI_BUF_CTL(PORT_E),  in hsw_fdi_link_train()
935 		intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
940 		intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));  in hsw_fdi_link_train()
944 		intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
945 		intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
951 		intel_de_rmw(display, FDI_RX_MISC(PIPE_A),  in hsw_fdi_link_train()
953 		intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
958 		temp = intel_de_read(display, DP_TP_STATUS(PORT_E));  in hsw_fdi_link_train()
960 			drm_dbg_kms(display->drm,  in hsw_fdi_link_train()
970 			drm_err(display->drm, "FDI link training failed!\n");  in hsw_fdi_link_train()
975 		intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);  in hsw_fdi_link_train()
976 		intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));  in hsw_fdi_link_train()
978 		intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);  in hsw_fdi_link_train()
979 		intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
982 		intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);  in hsw_fdi_link_train()
983 		intel_de_posting_read(display, DP_TP_CTL(PORT_E));  in hsw_fdi_link_train()
985 		intel_wait_ddi_buf_idle(display, PORT_E);  in hsw_fdi_link_train()
988 		intel_de_rmw(display, FDI_RX_MISC(PIPE_A),  in hsw_fdi_link_train()
991 		intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));  in hsw_fdi_link_train()
995 	intel_de_write(display, DP_TP_CTL(PORT_E),  in hsw_fdi_link_train()
1004 	struct intel_display *display = to_intel_display(encoder);  in hsw_fdi_disable()  local
1012 	intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);  in hsw_fdi_disable()
1013 	intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);  in hsw_fdi_disable()
1014 	intel_wait_ddi_buf_idle(display, PORT_E);  in hsw_fdi_disable()
1016 	intel_de_rmw(display, FDI_RX_MISC(PIPE_A),  in hsw_fdi_disable()
1019 	intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);  in hsw_fdi_disable()
1020 	intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);  in hsw_fdi_disable()
1025 	struct intel_display *display = to_intel_display(crtc_state);  in ilk_fdi_pll_enable()  local
1033 	temp = intel_de_read(display, reg);  in ilk_fdi_pll_enable()
1036 	temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;  in ilk_fdi_pll_enable()
1037 	intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE);  in ilk_fdi_pll_enable()
1039 	intel_de_posting_read(display, reg);  in ilk_fdi_pll_enable()
1043 	intel_de_rmw(display, reg, 0, FDI_PCDCLK);  in ilk_fdi_pll_enable()
1044 	intel_de_posting_read(display, reg);  in ilk_fdi_pll_enable()
1049 	temp = intel_de_read(display, reg);  in ilk_fdi_pll_enable()
1051 		intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE);  in ilk_fdi_pll_enable()
1053 		intel_de_posting_read(display, reg);  in ilk_fdi_pll_enable()
1060 	struct intel_display *display = to_intel_display(crtc);  in ilk_fdi_pll_disable()  local
1064 	intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);  in ilk_fdi_pll_disable()
1067 	intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);  in ilk_fdi_pll_disable()
1068 	intel_de_posting_read(display, FDI_TX_CTL(pipe));  in ilk_fdi_pll_disable()
1072 	intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);  in ilk_fdi_pll_disable()
1073 	intel_de_posting_read(display, FDI_RX_CTL(pipe));  in ilk_fdi_pll_disable()
1079 	struct intel_display *display = to_intel_display(crtc);  in ilk_fdi_disable()  local
1086 	intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);  in ilk_fdi_disable()
1087 	intel_de_posting_read(display, FDI_TX_CTL(pipe));  in ilk_fdi_disable()
1090 	temp = intel_de_read(display, reg);  in ilk_fdi_disable()
1092 	temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;  in ilk_fdi_disable()
1093 	intel_de_write(display, reg, temp & ~FDI_RX_ENABLE);  in ilk_fdi_disable()
1095 	intel_de_posting_read(display, reg);  in ilk_fdi_disable()
1100 		intel_de_write(display, FDI_RX_CHICKEN(pipe),  in ilk_fdi_disable()
1104 	intel_de_rmw(display, FDI_TX_CTL(pipe),  in ilk_fdi_disable()
1108 	temp = intel_de_read(display, reg);  in ilk_fdi_disable()
1118 	temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;  in ilk_fdi_disable()
1119 	intel_de_write(display, reg, temp);  in ilk_fdi_disable()
1121 	intel_de_posting_read(display, reg);  in ilk_fdi_disable()
1138 intel_fdi_init_hook(struct intel_display *display)  in intel_fdi_init_hook()  argument
1140 	if (display->platform.ironlake) {  in intel_fdi_init_hook()
1141 		display->funcs.fdi = &ilk_funcs;  in intel_fdi_init_hook()
1142 	} else if (display->platform.sandybridge) {  in intel_fdi_init_hook()
1143 		display->funcs.fdi = &gen6_funcs;  in intel_fdi_init_hook()
1144 	} else if (display->platform.ivybridge) {  in intel_fdi_init_hook()
1146 		display->funcs.fdi = &ivb_funcs;  in intel_fdi_init_hook()