23 static void vlv_steal_power_sequencer(struct intel_display *display,
31 	struct intel_display *display = to_intel_display(intel_dp);  in pps_name()  local
34 	if (display->platform.valleyview || display->platform.cherryview) {  in pps_name()
67 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_lock()  local
73 	wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);  in intel_pps_lock()
74 	mutex_lock(&display->pps.mutex);  in intel_pps_lock()
82 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_unlock()  local
84 	mutex_unlock(&display->pps.mutex);  in intel_pps_unlock()
85 	intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);  in intel_pps_unlock()
93 	struct intel_display *display = to_intel_display(intel_dp);  in vlv_power_sequencer_kick()  local
94 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in vlv_power_sequencer_kick()
102 	if (drm_WARN(display->drm,  in vlv_power_sequencer_kick()
103 		     intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,  in vlv_power_sequencer_kick()
109 	drm_dbg_kms(display->drm,  in vlv_power_sequencer_kick()
117 	DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;  in vlv_power_sequencer_kick()
122 	if (display->platform.cherryview)  in vlv_power_sequencer_kick()
127 	pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;  in vlv_power_sequencer_kick()
134 		release_cl_override = display->platform.cherryview &&  in vlv_power_sequencer_kick()
135 			!chv_phy_powergate_ch(display, phy, ch, true);  in vlv_power_sequencer_kick()
137 		if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) {  in vlv_power_sequencer_kick()
138 			drm_err(display->drm,  in vlv_power_sequencer_kick()
151 	intel_de_write(display, intel_dp->output_reg, DP);  in vlv_power_sequencer_kick()
152 	intel_de_posting_read(display, intel_dp->output_reg);  in vlv_power_sequencer_kick()
154 	intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);  in vlv_power_sequencer_kick()
155 	intel_de_posting_read(display, intel_dp->output_reg);  in vlv_power_sequencer_kick()
157 	intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);  in vlv_power_sequencer_kick()
158 	intel_de_posting_read(display, intel_dp->output_reg);  in vlv_power_sequencer_kick()
164 			chv_phy_powergate_ch(display, phy, ch, false);  in vlv_power_sequencer_kick()
168 static enum pipe vlv_find_free_pps(struct intel_display *display)  in vlv_find_free_pps()  argument
177 	for_each_intel_dp(display->drm, encoder) {  in vlv_find_free_pps()
181 			drm_WARN_ON(display->drm,  in vlv_find_free_pps()
189 			drm_WARN_ON(display->drm,  in vlv_find_free_pps()
206 	struct intel_display *display = to_intel_display(intel_dp);  in vlv_power_sequencer_pipe()  local
210 	lockdep_assert_held(&display->pps.mutex);  in vlv_power_sequencer_pipe()
213 	drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));  in vlv_power_sequencer_pipe()
215 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&  in vlv_power_sequencer_pipe()
221 	pipe = vlv_find_free_pps(display);  in vlv_power_sequencer_pipe()
227 	if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE))  in vlv_power_sequencer_pipe()
230 	vlv_steal_power_sequencer(display, pipe);  in vlv_power_sequencer_pipe()
233 	drm_dbg_kms(display->drm,  in vlv_power_sequencer_pipe()
254 	struct intel_display *display = to_intel_display(intel_dp);  in bxt_power_sequencer_idx()  local
257 	lockdep_assert_held(&display->pps.mutex);  in bxt_power_sequencer_idx()
260 	drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));  in bxt_power_sequencer_idx()
276 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
278 static bool pps_has_pp_on(struct intel_display *display, int pps_idx)  in pps_has_pp_on()  argument
280 	return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;  in pps_has_pp_on()
283 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx)  in pps_has_vdd_on()  argument
285 	return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;  in pps_has_vdd_on()
288 static bool pps_any(struct intel_display *display, int pps_idx)  in pps_any()  argument
294 vlv_initial_pps_pipe(struct intel_display *display,  in vlv_initial_pps_pipe()  argument
300 		u32 port_sel = intel_de_read(display,  in vlv_initial_pps_pipe()
301 					     PP_ON_DELAYS(display, pipe)) &  in vlv_initial_pps_pipe()
307 		if (!check(display, pipe))  in vlv_initial_pps_pipe()
319 	struct intel_display *display = to_intel_display(intel_dp);  in vlv_initial_power_sequencer_setup()  local
323 	lockdep_assert_held(&display->pps.mutex);  in vlv_initial_power_sequencer_setup()
327 	intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,  in vlv_initial_power_sequencer_setup()
331 		intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,  in vlv_initial_power_sequencer_setup()
335 		intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,  in vlv_initial_power_sequencer_setup()
340 		drm_dbg_kms(display->drm,  in vlv_initial_power_sequencer_setup()
346 	drm_dbg_kms(display->drm,  in vlv_initial_power_sequencer_setup()
352 static int intel_num_pps(struct intel_display *display)  in intel_num_pps()  argument
354 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_num_pps()
356 	if (display->platform.valleyview || display->platform.cherryview)  in intel_num_pps()
359 	if (display->platform.geminilake || display->platform.broxton)  in intel_num_pps()
376 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_is_valid()  local
377 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_pps_is_valid()
382 		return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;  in intel_pps_is_valid()
388 bxt_initial_pps_idx(struct intel_display *display, pps_check check)  in bxt_initial_pps_idx()  argument
390 	int pps_idx, pps_num = intel_num_pps(display);  in bxt_initial_pps_idx()
393 		if (check(display, pps_idx))  in bxt_initial_pps_idx()
403 	struct intel_display *display = to_intel_display(intel_dp);  in pps_initial_setup()  local
407 	lockdep_assert_held(&display->pps.mutex);  in pps_initial_setup()
409 	if (display->platform.valleyview || display->platform.cherryview) {  in pps_initial_setup()
415 	if (intel_num_pps(display) > 1)  in pps_initial_setup()
420 	if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))  in pps_initial_setup()
425 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);  in pps_initial_setup()
428 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);  in pps_initial_setup()
431 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);  in pps_initial_setup()
433 		drm_dbg_kms(display->drm,  in pps_initial_setup()
438 		drm_dbg_kms(display->drm,  in pps_initial_setup()
447 void vlv_pps_reset_all(struct intel_display *display)  in vlv_pps_reset_all()  argument
451 	if (!HAS_DISPLAY(display))  in vlv_pps_reset_all()
464 	for_each_intel_dp(display->drm, encoder) {  in vlv_pps_reset_all()
467 		drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);  in vlv_pps_reset_all()
474 void bxt_pps_reset_all(struct intel_display *display)  in bxt_pps_reset_all()  argument
478 	if (!HAS_DISPLAY(display))  in bxt_pps_reset_all()
483 	for_each_intel_dp(display->drm, encoder) {  in bxt_pps_reset_all()
502 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_get_registers()  local
503 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_pps_get_registers()
508 	if (display->platform.valleyview || display->platform.cherryview)  in intel_pps_get_registers()
510 	else if (display->platform.geminilake || display->platform.broxton)  in intel_pps_get_registers()
515 	regs->pp_ctrl = PP_CONTROL(display, pps_idx);  in intel_pps_get_registers()
516 	regs->pp_stat = PP_STATUS(display, pps_idx);  in intel_pps_get_registers()
517 	regs->pp_on = PP_ON_DELAYS(display, pps_idx);  in intel_pps_get_registers()
518 	regs->pp_off = PP_OFF_DELAYS(display, pps_idx);  in intel_pps_get_registers()
521 	if (display->platform.geminilake || display->platform.broxton ||  in intel_pps_get_registers()
525 		regs->pp_div = PP_DIVISOR(display, pps_idx);  in intel_pps_get_registers()
550 	struct intel_display *display = to_intel_display(intel_dp);  in edp_have_panel_power()  local
552 	lockdep_assert_held(&display->pps.mutex);  in edp_have_panel_power()
554 	if ((display->platform.valleyview || display->platform.cherryview) &&  in edp_have_panel_power()
558 	return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;  in edp_have_panel_power()
563 	struct intel_display *display = to_intel_display(intel_dp);  in edp_have_panel_vdd()  local
565 	lockdep_assert_held(&display->pps.mutex);  in edp_have_panel_vdd()
567 	if ((display->platform.valleyview || display->platform.cherryview) &&  in edp_have_panel_vdd()
571 	return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;  in edp_have_panel_vdd()
576 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_check_power_unlocked()  local
583 		drm_WARN(display->drm, 1,  in intel_pps_check_power_unlocked()
587 		drm_dbg_kms(display->drm,  in intel_pps_check_power_unlocked()
591 			    intel_de_read(display, _pp_stat_reg(intel_dp)),  in intel_pps_check_power_unlocked()
592 			    intel_de_read(display, _pp_ctrl_reg(intel_dp)));  in intel_pps_check_power_unlocked()
610 	struct intel_display *display = to_intel_display(intel_dp);  in wait_panel_status()  local
614 	lockdep_assert_held(&display->pps.mutex);  in wait_panel_status()
621 	drm_dbg_kms(display->drm,  in wait_panel_status()
626 		    intel_de_read(display, pp_stat_reg),  in wait_panel_status()
627 		    intel_de_read(display, pp_ctrl_reg));  in wait_panel_status()
629 	if (intel_de_wait(display, pp_stat_reg, mask, value, 5000))  in wait_panel_status()
630 		drm_err(display->drm,  in wait_panel_status()
634 			intel_de_read(display, pp_stat_reg),  in wait_panel_status()
635 			intel_de_read(display, pp_ctrl_reg));  in wait_panel_status()
637 	drm_dbg_kms(display->drm, "Wait complete\n");  in wait_panel_status()
642 	struct intel_display *display = to_intel_display(intel_dp);  in wait_panel_on()  local
645 	drm_dbg_kms(display->drm,  in wait_panel_on()
654 	struct intel_display *display = to_intel_display(intel_dp);  in wait_panel_off()  local
657 	drm_dbg_kms(display->drm,  in wait_panel_off()
666 	struct intel_display *display = to_intel_display(intel_dp);  in wait_panel_power_cycle()  local
678 	drm_dbg_kms(display->drm,  in wait_panel_power_cycle()
720 	struct intel_display *display = to_intel_display(intel_dp);  in ilk_get_pp_control()  local
723 	lockdep_assert_held(&display->pps.mutex);  in ilk_get_pp_control()
725 	control = intel_de_read(display, _pp_ctrl_reg(intel_dp));  in ilk_get_pp_control()
726 	if (drm_WARN_ON(display->drm, !HAS_DDI(display) &&  in ilk_get_pp_control()
741 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_vdd_on_unlocked()  local
747 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_vdd_on_unlocked()
758 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);  in intel_pps_vdd_on_unlocked()
759 	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,  in intel_pps_vdd_on_unlocked()
765 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n",  in intel_pps_vdd_on_unlocked()
775 	intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_vdd_on_unlocked()
776 	intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_vdd_on_unlocked()
777 	drm_dbg_kms(display->drm,  in intel_pps_vdd_on_unlocked()
781 		    intel_de_read(display, pp_stat_reg),  in intel_pps_vdd_on_unlocked()
782 		    intel_de_read(display, pp_ctrl_reg));  in intel_pps_vdd_on_unlocked()
787 		drm_dbg_kms(display->drm,  in intel_pps_vdd_on_unlocked()
806 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_vdd_on()  local
816 	INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",  in intel_pps_vdd_on()
824 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_vdd_off_sync_unlocked()  local
829 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_vdd_off_sync_unlocked()
831 	drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);  in intel_pps_vdd_off_sync_unlocked()
836 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",  in intel_pps_vdd_off_sync_unlocked()
846 	intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_vdd_off_sync_unlocked()
847 	intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_vdd_off_sync_unlocked()
850 	drm_dbg_kms(display->drm,  in intel_pps_vdd_off_sync_unlocked()
854 		    intel_de_read(display, pp_stat_reg),  in intel_pps_vdd_off_sync_unlocked()
855 		    intel_de_read(display, pp_ctrl_reg));  in intel_pps_vdd_off_sync_unlocked()
862 	intel_display_power_put(display,  in intel_pps_vdd_off_sync_unlocked()
898 	struct intel_display *display = to_intel_display(intel_dp);  in edp_panel_vdd_schedule_off()  local
899 	struct drm_i915_private *i915 = to_i915(display->drm);  in edp_panel_vdd_schedule_off()
926 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_vdd_off_unlocked()  local
928 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_vdd_off_unlocked()
933 	INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,  in intel_pps_vdd_off_unlocked()
960 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_on_unlocked()  local
964 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_on_unlocked()
969 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n",  in intel_pps_on_unlocked()
974 	if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),  in intel_pps_on_unlocked()
985 	if (display->platform.ironlake) {  in intel_pps_on_unlocked()
988 		intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_on_unlocked()
989 		intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_on_unlocked()
996 	if (IS_DISPLAY_VER(display, 13, 14))  in intel_pps_on_unlocked()
997 		intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,  in intel_pps_on_unlocked()
1001 	if (!display->platform.ironlake)  in intel_pps_on_unlocked()
1004 	intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_on_unlocked()
1005 	intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_on_unlocked()
1010 	if (IS_DISPLAY_VER(display, 13, 14))  in intel_pps_on_unlocked()
1011 		intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,  in intel_pps_on_unlocked()
1014 	if (display->platform.ironlake) {  in intel_pps_on_unlocked()
1016 		intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_on_unlocked()
1017 		intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_on_unlocked()
1034 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_off_unlocked()  local
1039 	lockdep_assert_held(&display->pps.mutex);  in intel_pps_off_unlocked()
1044 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n",  in intel_pps_off_unlocked()
1048 	drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,  in intel_pps_off_unlocked()
1063 	intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_off_unlocked()
1064 	intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_off_unlocked()
1072 	intel_display_power_put(display,  in intel_pps_off_unlocked()
1091 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_backlight_on()  local
1109 		intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_backlight_on()
1110 		intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_backlight_on()
1117 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_backlight_off()  local
1130 		intel_de_write(display, pp_ctrl_reg, pp);  in intel_pps_backlight_off()
1131 		intel_de_posting_read(display, pp_ctrl_reg);  in intel_pps_backlight_off()
1144 	struct intel_display *display = to_intel_display(connector);  in intel_pps_backlight_power()  local
1155 	drm_dbg_kms(display->drm, "panel power control backlight %s\n",  in intel_pps_backlight_power()
1166 	struct intel_display *display = to_intel_display(intel_dp);  in vlv_detach_power_sequencer()  local
1169 	i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);  in vlv_detach_power_sequencer()
1171 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);  in vlv_detach_power_sequencer()
1173 	if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B))  in vlv_detach_power_sequencer()
1187 	drm_dbg_kms(display->drm,  in vlv_detach_power_sequencer()
1191 	intel_de_write(display, pp_on_reg, 0);  in vlv_detach_power_sequencer()
1192 	intel_de_posting_read(display, pp_on_reg);  in vlv_detach_power_sequencer()
1197 static void vlv_steal_power_sequencer(struct intel_display *display,  in vlv_steal_power_sequencer()  argument
1202 	lockdep_assert_held(&display->pps.mutex);  in vlv_steal_power_sequencer()
1204 	for_each_intel_dp(display->drm, encoder) {  in vlv_steal_power_sequencer()
1207 		drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,  in vlv_steal_power_sequencer()
1215 		drm_dbg_kms(display->drm,  in vlv_steal_power_sequencer()
1227 	struct intel_display *display = to_intel_display(intel_dp);  in vlv_active_pipe()  local
1231 	if (g4x_dp_port_enabled(display, intel_dp->output_reg,  in vlv_active_pipe()
1278 	struct intel_display *display = to_intel_display(encoder);  in vlv_pps_port_enable_unlocked()  local
1282 	lockdep_assert_held(&display->pps.mutex);  in vlv_pps_port_enable_unlocked()
1284 	drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);  in vlv_pps_port_enable_unlocked()
1300 	vlv_steal_power_sequencer(display, crtc->pipe);  in vlv_pps_port_enable_unlocked()
1310 	drm_dbg_kms(display->drm,  in vlv_pps_port_enable_unlocked()
1334 	struct intel_display *display = to_intel_display(intel_dp);  in pps_vdd_init()  local
1337 	lockdep_assert_held(&display->pps.mutex);  in pps_vdd_init()
1348 	drm_dbg_kms(display->drm,  in pps_vdd_init()
1352 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);  in pps_vdd_init()
1353 	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,  in pps_vdd_init()
1386 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_readout_hw_state()  local
1395 	if (!HAS_DDI(display))  in intel_pps_readout_hw_state()
1396 		intel_de_write(display, regs.pp_ctrl, pp_ctl);  in intel_pps_readout_hw_state()
1398 	pp_on = intel_de_read(display, regs.pp_on);  in intel_pps_readout_hw_state()
1399 	pp_off = intel_de_read(display, regs.pp_off);  in intel_pps_readout_hw_state()
1410 		pp_div = intel_de_read(display, regs.pp_div);  in intel_pps_readout_hw_state()
1425 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_dump_state()  local
1427 	drm_dbg_kms(display->drm,  in intel_pps_dump_state()
1436 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_verify_state()  local
1447 		drm_err(display->drm, "PPS state mismatch\n");  in intel_pps_verify_state()
1474 	struct intel_display *display = to_intel_display(intel_dp);  in pps_init_delays_bios()  local
1476 	lockdep_assert_held(&display->pps.mutex);  in pps_init_delays_bios()
1489 	struct intel_display *display = to_intel_display(intel_dp);  in pps_init_delays_vbt()  local
1503 	if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) {  in pps_init_delays_vbt()
1505 		drm_dbg_kms(display->drm,  in pps_init_delays_vbt()
1516 	struct intel_display *display = to_intel_display(intel_dp);  in pps_init_delays_spec()  local
1518 	lockdep_assert_held(&display->pps.mutex);  in pps_init_delays_spec()
1532 	struct intel_display *display = to_intel_display(intel_dp);  in pps_init_delays()  local
1536 	lockdep_assert_held(&display->pps.mutex);  in pps_init_delays()
1564 	drm_dbg_kms(display->drm,  in pps_init_delays()
1570 	drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n",  in pps_init_delays()
1594 	struct intel_display *display = to_intel_display(intel_dp);  in pps_init_registers()  local
1595 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in pps_init_registers()
1597 	int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000;  in pps_init_registers()
1602 	lockdep_assert_held(&display->pps.mutex);  in pps_init_registers()
1621 		drm_WARN(display->drm, pp & PANEL_POWER_ON,  in pps_init_registers()
1625 			drm_dbg_kms(display->drm,  in pps_init_registers()
1630 		intel_de_write(display, regs.pp_ctrl, pp);  in pps_init_registers()
1640 	if (display->platform.valleyview || display->platform.cherryview) {  in pps_init_registers()
1661 	intel_de_write(display, regs.pp_on, pp_on);  in pps_init_registers()
1662 	intel_de_write(display, regs.pp_off, pp_off);  in pps_init_registers()
1668 		intel_de_write(display, regs.pp_div,  in pps_init_registers()
1674 		intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK,  in pps_init_registers()
1678 	drm_dbg_kms(display->drm,  in pps_init_registers()
1680 		    intel_de_read(display, regs.pp_on),  in pps_init_registers()
1681 		    intel_de_read(display, regs.pp_off),  in pps_init_registers()
1683 		    intel_de_read(display, regs.pp_div) :  in pps_init_registers()
1684 		    (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));  in pps_init_registers()
1689 	struct intel_display *display = to_intel_display(intel_dp);  in intel_pps_encoder_reset()  local
1700 		if (display->platform.valleyview || display->platform.cherryview)  in intel_pps_encoder_reset()
1735 	struct intel_display *display = to_intel_display(intel_dp);  in pps_init_late()  local
1739 	if (display->platform.valleyview || display->platform.cherryview)  in pps_init_late()
1742 	if (intel_num_pps(display) < 2)  in pps_init_late()
1745 	drm_WARN(display->drm,  in pps_init_late()
1775 void intel_pps_unlock_regs_wa(struct intel_display *display)  in intel_pps_unlock_regs_wa()  argument
1780 	if (!HAS_DISPLAY(display) || HAS_DDI(display))  in intel_pps_unlock_regs_wa()
1786 	pps_num = intel_num_pps(display);  in intel_pps_unlock_regs_wa()
1789 		intel_de_rmw(display, PP_CONTROL(display, pps_idx),  in intel_pps_unlock_regs_wa()
1793 void intel_pps_setup(struct intel_display *display)  in intel_pps_setup()  argument
1795 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_pps_setup()
1797 	if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton)  in intel_pps_setup()
1798 		display->pps.mmio_base = PCH_PPS_BASE;  in intel_pps_setup()
1799 	else if (display->platform.valleyview || display->platform.cherryview)  in intel_pps_setup()
1800 		display->pps.mmio_base = VLV_PPS_BASE;  in intel_pps_setup()
1802 		display->pps.mmio_base = PPS_BASE;  in intel_pps_setup()
1838 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)  in assert_pps_unlocked()  argument
1840 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in assert_pps_unlocked()
1846 	if (drm_WARN_ON(display->drm, HAS_DDI(display)))  in assert_pps_unlocked()
1852 		pp_reg = PP_CONTROL(display, 0);  in assert_pps_unlocked()
1853 		port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &  in assert_pps_unlocked()
1861 			g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);  in assert_pps_unlocked()
1864 			g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe);  in assert_pps_unlocked()
1867 			g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe);  in assert_pps_unlocked()
1873 	} else if (display->platform.valleyview || display->platform.cherryview) {  in assert_pps_unlocked()
1875 		pp_reg = PP_CONTROL(display, pipe);  in assert_pps_unlocked()
1880 		pp_reg = PP_CONTROL(display, 0);  in assert_pps_unlocked()
1881 		port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &  in assert_pps_unlocked()
1884 		drm_WARN_ON(display->drm,  in assert_pps_unlocked()
1889 	val = intel_de_read(display, pp_reg);  in assert_pps_unlocked()
1894 	INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,  in assert_pps_unlocked()