Lines Matching full:display
33 intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, in intel_display_irq_regs_init() argument
36 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_init()
37 intel_dmc_wl_get(display, regs.ier); in intel_display_irq_regs_init()
38 intel_dmc_wl_get(display, regs.iir); in intel_display_irq_regs_init()
40 gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); in intel_display_irq_regs_init()
42 intel_dmc_wl_put(display, regs.iir); in intel_display_irq_regs_init()
43 intel_dmc_wl_put(display, regs.ier); in intel_display_irq_regs_init()
44 intel_dmc_wl_put(display, regs.imr); in intel_display_irq_regs_init()
48 intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) in intel_display_irq_regs_reset() argument
50 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_reset()
51 intel_dmc_wl_get(display, regs.ier); in intel_display_irq_regs_reset()
52 intel_dmc_wl_get(display, regs.iir); in intel_display_irq_regs_reset()
54 gen2_irq_reset(to_intel_uncore(display->drm), regs); in intel_display_irq_regs_reset()
56 intel_dmc_wl_put(display, regs.iir); in intel_display_irq_regs_reset()
57 intel_dmc_wl_put(display, regs.ier); in intel_display_irq_regs_reset()
58 intel_dmc_wl_put(display, regs.imr); in intel_display_irq_regs_reset()
62 intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg) in intel_display_irq_regs_assert_irr_is_zero() argument
64 intel_dmc_wl_get(display, reg); in intel_display_irq_regs_assert_irr_is_zero()
66 gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg); in intel_display_irq_regs_assert_irr_is_zero()
68 intel_dmc_wl_put(display, reg); in intel_display_irq_regs_assert_irr_is_zero()
79 struct intel_display *display = to_intel_display(crtc); in handle_plane_fault() local
89 drm_err_ratelimited(display->drm, in handle_plane_fault()
98 static void intel_pipe_fault_irq_handler(struct intel_display *display, in intel_pipe_fault_irq_handler() argument
102 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_pipe_fault_irq_handler()
120 struct intel_display *display = &dev_priv->display; in intel_handle_vblank() local
121 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_handle_vblank()
135 struct intel_display *display = &dev_priv->display; in ilk_update_display_irq() local
148 intel_de_write(display, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
149 intel_de_posting_read(display, DEIMR); in ilk_update_display_irq()
172 struct intel_display *display = &dev_priv->display; in bdw_update_port_irq() local
183 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
190 intel_de_write(display, GEN8_DE_PORT_IMR, new_val); in bdw_update_port_irq()
191 intel_de_posting_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
206 struct intel_display *display = &dev_priv->display; in bdw_update_pipe_irq() local
216 new_val = dev_priv->display.irq.de_irq_mask[pipe]; in bdw_update_pipe_irq()
220 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { in bdw_update_pipe_irq()
221 dev_priv->display.irq.de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
222 intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]); in bdw_update_pipe_irq()
223 intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
249 struct intel_display *display = &dev_priv->display; in ibx_display_interrupt_update() local
250 u32 sdeimr = intel_de_read(display, SDEIMR); in ibx_display_interrupt_update()
262 intel_de_write(display, SDEIMR, sdeimr); in ibx_display_interrupt_update()
263 intel_de_posting_read(display, SDEIMR); in ibx_display_interrupt_update()
276 u32 i915_pipestat_enable_mask(struct intel_display *display, in i915_pipestat_enable_mask() argument
279 struct drm_i915_private *dev_priv = to_i915(display->drm); in i915_pipestat_enable_mask()
280 u32 status_mask = display->irq.pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
285 if (DISPLAY_VER(display) < 5) in i915_pipestat_enable_mask()
292 if (drm_WARN_ON_ONCE(display->drm, in i915_pipestat_enable_mask()
299 if (drm_WARN_ON_ONCE(display->drm, in i915_pipestat_enable_mask()
312 drm_WARN_ONCE(display->drm, in i915_pipestat_enable_mask()
324 struct intel_display *display = &dev_priv->display; in i915_enable_pipestat() local
335 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
338 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
339 enable_mask = i915_pipestat_enable_mask(display, pipe); in i915_enable_pipestat()
341 intel_de_write(display, reg, enable_mask | status_mask); in i915_enable_pipestat()
342 intel_de_posting_read(display, reg); in i915_enable_pipestat()
348 struct intel_display *display = &dev_priv->display; in i915_disable_pipestat() local
359 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
362 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
363 enable_mask = i915_pipestat_enable_mask(display, pipe); in i915_disable_pipestat()
365 intel_de_write(display, reg, enable_mask | status_mask); in i915_disable_pipestat()
366 intel_de_posting_read(display, reg); in i915_disable_pipestat()
369 static bool i915_has_legacy_blc_interrupt(struct intel_display *display) in i915_has_legacy_blc_interrupt() argument
371 struct drm_i915_private *i915 = to_i915(display->drm); in i915_has_legacy_blc_interrupt()
379 return IS_DISPLAY_VER(display, 3, 4) && IS_MOBILE(i915); in i915_has_legacy_blc_interrupt()
388 struct intel_display *display = &dev_priv->display; in i915_enable_asle_pipestat() local
390 if (!intel_opregion_asle_present(display)) in i915_enable_asle_pipestat()
393 if (!i915_has_legacy_blc_interrupt(display)) in i915_enable_asle_pipestat()
413 struct intel_display *display = &dev_priv->display; in display_pipe_crc_irq_handler() local
414 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in display_pipe_crc_irq_handler()
453 struct intel_display *display = &i915->display; in flip_done_handler() local
454 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in flip_done_handler()
470 struct intel_display *display = &dev_priv->display; in hsw_pipe_crc_irq_handler() local
473 intel_de_read(display, PIPE_CRC_RES_HSW(pipe)), in hsw_pipe_crc_irq_handler()
480 struct intel_display *display = &dev_priv->display; in ivb_pipe_crc_irq_handler() local
483 intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
484 intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
485 intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
486 intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
487 intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
493 struct intel_display *display = &dev_priv->display; in i9xx_pipe_crc_irq_handler() local
497 res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
502 res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
507 intel_de_read(display, PIPE_CRC_RES_RED(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
508 intel_de_read(display, PIPE_CRC_RES_GREEN(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
509 intel_de_read(display, PIPE_CRC_RES_BLUE(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
515 struct intel_display *display = &dev_priv->display; in i9xx_pipestat_irq_reset() local
519 intel_de_write(display, in i9xx_pipestat_irq_reset()
523 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
530 struct intel_display *display = &dev_priv->display; in i9xx_pipestat_irq_ack() local
536 !dev_priv->display.irq.vlv_display_irqs_enabled) { in i9xx_pipestat_irq_ack()
569 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
575 pipe_stats[pipe] = intel_de_read(display, reg) & status_mask; in i9xx_pipestat_irq_ack()
576 enable_mask = i915_pipestat_enable_mask(display, pipe); in i9xx_pipestat_irq_ack()
588 intel_de_write(display, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
589 intel_de_write(display, reg, enable_mask); in i9xx_pipestat_irq_ack()
598 struct intel_display *display = &dev_priv->display; in i915_pipestat_irq_handler() local
613 intel_cpu_fifo_underrun_irq_handler(display, pipe); in i915_pipestat_irq_handler()
617 intel_opregion_asle_intr(display); in i915_pipestat_irq_handler()
623 struct intel_display *display = &dev_priv->display; in i965_pipestat_irq_handler() local
638 intel_cpu_fifo_underrun_irq_handler(display, pipe); in i965_pipestat_irq_handler()
642 intel_opregion_asle_intr(display); in i965_pipestat_irq_handler()
645 intel_gmbus_irq_handler(display); in i965_pipestat_irq_handler()
651 struct intel_display *display = &dev_priv->display; in valleyview_pipestat_irq_handler() local
665 intel_cpu_fifo_underrun_irq_handler(display, pipe); in valleyview_pipestat_irq_handler()
669 intel_gmbus_irq_handler(display); in valleyview_pipestat_irq_handler()
674 struct intel_display *display = &dev_priv->display; in ibx_irq_handler() local
688 intel_dp_aux_irq_handler(display); in ibx_irq_handler()
691 intel_gmbus_irq_handler(display); in ibx_irq_handler()
706 intel_de_read(display, FDI_RX_IIR(pipe))); in ibx_irq_handler()
717 intel_pch_fifo_underrun_irq_handler(display, PIPE_A); in ibx_irq_handler()
720 intel_pch_fifo_underrun_irq_handler(display, PIPE_B); in ibx_irq_handler()
758 struct intel_display *display = &dev_priv->display; in ivb_err_int_handler() local
759 u32 err_int = intel_de_read(display, GEN7_ERR_INT); in ivb_err_int_handler()
766 drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); in ivb_err_int_handler()
769 drm_err_ratelimited(display->drm, "Invalid PTE data\n"); in ivb_err_int_handler()
775 intel_cpu_fifo_underrun_irq_handler(display, pipe); in ivb_err_int_handler()
786 intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers, in ivb_err_int_handler()
790 intel_de_write(display, GEN7_ERR_INT, err_int); in ivb_err_int_handler()
795 struct intel_display *display = &dev_priv->display; in cpt_serr_int_handler() local
796 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_serr_int_handler()
804 intel_pch_fifo_underrun_irq_handler(display, pipe); in cpt_serr_int_handler()
806 intel_de_write(display, SERR_INT, serr_int); in cpt_serr_int_handler()
811 struct intel_display *display = &dev_priv->display; in cpt_irq_handler() local
825 intel_dp_aux_irq_handler(display); in cpt_irq_handler()
828 intel_gmbus_irq_handler(display); in cpt_irq_handler()
840 intel_de_read(display, FDI_RX_IIR(pipe))); in cpt_irq_handler()
873 static void ilk_gtt_fault_irq_handler(struct intel_display *display) in ilk_gtt_fault_irq_handler() argument
878 gtt_fault = intel_de_read(display, ILK_GTT_FAULT); in ilk_gtt_fault_irq_handler()
879 intel_de_write(display, ILK_GTT_FAULT, gtt_fault); in ilk_gtt_fault_irq_handler()
882 drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); in ilk_gtt_fault_irq_handler()
885 drm_err_ratelimited(display->drm, "Invalid PTE data\n"); in ilk_gtt_fault_irq_handler()
887 for_each_pipe(display, pipe) { in ilk_gtt_fault_irq_handler()
892 intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers, in ilk_gtt_fault_irq_handler()
899 struct intel_display *display = &dev_priv->display; in ilk_display_irq_handler() local
907 intel_dp_aux_irq_handler(display); in ilk_display_irq_handler()
910 intel_opregion_asle_intr(display); in ilk_display_irq_handler()
916 ilk_gtt_fault_irq_handler(display); in ilk_display_irq_handler()
926 intel_cpu_fifo_underrun_irq_handler(display, pipe); in ilk_display_irq_handler()
934 u32 pch_iir = intel_de_read(display, SDEIIR); in ilk_display_irq_handler()
942 intel_de_write(display, SDEIIR, pch_iir); in ilk_display_irq_handler()
951 struct intel_display *display = &dev_priv->display; in ivb_display_irq_handler() local
968 psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0); in ivb_display_irq_handler()
975 intel_dp_aux_irq_handler(display); in ivb_display_irq_handler()
978 intel_opregion_asle_intr(display); in ivb_display_irq_handler()
990 u32 pch_iir = intel_de_read(display, SDEIIR); in ivb_display_irq_handler()
995 intel_de_write(display, SDEIIR, pch_iir); in ivb_display_irq_handler()
1045 struct intel_display *display = &dev_priv->display; in gen8_de_pipe_fault_mask() local
1047 if (DISPLAY_VER(display) >= 14) in gen8_de_pipe_fault_mask()
1057 else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) in gen8_de_pipe_fault_mask()
1065 else if (DISPLAY_VER(display) == 12) in gen8_de_pipe_fault_mask()
1075 else if (DISPLAY_VER(display) == 11) in gen8_de_pipe_fault_mask()
1084 else if (DISPLAY_VER(display) >= 9) in gen8_de_pipe_fault_mask()
1098 struct intel_display *display = to_intel_display(crtc); in handle_plane_ats_fault() local
1100 drm_err_ratelimited(display->drm, in handle_plane_ats_fault()
1109 struct intel_display *display = to_intel_display(crtc); in handle_pipedmc_ats_fault() local
1111 drm_err_ratelimited(display->drm, in handle_pipedmc_ats_fault()
1120 struct intel_display *display = to_intel_display(crtc); in handle_pipedmc_fault() local
1122 drm_err_ratelimited(display->drm, in handle_pipedmc_fault()
1184 gen8_pipe_fault_handlers(struct intel_display *display) in gen8_pipe_fault_handlers() argument
1186 if (DISPLAY_VER(display) >= 14) in gen8_pipe_fault_handlers()
1188 else if (DISPLAY_VER(display) >= 12) in gen8_pipe_fault_handlers()
1190 else if (DISPLAY_VER(display) >= 11) in gen8_pipe_fault_handlers()
1192 else if (DISPLAY_VER(display) >= 9) in gen8_pipe_fault_handlers()
1200 wake_up_all(&dev_priv->display.pmdemand.waitqueue); in intel_pmdemand_irq_handler()
1206 struct intel_display *display = &dev_priv->display; in gen8_de_misc_irq_handler() local
1209 if (HAS_DBUF_OVERLAP_DETECTION(display)) { in gen8_de_misc_irq_handler()
1211 drm_warn(display->drm, "DBuf overlap detected\n"); in gen8_de_misc_irq_handler()
1228 u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE); in gen8_de_misc_irq_handler()
1233 intel_opregion_asle_intr(display); in gen8_de_misc_irq_handler()
1251 psr_iir = intel_de_rmw(display, iir_reg, 0, 0); in gen8_de_misc_irq_handler()
1271 struct intel_display *display = &dev_priv->display; in gen11_dsi_te_interrupt_handler() local
1281 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0)); in gen11_dsi_te_interrupt_handler()
1293 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); in gen11_dsi_te_interrupt_handler()
1302 val = intel_de_read(display, TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); in gen11_dsi_te_interrupt_handler()
1322 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); in gen11_dsi_te_interrupt_handler()
1335 struct intel_display *display = &i915->display; in gen8_read_and_ack_pch_irqs() local
1339 *pch_iir = intel_de_read(display, SDEIIR); in gen8_read_and_ack_pch_irqs()
1351 pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0); in gen8_read_and_ack_pch_irqs()
1352 *pica_iir = intel_de_read(display, PICAINTERRUPT_IIR); in gen8_read_and_ack_pch_irqs()
1353 intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir); in gen8_read_and_ack_pch_irqs()
1356 intel_de_write(display, SDEIIR, *pch_iir); in gen8_read_and_ack_pch_irqs()
1359 intel_de_write(display, PICAINTERRUPT_IER, pica_ier); in gen8_read_and_ack_pch_irqs()
1364 struct intel_display *display = &dev_priv->display; in gen8_de_irq_handler() local
1371 iir = intel_de_read(display, GEN8_DE_MISC_IIR); in gen8_de_irq_handler()
1373 intel_de_write(display, GEN8_DE_MISC_IIR, iir); in gen8_de_irq_handler()
1382 iir = intel_de_read(display, GEN11_DE_HPD_IIR); in gen8_de_irq_handler()
1384 intel_de_write(display, GEN11_DE_HPD_IIR, iir); in gen8_de_irq_handler()
1393 iir = intel_de_read(display, GEN8_DE_PORT_IIR); in gen8_de_irq_handler()
1397 intel_de_write(display, GEN8_DE_PORT_IIR, iir); in gen8_de_irq_handler()
1400 intel_dp_aux_irq_handler(display); in gen8_de_irq_handler()
1422 intel_gmbus_irq_handler(display); in gen8_de_irq_handler()
1450 iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
1457 intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
1467 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); in gen8_de_irq_handler()
1470 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); in gen8_de_irq_handler()
1473 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); in gen8_de_irq_handler()
1480 intel_cpu_fifo_underrun_irq_handler(display, pipe); in gen8_de_irq_handler()
1484 intel_pipe_fault_irq_handler(display, in gen8_de_irq_handler()
1485 gen8_pipe_fault_handlers(display), in gen8_de_irq_handler()
1522 struct intel_display *display = &i915->display; in gen11_gu_misc_irq_ack() local
1528 iir = intel_de_read(display, GEN11_GU_MISC_IIR); in gen11_gu_misc_irq_ack()
1530 intel_de_write(display, GEN11_GU_MISC_IIR, iir); in gen11_gu_misc_irq_ack()
1537 struct intel_display *display = &i915->display; in gen11_gu_misc_irq_handler() local
1540 intel_opregion_asle_intr(display); in gen11_gu_misc_irq_handler()
1545 struct intel_display *display = &i915->display; in gen11_display_irq_handler() local
1551 * for the display related bits. in gen11_display_irq_handler()
1553 disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL); in gen11_display_irq_handler()
1555 intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); in gen11_display_irq_handler()
1557 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); in gen11_display_irq_handler()
1564 struct intel_display *display = &i915->display; in i915gm_irq_cstate_wa_enable() local
1573 if (i915->display.irq.vblank_enabled++ == 0) in i915gm_irq_cstate_wa_enable()
1574 intel_de_write(display, SCPD0, in i915gm_irq_cstate_wa_enable()
1580 struct intel_display *display = &i915->display; in i915gm_irq_cstate_wa_disable() local
1583 if (--i915->display.irq.vblank_enabled == 0) in i915gm_irq_cstate_wa_disable()
1584 intel_de_write(display, SCPD0, in i915gm_irq_cstate_wa_disable()
1705 struct intel_display *display = to_intel_display(intel_crtc); in gen11_dsi_configure_te() local
1718 intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT); in gen11_dsi_configure_te()
1720 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); in gen11_dsi_configure_te()
1727 struct intel_display *display = in intel_display_vblank_dc_work() local
1728 container_of(work, typeof(*display), irq.vblank_dc_work); in intel_display_vblank_dc_work()
1729 int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); in intel_display_vblank_dc_work()
1737 intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE : in intel_display_vblank_dc_work()
1744 struct intel_display *display = to_intel_display(crtc); in bdw_enable_vblank() local
1752 if (crtc->block_dc_for_vblank && display->irq.vblank_wa_num_pipes++ == 0) in bdw_enable_vblank()
1753 schedule_work(&display->irq.vblank_dc_work); in bdw_enable_vblank()
1771 struct intel_display *display = to_intel_display(crtc); in bdw_disable_vblank() local
1783 if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes == 0) in bdw_disable_vblank()
1784 schedule_work(&display->irq.vblank_dc_work); in bdw_disable_vblank()
1826 static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt) in vlv_page_table_error_irq_ack() argument
1830 tmp = intel_de_read(display, DPINVGTT); in vlv_page_table_error_irq_ack()
1839 * reset if the display power well goes down, so no need to in vlv_page_table_error_irq_ack()
1846 intel_de_write(display, DPINVGTT, status); in vlv_page_table_error_irq_ack()
1847 intel_de_write(display, DPINVGTT, enable << 16); in vlv_page_table_error_irq_ack()
1850 static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt) in vlv_page_table_error_irq_handler() argument
1854 for_each_pipe(display, pipe) { in vlv_page_table_error_irq_handler()
1859 intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers, in vlv_page_table_error_irq_handler()
1864 void vlv_display_error_irq_ack(struct intel_display *display, in vlv_display_error_irq_ack() argument
1869 *eir = intel_de_read(display, VLV_EIR); in vlv_display_error_irq_ack()
1872 vlv_page_table_error_irq_ack(display, dpinvgtt); in vlv_display_error_irq_ack()
1874 intel_de_write(display, VLV_EIR, *eir); in vlv_display_error_irq_ack()
1881 emr = intel_de_read(display, VLV_EMR); in vlv_display_error_irq_ack()
1882 intel_de_write(display, VLV_EMR, 0xffffffff); in vlv_display_error_irq_ack()
1883 intel_de_write(display, VLV_EMR, emr); in vlv_display_error_irq_ack()
1886 void vlv_display_error_irq_handler(struct intel_display *display, in vlv_display_error_irq_handler() argument
1889 drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir); in vlv_display_error_irq_handler()
1892 vlv_page_table_error_irq_handler(display, dpinvgtt); in vlv_display_error_irq_handler()
1897 struct intel_display *display = &dev_priv->display; in _vlv_display_irq_reset() local
1900 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); in _vlv_display_irq_reset()
1902 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); in _vlv_display_irq_reset()
1904 gen2_error_reset(to_intel_uncore(display->drm), in _vlv_display_irq_reset()
1908 intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0); in _vlv_display_irq_reset()
1912 intel_display_irq_regs_reset(display, VLV_IRQ_REGS); in _vlv_display_irq_reset()
1918 if (dev_priv->display.irq.vlv_display_irqs_enabled) in vlv_display_irq_reset()
1924 struct intel_display *display = &i915->display; in i9xx_display_irq_reset() local
1928 intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0); in i9xx_display_irq_reset()
1942 struct intel_display *display = &dev_priv->display; in vlv_display_irq_postinstall() local
1947 if (!dev_priv->display.irq.vlv_display_irqs_enabled) in vlv_display_irq_postinstall()
1951 intel_de_write(display, DPINVGTT, in vlv_display_irq_postinstall()
1955 intel_de_write(display, DPINVGTT, in vlv_display_irq_postinstall()
1959 gen2_error_init(to_intel_uncore(display->drm), in vlv_display_irq_postinstall()
1983 intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask); in vlv_display_irq_postinstall()
1988 struct intel_display *display = &dev_priv->display; in gen8_display_irq_reset() local
1994 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); in gen8_display_irq_reset()
1995 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); in gen8_display_irq_reset()
1998 if (intel_display_power_is_enabled(display, in gen8_display_irq_reset()
2000 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen8_display_irq_reset()
2002 intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); in gen8_display_irq_reset()
2003 intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); in gen8_display_irq_reset()
2008 struct intel_display *display = &dev_priv->display; in gen11_display_irq_reset() local
2016 intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); in gen11_display_irq_reset()
2025 if (!intel_display_power_is_enabled(display, domain)) in gen11_display_irq_reset()
2028 intel_de_write(display, in gen11_display_irq_reset()
2031 intel_de_write(display, in gen11_display_irq_reset()
2036 intel_de_write(display, EDP_PSR_IMR, 0xffffffff); in gen11_display_irq_reset()
2037 intel_de_write(display, EDP_PSR_IIR, 0xffffffff); in gen11_display_irq_reset()
2041 if (intel_display_power_is_enabled(display, in gen11_display_irq_reset()
2043 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen11_display_irq_reset()
2045 intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); in gen11_display_irq_reset()
2046 intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); in gen11_display_irq_reset()
2049 intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS); in gen11_display_irq_reset()
2051 intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); in gen11_display_irq_reset()
2054 intel_display_irq_regs_reset(display, SDE_IRQ_REGS); in gen11_display_irq_reset()
2060 struct intel_display *display = &dev_priv->display; in gen8_irq_power_well_post_enable() local
2073 intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), in gen8_irq_power_well_post_enable()
2074 dev_priv->display.irq.de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
2075 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
2083 struct intel_display *display = &dev_priv->display; in gen8_irq_power_well_pre_disable() local
2094 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen8_irq_power_well_pre_disable()
2098 /* make sure we're done processing display irqs */ in gen8_irq_power_well_pre_disable()
2115 struct intel_display *display = &dev_priv->display; in ibx_irq_postinstall() local
2128 intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); in ibx_irq_postinstall()
2135 if (dev_priv->display.irq.vlv_display_irqs_enabled) in valleyview_enable_display_irqs()
2138 dev_priv->display.irq.vlv_display_irqs_enabled = true; in valleyview_enable_display_irqs()
2150 if (!dev_priv->display.irq.vlv_display_irqs_enabled) in valleyview_disable_display_irqs()
2153 dev_priv->display.irq.vlv_display_irqs_enabled = false; in valleyview_disable_display_irqs()
2161 struct intel_display *display = &i915->display; in ilk_de_irq_postinstall() local
2186 intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); in ilk_de_irq_postinstall()
2197 intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask, in ilk_de_irq_postinstall()
2206 struct intel_display *display = &dev_priv->display; in gen8_de_irq_postinstall() local
2240 if (intel_bios_is_dsi_present(display, &port)) in gen8_de_irq_postinstall()
2244 if (HAS_DBUF_OVERLAP_DETECTION(display)) in gen8_de_irq_postinstall()
2269 if (!intel_display_power_is_enabled(display, domain)) in gen8_de_irq_postinstall()
2272 intel_display_irq_regs_assert_irr_is_zero(display, in gen8_de_irq_postinstall()
2276 intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); in gen8_de_irq_postinstall()
2280 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
2282 if (intel_display_power_is_enabled(display, in gen8_de_irq_postinstall()
2284 intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), in gen8_de_irq_postinstall()
2285 dev_priv->display.irq.de_irq_mask[pipe], in gen8_de_irq_postinstall()
2289 intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, in gen8_de_irq_postinstall()
2291 intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, in gen8_de_irq_postinstall()
2299 intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, in gen8_de_irq_postinstall()
2306 struct intel_display *display = &i915->display; in mtp_irq_postinstall() local
2312 intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, in mtp_irq_postinstall()
2315 intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); in mtp_irq_postinstall()
2320 struct intel_display *display = &dev_priv->display; in icp_irq_postinstall() local
2323 intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); in icp_irq_postinstall()
2328 struct intel_display *display = &dev_priv->display; in gen11_de_irq_postinstall() local
2335 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); in gen11_de_irq_postinstall()
2340 struct intel_display *display = &i915->display; in dg1_de_irq_postinstall() local
2346 intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); in dg1_de_irq_postinstall()
2355 INIT_WORK(&i915->display.irq.vblank_dc_work, in intel_display_irq_init()