41  * The i915 driver checks for display fifo underruns using the interrupt signals
43  * debug display issues, especially watermark settings.
58 static bool ivb_can_enable_err_int(struct intel_display *display)  in ivb_can_enable_err_int()  argument
60 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in ivb_can_enable_err_int()
66 	for_each_pipe(display, pipe) {  in ivb_can_enable_err_int()
67 		crtc = intel_crtc_for_pipe(display, pipe);  in ivb_can_enable_err_int()
76 static bool cpt_can_enable_serr_int(struct intel_display *display)  in cpt_can_enable_serr_int()  argument
78 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in cpt_can_enable_serr_int()
84 	for_each_pipe(display, pipe) {  in cpt_can_enable_serr_int()
85 		crtc = intel_crtc_for_pipe(display, pipe);  in cpt_can_enable_serr_int()
96 	struct intel_display *display = to_intel_display(crtc);  in i9xx_check_fifo_underruns()  local
98 	i915_reg_t reg = PIPESTAT(display, crtc->pipe);  in i9xx_check_fifo_underruns()
103 	if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)  in i9xx_check_fifo_underruns()
106 	enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);  in i9xx_check_fifo_underruns()
107 	intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);  in i9xx_check_fifo_underruns()
108 	intel_de_posting_read(display, reg);  in i9xx_check_fifo_underruns()
110 	trace_intel_cpu_fifo_underrun(display, crtc->pipe);  in i9xx_check_fifo_underruns()
111 	drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
114 static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,  in i9xx_set_fifo_underrun_reporting()  argument
118 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in i9xx_set_fifo_underrun_reporting()
119 	i915_reg_t reg = PIPESTAT(display, pipe);  in i9xx_set_fifo_underrun_reporting()
124 		u32 enable_mask = i915_pipestat_enable_mask(display, pipe);  in i9xx_set_fifo_underrun_reporting()
126 		intel_de_write(display, reg,  in i9xx_set_fifo_underrun_reporting()
128 		intel_de_posting_read(display, reg);  in i9xx_set_fifo_underrun_reporting()
130 		if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)  in i9xx_set_fifo_underrun_reporting()
131 			drm_err(display->drm, "pipe %c underrun\n",  in i9xx_set_fifo_underrun_reporting()
136 static void ilk_set_fifo_underrun_reporting(struct intel_display *display,  in ilk_set_fifo_underrun_reporting()  argument
139 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in ilk_set_fifo_underrun_reporting()
151 	struct intel_display *display = to_intel_display(crtc);  in ivb_check_fifo_underruns()  local
154 	u32 err_int = intel_de_read(display, GEN7_ERR_INT);  in ivb_check_fifo_underruns()
161 	intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_check_fifo_underruns()
162 	intel_de_posting_read(display, GEN7_ERR_INT);  in ivb_check_fifo_underruns()
164 	trace_intel_cpu_fifo_underrun(display, pipe);  in ivb_check_fifo_underruns()
165 	drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));  in ivb_check_fifo_underruns()
168 static void ivb_set_fifo_underrun_reporting(struct intel_display *display,  in ivb_set_fifo_underrun_reporting()  argument
172 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in ivb_set_fifo_underrun_reporting()
174 		intel_de_write(display, GEN7_ERR_INT,  in ivb_set_fifo_underrun_reporting()
177 		if (!ivb_can_enable_err_int(display))  in ivb_set_fifo_underrun_reporting()
185 		    intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {  in ivb_set_fifo_underrun_reporting()
186 			drm_err(display->drm,  in ivb_set_fifo_underrun_reporting()
193 static void bdw_set_fifo_underrun_reporting(struct intel_display *display,  in bdw_set_fifo_underrun_reporting()  argument
196 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in bdw_set_fifo_underrun_reporting()
204 static void ibx_set_fifo_underrun_reporting(struct intel_display *display,  in ibx_set_fifo_underrun_reporting()  argument
208 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in ibx_set_fifo_underrun_reporting()
220 	struct intel_display *display = to_intel_display(crtc);  in cpt_check_pch_fifo_underruns()  local
223 	u32 serr_int = intel_de_read(display, SERR_INT);  in cpt_check_pch_fifo_underruns()
230 	intel_de_write(display, SERR_INT,  in cpt_check_pch_fifo_underruns()
232 	intel_de_posting_read(display, SERR_INT);  in cpt_check_pch_fifo_underruns()
234 	trace_intel_pch_fifo_underrun(display, pch_transcoder);  in cpt_check_pch_fifo_underruns()
235 	drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",  in cpt_check_pch_fifo_underruns()
239 static void cpt_set_fifo_underrun_reporting(struct intel_display *display,  in cpt_set_fifo_underrun_reporting()  argument
243 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in cpt_set_fifo_underrun_reporting()
246 		intel_de_write(display, SERR_INT,  in cpt_set_fifo_underrun_reporting()
249 		if (!cpt_can_enable_serr_int(display))  in cpt_set_fifo_underrun_reporting()
256 		if (old && intel_de_read(display, SERR_INT) &  in cpt_set_fifo_underrun_reporting()
258 			drm_err(display->drm,  in cpt_set_fifo_underrun_reporting()
265 static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,  in __intel_set_cpu_fifo_underrun_reporting()  argument
268 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in __intel_set_cpu_fifo_underrun_reporting()
269 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);  in __intel_set_cpu_fifo_underrun_reporting()
277 	if (HAS_GMCH(display))  in __intel_set_cpu_fifo_underrun_reporting()
278 		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
279 	else if (display->platform.ironlake || display->platform.sandybridge)  in __intel_set_cpu_fifo_underrun_reporting()
280 		ilk_set_fifo_underrun_reporting(display, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
281 	else if (DISPLAY_VER(display) == 7)  in __intel_set_cpu_fifo_underrun_reporting()
282 		ivb_set_fifo_underrun_reporting(display, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
283 	else if (DISPLAY_VER(display) >= 8)  in __intel_set_cpu_fifo_underrun_reporting()
284 		bdw_set_fifo_underrun_reporting(display, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
291  * @display: display device instance
305 bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,  in intel_set_cpu_fifo_underrun_reporting()  argument
308 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_set_cpu_fifo_underrun_reporting()
313 	ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);  in intel_set_cpu_fifo_underrun_reporting()
321  * @display: display device instance
333 bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,  in intel_set_pch_fifo_underrun_reporting()  argument
337 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_set_pch_fifo_underrun_reporting()
338 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder);  in intel_set_pch_fifo_underrun_reporting()
357 		ibx_set_fifo_underrun_reporting(display,  in intel_set_pch_fifo_underrun_reporting()
361 		cpt_set_fifo_underrun_reporting(display,  in intel_set_pch_fifo_underrun_reporting()
371  * @display: display device instance
378 void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,  in intel_cpu_fifo_underrun_irq_handler()  argument
381 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);  in intel_cpu_fifo_underrun_irq_handler()
388 	if (HAS_GMCH(display) &&  in intel_cpu_fifo_underrun_irq_handler()
392 	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {  in intel_cpu_fifo_underrun_irq_handler()
393 		trace_intel_cpu_fifo_underrun(display, pipe);  in intel_cpu_fifo_underrun_irq_handler()
395 		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()
398 	intel_fbc_handle_fifo_underrun_irq(display);  in intel_cpu_fifo_underrun_irq_handler()
403  * @display: display device instance
410 void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,  in intel_pch_fifo_underrun_irq_handler()  argument
413 	if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,  in intel_pch_fifo_underrun_irq_handler()
415 		trace_intel_pch_fifo_underrun(display, pch_transcoder);  in intel_pch_fifo_underrun_irq_handler()
416 		drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",  in intel_pch_fifo_underrun_irq_handler()
423  * @display: display device instance
430 void intel_check_cpu_fifo_underruns(struct intel_display *display)  in intel_check_cpu_fifo_underruns()  argument
432 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_check_cpu_fifo_underruns()
437 	for_each_intel_crtc(display->drm, crtc) {  in intel_check_cpu_fifo_underruns()
441 		if (HAS_GMCH(display))  in intel_check_cpu_fifo_underruns()
443 		else if (DISPLAY_VER(display) == 7)  in intel_check_cpu_fifo_underruns()
452  * @display: display device instance
458 void intel_check_pch_fifo_underruns(struct intel_display *display)  in intel_check_pch_fifo_underruns()  argument
460 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_check_pch_fifo_underruns()
465 	for_each_intel_crtc(display->drm, crtc) {  in intel_check_pch_fifo_underruns()
476 void intel_init_fifo_underrun_reporting(struct intel_display *display,  in intel_init_fifo_underrun_reporting()  argument
480 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_init_fifo_underrun_reporting()