Lines Matching full:display
201 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
212 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
227 * @display: display device instance
242 bool intel_display_power_is_enabled(struct intel_display *display, in intel_display_power_is_enabled() argument
245 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
249 ret = __intel_display_power_is_enabled(display, domain); in intel_display_power_is_enabled()
256 sanitize_target_dc_state(struct intel_display *display, in sanitize_target_dc_state() argument
259 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
283 * @display: display device
290 void intel_display_power_set_target_dc_state(struct intel_display *display, in intel_display_power_set_target_dc_state() argument
295 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_set_target_dc_state()
298 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); in intel_display_power_set_target_dc_state()
300 if (drm_WARN_ON(display->drm, !power_well)) in intel_display_power_set_target_dc_state()
303 state = sanitize_target_dc_state(display, state); in intel_display_power_set_target_dc_state()
308 dc_off_enabled = intel_power_well_is_enabled(display, power_well); in intel_display_power_set_target_dc_state()
314 intel_power_well_enable(display, power_well); in intel_display_power_set_target_dc_state()
319 intel_power_well_disable(display, power_well); in intel_display_power_set_target_dc_state()
339 struct intel_display *display = container_of(power_domains, in assert_async_put_domain_masks_disjoint() local
343 return !drm_WARN_ON(display->drm, in assert_async_put_domain_masks_disjoint()
352 struct intel_display *display = container_of(power_domains, in __async_put_domains_state_ok() local
361 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
366 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
375 struct intel_display *display = container_of(power_domains, in print_power_domains() local
380 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); in print_power_domains()
382 drm_dbg_kms(display->drm, "%s use_count %d\n", in print_power_domains()
390 struct intel_display *display = container_of(power_domains, in print_async_put_domains_state() local
394 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", in print_async_put_domains_state()
455 intel_display_power_grab_async_put_ref(struct intel_display *display, in intel_display_power_grab_async_put_ref() argument
458 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_grab_async_put_ref()
459 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_grab_async_put_ref()
485 __intel_display_power_get_domain(struct intel_display *display, in __intel_display_power_get_domain() argument
488 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_get_domain()
491 if (intel_display_power_grab_async_put_ref(display, domain)) in __intel_display_power_get_domain()
494 for_each_power_domain_well(display, power_well, domain) in __intel_display_power_get_domain()
495 intel_power_well_get(display, power_well); in __intel_display_power_get_domain()
502 * @display: display device instance
512 intel_wakeref_t intel_display_power_get(struct intel_display *display, in intel_display_power_get() argument
515 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_get()
516 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get()
520 __intel_display_power_get_domain(display, domain); in intel_display_power_get()
527 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
528 * @display: display device instance
539 intel_display_power_get_if_enabled(struct intel_display *display, in intel_display_power_get_if_enabled() argument
542 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_get_if_enabled()
543 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get_if_enabled()
553 if (__intel_display_power_is_enabled(display, domain)) { in intel_display_power_get_if_enabled()
554 __intel_display_power_get_domain(display, domain); in intel_display_power_get_if_enabled()
571 __intel_display_power_put_domain(struct intel_display *display, in __intel_display_power_put_domain() argument
574 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_domain()
579 drm_WARN(display->drm, !power_domains->domain_use_count[domain], in __intel_display_power_put_domain()
583 drm_WARN(display->drm, in __intel_display_power_put_domain()
590 for_each_power_domain_well_reverse(display, power_well, domain) in __intel_display_power_put_domain()
591 intel_power_well_put(display, power_well); in __intel_display_power_put_domain()
594 static void __intel_display_power_put(struct intel_display *display, in __intel_display_power_put() argument
597 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put()
600 __intel_display_power_put_domain(display, domain); in __intel_display_power_put()
609 struct intel_display *display = container_of(power_domains, in queue_async_put_domains_work() local
612 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in queue_async_put_domains_work()
614 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, in queue_async_put_domains_work()
623 struct intel_display *display = container_of(power_domains, in release_async_put_domains() local
626 struct drm_i915_private *dev_priv = to_i915(display->drm); in release_async_put_domains()
636 __intel_display_power_put_domain(display, domain); in release_async_put_domains()
645 struct intel_display *display = container_of(work, struct intel_display, in intel_display_power_put_async_work() local
647 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put_async_work()
648 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_put_async_work()
698 * @display: display device instance
709 void __intel_display_power_put_async(struct intel_display *display, in __intel_display_power_put_async() argument
714 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_display_power_put_async()
715 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_async()
724 __intel_display_power_put_domain(display, domain); in __intel_display_power_put_async()
729 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); in __intel_display_power_put_async()
755 * intel_display_power_flush_work - flushes the async display power disabling work
756 * @display: display device instance
766 void intel_display_power_flush_work(struct intel_display *display) in intel_display_power_flush_work() argument
768 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_flush_work()
769 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work()
793 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
794 * @display: display device instance
800 intel_display_power_flush_work_sync(struct intel_display *display) in intel_display_power_flush_work_sync() argument
802 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work_sync()
804 intel_display_power_flush_work(display); in intel_display_power_flush_work_sync()
809 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in intel_display_power_flush_work_sync()
815 * @display: display device instance
823 void intel_display_power_put(struct intel_display *display, in intel_display_power_put() argument
827 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put()
829 __intel_display_power_put(display, domain); in intel_display_power_put()
835 * @display: display device instance
846 void intel_display_power_put_unchecked(struct intel_display *display, in intel_display_power_put_unchecked() argument
849 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put_unchecked()
851 __intel_display_power_put(display, domain); in intel_display_power_put_unchecked()
857 intel_display_power_get_in_set(struct intel_display *display, in intel_display_power_get_in_set() argument
863 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set()
865 wf = intel_display_power_get(display, domain); in intel_display_power_get_in_set()
873 intel_display_power_get_in_set_if_enabled(struct intel_display *display, in intel_display_power_get_in_set_if_enabled() argument
879 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set_if_enabled()
881 wf = intel_display_power_get_if_enabled(display, domain); in intel_display_power_get_in_set_if_enabled()
894 intel_display_power_put_mask_in_set(struct intel_display *display, in intel_display_power_put_mask_in_set() argument
900 drm_WARN_ON(display->drm, in intel_display_power_put_mask_in_set()
909 intel_display_power_put(display, domain, wf); in intel_display_power_put_mask_in_set()
923 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) in get_allowed_dc_mask() argument
929 if (!HAS_DISPLAY(display)) in get_allowed_dc_mask()
932 if (DISPLAY_VER(display) >= 20) in get_allowed_dc_mask()
934 else if (display->platform.dg2) in get_allowed_dc_mask()
936 else if (display->platform.dg1) in get_allowed_dc_mask()
938 else if (DISPLAY_VER(display) >= 12) in get_allowed_dc_mask()
940 else if (display->platform.geminilake || display->platform.broxton) in get_allowed_dc_mask()
942 else if (DISPLAY_VER(display) >= 9) in get_allowed_dc_mask()
952 mask = display->platform.geminilake || display->platform.broxton || in get_allowed_dc_mask()
953 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; in get_allowed_dc_mask()
955 if (!display->params.disable_power_well) in get_allowed_dc_mask()
963 drm_dbg_kms(display->drm, in get_allowed_dc_mask()
968 drm_err(display->drm, in get_allowed_dc_mask()
988 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); in get_allowed_dc_mask()
995 * @display: display device instance
997 * Initializes the power domain structures for @display depending upon the
1000 int intel_power_domains_init(struct intel_display *display) in intel_power_domains_init() argument
1002 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init()
1004 display->params.disable_power_well = in intel_power_domains_init()
1005 sanitize_disable_power_well_option(display->params.disable_power_well); in intel_power_domains_init()
1007 get_allowed_dc_mask(display, display->params.enable_dc); in intel_power_domains_init()
1010 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); in intel_power_domains_init()
1022 * @display: display device instance
1026 void intel_power_domains_cleanup(struct intel_display *display) in intel_power_domains_cleanup() argument
1028 intel_display_power_map_cleanup(&display->power.domains); in intel_power_domains_cleanup()
1031 static void intel_power_domains_sync_hw(struct intel_display *display) in intel_power_domains_sync_hw() argument
1033 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sync_hw()
1037 for_each_power_well(display, power_well) in intel_power_domains_sync_hw()
1038 intel_power_well_sync_hw(display, power_well); in intel_power_domains_sync_hw()
1042 static void gen9_dbuf_slice_set(struct intel_display *display, in gen9_dbuf_slice_set() argument
1048 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, in gen9_dbuf_slice_set()
1050 intel_de_posting_read(display, reg); in gen9_dbuf_slice_set()
1053 state = intel_de_read(display, reg) & DBUF_POWER_STATE; in gen9_dbuf_slice_set()
1054 drm_WARN(display->drm, enable != state, in gen9_dbuf_slice_set()
1059 void gen9_dbuf_slices_update(struct intel_display *display, in gen9_dbuf_slices_update() argument
1062 struct i915_power_domains *power_domains = &display->power.domains; in gen9_dbuf_slices_update()
1063 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1066 drm_WARN(display->drm, req_slices & ~slice_mask, in gen9_dbuf_slices_update()
1070 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", in gen9_dbuf_slices_update()
1082 for_each_dbuf_slice(display, slice) in gen9_dbuf_slices_update()
1083 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); in gen9_dbuf_slices_update()
1085 display->dbuf.enabled_slices = req_slices; in gen9_dbuf_slices_update()
1090 static void gen9_dbuf_enable(struct intel_display *display) in gen9_dbuf_enable() argument
1094 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); in gen9_dbuf_enable()
1096 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; in gen9_dbuf_enable()
1098 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_enable()
1099 intel_pmdemand_program_dbuf(display, slices_mask); in gen9_dbuf_enable()
1105 gen9_dbuf_slices_update(display, slices_mask); in gen9_dbuf_enable()
1108 static void gen9_dbuf_disable(struct intel_display *display) in gen9_dbuf_disable() argument
1110 gen9_dbuf_slices_update(display, 0); in gen9_dbuf_disable()
1112 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_disable()
1113 intel_pmdemand_program_dbuf(display, 0); in gen9_dbuf_disable()
1116 static void gen12_dbuf_slices_config(struct intel_display *display) in gen12_dbuf_slices_config() argument
1120 for_each_dbuf_slice(display, slice) in gen12_dbuf_slices_config()
1121 intel_de_rmw(display, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
1126 static void icl_mbus_init(struct intel_display *display) in icl_mbus_init() argument
1128 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; in icl_mbus_init()
1131 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1148 if (DISPLAY_VER(display) == 12) in icl_mbus_init()
1152 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); in icl_mbus_init()
1155 static void hsw_assert_cdclk(struct intel_display *display) in hsw_assert_cdclk() argument
1157 u32 val = intel_de_read(display, LCPLL_CTL); in hsw_assert_cdclk()
1166 drm_err(display->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1169 drm_err(display->drm, "LCPLL is disabled\n"); in hsw_assert_cdclk()
1172 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); in hsw_assert_cdclk()
1175 static void assert_can_disable_lcpll(struct intel_display *display) in assert_can_disable_lcpll() argument
1177 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_can_disable_lcpll()
1180 for_each_intel_crtc(display->drm, crtc) in assert_can_disable_lcpll()
1181 INTEL_DISPLAY_STATE_WARN(display, crtc->active, in assert_can_disable_lcpll()
1185 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1186 "Display power well on\n"); in assert_can_disable_lcpll()
1187 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1188 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1190 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1191 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1193 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1194 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1196 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1197 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, in assert_can_disable_lcpll()
1199 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1200 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1202 if (display->platform.haswell) in assert_can_disable_lcpll()
1203 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1204 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1206 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1207 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
1209 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1210 …(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABL… in assert_can_disable_lcpll()
1212 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1213 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, in assert_can_disable_lcpll()
1222 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), in assert_can_disable_lcpll()
1226 static u32 hsw_read_dcomp(struct intel_display *display) in hsw_read_dcomp() argument
1228 if (display->platform.haswell) in hsw_read_dcomp()
1229 return intel_de_read(display, D_COMP_HSW); in hsw_read_dcomp()
1231 return intel_de_read(display, D_COMP_BDW); in hsw_read_dcomp()
1234 static void hsw_write_dcomp(struct intel_display *display, u32 val) in hsw_write_dcomp() argument
1236 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_write_dcomp()
1238 if (display->platform.haswell) { in hsw_write_dcomp()
1240 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); in hsw_write_dcomp()
1242 intel_de_write(display, D_COMP_BDW, val); in hsw_write_dcomp()
1243 intel_de_posting_read(display, D_COMP_BDW); in hsw_write_dcomp()
1249 * - Sequence for display software to disable LCPLL
1250 * - Sequence for display software to allow package C8+
1252 * register. Callers should take care of disabling all the display engine
1255 static void hsw_disable_lcpll(struct intel_display *display, in hsw_disable_lcpll() argument
1260 assert_can_disable_lcpll(display); in hsw_disable_lcpll()
1262 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1266 intel_de_write(display, LCPLL_CTL, val); in hsw_disable_lcpll()
1268 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in hsw_disable_lcpll()
1270 drm_err(display->drm, "Switching to FCLK failed\n"); in hsw_disable_lcpll()
1272 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1276 intel_de_write(display, LCPLL_CTL, val); in hsw_disable_lcpll()
1277 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1279 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) in hsw_disable_lcpll()
1280 drm_err(display->drm, "LCPLL still locked\n"); in hsw_disable_lcpll()
1282 val = hsw_read_dcomp(display); in hsw_disable_lcpll()
1284 hsw_write_dcomp(display, val); in hsw_disable_lcpll()
1287 if (wait_for((hsw_read_dcomp(display) & in hsw_disable_lcpll()
1289 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); in hsw_disable_lcpll()
1292 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); in hsw_disable_lcpll()
1293 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1301 static void hsw_restore_lcpll(struct intel_display *display) in hsw_restore_lcpll() argument
1303 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in hsw_restore_lcpll()
1306 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1320 intel_de_write(display, LCPLL_CTL, val); in hsw_restore_lcpll()
1321 intel_de_posting_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1324 val = hsw_read_dcomp(display); in hsw_restore_lcpll()
1327 hsw_write_dcomp(display, val); in hsw_restore_lcpll()
1329 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1331 intel_de_write(display, LCPLL_CTL, val); in hsw_restore_lcpll()
1333 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) in hsw_restore_lcpll()
1334 drm_err(display->drm, "LCPLL not locked yet\n"); in hsw_restore_lcpll()
1337 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); in hsw_restore_lcpll()
1339 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in hsw_restore_lcpll()
1341 drm_err(display->drm, in hsw_restore_lcpll()
1347 intel_update_cdclk(display); in hsw_restore_lcpll()
1348 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1371 * For more, read "Display Sequences for Package C8" on the hardware
1374 static void hsw_enable_pc8(struct intel_display *display) in hsw_enable_pc8() argument
1376 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_enable_pc8()
1378 drm_dbg_kms(display->drm, "Enabling package C8+\n"); in hsw_enable_pc8()
1381 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in hsw_enable_pc8()
1385 hsw_disable_lcpll(display, true, true); in hsw_enable_pc8()
1388 static void hsw_disable_pc8(struct intel_display *display) in hsw_disable_pc8() argument
1390 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_disable_pc8()
1392 drm_dbg_kms(display->drm, "Disabling package C8+\n"); in hsw_disable_pc8()
1394 hsw_restore_lcpll(display); in hsw_disable_pc8()
1397 /* Many display registers don't survive PC8+ */ in hsw_disable_pc8()
1403 static void intel_pch_reset_handshake(struct intel_display *display, in intel_pch_reset_handshake() argument
1409 if (display->platform.ivybridge) { in intel_pch_reset_handshake()
1417 if (DISPLAY_VER(display) >= 14) in intel_pch_reset_handshake()
1420 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); in intel_pch_reset_handshake()
1423 static void skl_display_core_init(struct intel_display *display, in skl_display_core_init() argument
1426 struct drm_i915_private *dev_priv = to_i915(display->drm); in skl_display_core_init()
1427 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_init()
1430 gen9_set_dc_state(display, DC_STATE_DISABLE); in skl_display_core_init()
1433 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); in skl_display_core_init()
1435 if (!HAS_DISPLAY(display)) in skl_display_core_init()
1441 well = lookup_power_well(display, SKL_DISP_PW_1); in skl_display_core_init()
1442 intel_power_well_enable(display, well); in skl_display_core_init()
1444 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); in skl_display_core_init()
1445 intel_power_well_enable(display, well); in skl_display_core_init()
1449 intel_cdclk_init_hw(display); in skl_display_core_init()
1451 gen9_dbuf_enable(display); in skl_display_core_init()
1454 intel_dmc_load_program(display); in skl_display_core_init()
1457 static void skl_display_core_uninit(struct intel_display *display) in skl_display_core_uninit() argument
1459 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_uninit()
1462 if (!HAS_DISPLAY(display)) in skl_display_core_uninit()
1465 gen9_disable_dc_states(display); in skl_display_core_uninit()
1468 gen9_dbuf_disable(display); in skl_display_core_uninit()
1470 intel_cdclk_uninit_hw(display); in skl_display_core_uninit()
1483 well = lookup_power_well(display, SKL_DISP_PW_1); in skl_display_core_uninit()
1484 intel_power_well_disable(display, well); in skl_display_core_uninit()
1491 static void bxt_display_core_init(struct intel_display *display, bool resume) in bxt_display_core_init() argument
1493 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_init()
1496 gen9_set_dc_state(display, DC_STATE_DISABLE); in bxt_display_core_init()
1504 intel_pch_reset_handshake(display, false); in bxt_display_core_init()
1506 if (!HAS_DISPLAY(display)) in bxt_display_core_init()
1512 well = lookup_power_well(display, SKL_DISP_PW_1); in bxt_display_core_init()
1513 intel_power_well_enable(display, well); in bxt_display_core_init()
1517 intel_cdclk_init_hw(display); in bxt_display_core_init()
1519 gen9_dbuf_enable(display); in bxt_display_core_init()
1522 intel_dmc_load_program(display); in bxt_display_core_init()
1525 static void bxt_display_core_uninit(struct intel_display *display) in bxt_display_core_uninit() argument
1527 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_uninit()
1530 if (!HAS_DISPLAY(display)) in bxt_display_core_uninit()
1533 gen9_disable_dc_states(display); in bxt_display_core_uninit()
1536 gen9_dbuf_disable(display); in bxt_display_core_uninit()
1538 intel_cdclk_uninit_hw(display); in bxt_display_core_uninit()
1549 well = lookup_power_well(display, SKL_DISP_PW_1); in bxt_display_core_uninit()
1550 intel_power_well_disable(display, well); in bxt_display_core_uninit()
1587 static void tgl_bw_buddy_init(struct intel_display *display) in tgl_bw_buddy_init() argument
1589 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_bw_buddy_init()
1593 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; in tgl_bw_buddy_init()
1597 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
1600 if (display->platform.alderlake_s || in tgl_bw_buddy_init()
1601 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) in tgl_bw_buddy_init()
1613 drm_dbg_kms(display->drm, in tgl_bw_buddy_init()
1616 intel_de_write(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1620 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), in tgl_bw_buddy_init()
1624 if (DISPLAY_VER(display) == 12) in tgl_bw_buddy_init()
1625 intel_de_rmw(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1632 static void icl_display_core_init(struct intel_display *display, in icl_display_core_init() argument
1635 struct drm_i915_private *dev_priv = to_i915(display->drm); in icl_display_core_init()
1636 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_init()
1639 gen9_set_dc_state(display, DC_STATE_DISABLE); in icl_display_core_init()
1644 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, in icl_display_core_init()
1648 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); in icl_display_core_init()
1650 if (!HAS_DISPLAY(display)) in icl_display_core_init()
1654 intel_combo_phy_init(display); in icl_display_core_init()
1661 well = lookup_power_well(display, SKL_DISP_PW_1); in icl_display_core_init()
1662 intel_power_well_enable(display, well); in icl_display_core_init()
1665 if (DISPLAY_VER(display) == 14) in icl_display_core_init()
1666 intel_de_rmw(display, DC_STATE_EN, in icl_display_core_init()
1670 intel_cdclk_init_hw(display); in icl_display_core_init()
1672 if (DISPLAY_VER(display) == 12 || display->platform.dg2) in icl_display_core_init()
1673 gen12_dbuf_slices_config(display); in icl_display_core_init()
1676 gen9_dbuf_enable(display); in icl_display_core_init()
1679 icl_mbus_init(display); in icl_display_core_init()
1682 if (DISPLAY_VER(display) >= 12) in icl_display_core_init()
1683 tgl_bw_buddy_init(display); in icl_display_core_init()
1686 if (display->platform.dg2) in icl_display_core_init()
1687 intel_snps_phy_wait_for_calibration(display); in icl_display_core_init()
1690 if (DISPLAY_VERx100(display) == 1401) in icl_display_core_init()
1691 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); in icl_display_core_init()
1694 intel_dmc_load_program(display); in icl_display_core_init()
1697 if (IS_DISPLAY_VERx100(display, 1200, 1300)) in icl_display_core_init()
1698 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, in icl_display_core_init()
1703 if (DISPLAY_VER(display) == 13) in icl_display_core_init()
1704 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); in icl_display_core_init()
1707 if (DISPLAY_VER(display) == 20) { in icl_display_core_init()
1708 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1710 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1715 static void icl_display_core_uninit(struct intel_display *display) in icl_display_core_uninit() argument
1717 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_uninit()
1720 if (!HAS_DISPLAY(display)) in icl_display_core_uninit()
1723 gen9_disable_dc_states(display); in icl_display_core_uninit()
1724 intel_dmc_disable_program(display); in icl_display_core_uninit()
1726 /* 1. Disable all display engine functions -> already done */ in icl_display_core_uninit()
1729 gen9_dbuf_disable(display); in icl_display_core_uninit()
1732 intel_cdclk_uninit_hw(display); in icl_display_core_uninit()
1734 if (DISPLAY_VER(display) == 14) in icl_display_core_uninit()
1735 intel_de_rmw(display, DC_STATE_EN, 0, in icl_display_core_uninit()
1744 well = lookup_power_well(display, SKL_DISP_PW_1); in icl_display_core_uninit()
1745 intel_power_well_disable(display, well); in icl_display_core_uninit()
1749 intel_combo_phy_uninit(display); in icl_display_core_uninit()
1752 static void chv_phy_control_init(struct intel_display *display) in chv_phy_control_init() argument
1755 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in chv_phy_control_init()
1757 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); in chv_phy_control_init()
1766 display->power.chv_phy_control = in chv_phy_control_init()
1780 if (intel_power_well_is_enabled(display, cmn_bc)) { in chv_phy_control_init()
1781 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); in chv_phy_control_init()
1788 display->power.chv_phy_control |= in chv_phy_control_init()
1791 display->power.chv_phy_control |= in chv_phy_control_init()
1798 display->power.chv_phy_control |= in chv_phy_control_init()
1801 display->power.chv_phy_control |= in chv_phy_control_init()
1804 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1806 display->power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1808 display->power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
1811 if (intel_power_well_is_enabled(display, cmn_d)) { in chv_phy_control_init()
1812 u32 status = intel_de_read(display, DPIO_PHY_STATUS); in chv_phy_control_init()
1820 display->power.chv_phy_control |= in chv_phy_control_init()
1823 display->power.chv_phy_control |= in chv_phy_control_init()
1826 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1828 display->power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1830 display->power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
1833 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", in chv_phy_control_init()
1834 display->power.chv_phy_control); in chv_phy_control_init()
1839 static void vlv_cmnlane_wa(struct intel_display *display) in vlv_cmnlane_wa() argument
1842 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in vlv_cmnlane_wa()
1844 lookup_power_well(display, VLV_DISP_PW_DISP2D); in vlv_cmnlane_wa()
1846 /* If the display might be already active skip this */ in vlv_cmnlane_wa()
1847 if (intel_power_well_is_enabled(display, cmn) && in vlv_cmnlane_wa()
1848 intel_power_well_is_enabled(display, disp2d) && in vlv_cmnlane_wa()
1849 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) in vlv_cmnlane_wa()
1852 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); in vlv_cmnlane_wa()
1855 intel_power_well_enable(display, disp2d); in vlv_cmnlane_wa()
1864 intel_power_well_disable(display, cmn); in vlv_cmnlane_wa()
1867 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) in vlv_punit_is_power_gated() argument
1869 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_punit_is_power_gated()
1879 static void assert_ved_power_gated(struct intel_display *display) in assert_ved_power_gated() argument
1881 drm_WARN(display->drm, in assert_ved_power_gated()
1882 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), in assert_ved_power_gated()
1886 static void assert_isp_power_gated(struct intel_display *display) in assert_isp_power_gated() argument
1894 drm_WARN(display->drm, !pci_dev_present(isp_ids) && in assert_isp_power_gated()
1895 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), in assert_isp_power_gated()
1899 static void intel_power_domains_verify_state(struct intel_display *display);
1903 * @display: display device instance
1917 void intel_power_domains_init_hw(struct intel_display *display, bool resume) in intel_power_domains_init_hw() argument
1919 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_init_hw()
1920 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init_hw()
1924 if (DISPLAY_VER(display) >= 11) { in intel_power_domains_init_hw()
1925 icl_display_core_init(display, resume); in intel_power_domains_init_hw()
1926 } else if (display->platform.geminilake || display->platform.broxton) { in intel_power_domains_init_hw()
1927 bxt_display_core_init(display, resume); in intel_power_domains_init_hw()
1928 } else if (DISPLAY_VER(display) == 9) { in intel_power_domains_init_hw()
1929 skl_display_core_init(display, resume); in intel_power_domains_init_hw()
1930 } else if (display->platform.cherryview) { in intel_power_domains_init_hw()
1932 chv_phy_control_init(display); in intel_power_domains_init_hw()
1934 assert_isp_power_gated(display); in intel_power_domains_init_hw()
1935 } else if (display->platform.valleyview) { in intel_power_domains_init_hw()
1937 vlv_cmnlane_wa(display); in intel_power_domains_init_hw()
1939 assert_ved_power_gated(display); in intel_power_domains_init_hw()
1940 assert_isp_power_gated(display); in intel_power_domains_init_hw()
1941 } else if (display->platform.broadwell || display->platform.haswell) { in intel_power_domains_init_hw()
1942 hsw_assert_cdclk(display); in intel_power_domains_init_hw()
1943 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); in intel_power_domains_init_hw()
1944 } else if (display->platform.ivybridge) { in intel_power_domains_init_hw()
1945 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); in intel_power_domains_init_hw()
1950 * initialization and to make sure we keep BIOS enabled display HW in intel_power_domains_init_hw()
1951 * resources powered until display HW readout is complete. We drop in intel_power_domains_init_hw()
1954 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_init_hw()
1956 intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_power_domains_init_hw()
1959 if (!display->params.disable_power_well) { in intel_power_domains_init_hw()
1960 drm_WARN_ON(display->drm, power_domains->disable_wakeref); in intel_power_domains_init_hw()
1961 display->power.domains.disable_wakeref = intel_display_power_get(display, in intel_power_domains_init_hw()
1964 intel_power_domains_sync_hw(display); in intel_power_domains_init_hw()
1971 * @display: display device instance
1973 * De-initializes the display power domain HW state. It also ensures that the
1980 void intel_power_domains_driver_remove(struct intel_display *display) in intel_power_domains_driver_remove() argument
1982 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_driver_remove()
1984 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_driver_remove()
1987 if (!display->params.disable_power_well) in intel_power_domains_driver_remove()
1988 intel_display_power_put(display, POWER_DOMAIN_INIT, in intel_power_domains_driver_remove()
1989 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_driver_remove()
1991 intel_display_power_flush_work_sync(display); in intel_power_domains_driver_remove()
1993 intel_power_domains_verify_state(display); in intel_power_domains_driver_remove()
2001 * @display: display device instance
2004 * The function will disable all display power wells that BIOS has enabled
2009 void intel_power_domains_sanitize_state(struct intel_display *display) in intel_power_domains_sanitize_state() argument
2011 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sanitize_state()
2016 for_each_power_well_reverse(display, power_well) { in intel_power_domains_sanitize_state()
2018 !intel_power_well_is_enabled(display, power_well)) in intel_power_domains_sanitize_state()
2021 drm_dbg_kms(display->drm, in intel_power_domains_sanitize_state()
2024 intel_power_well_disable(display, power_well); in intel_power_domains_sanitize_state()
2031 * intel_power_domains_enable - enable toggling of display power wells
2032 * @display: display device instance
2034 * Enable the ondemand enabling/disabling of the display power wells. Note that
2036 * only at specific points of the display modeset sequence, thus they are not
2039 * of display HW readout (which will acquire the power references reflecting
2042 void intel_power_domains_enable(struct intel_display *display) in intel_power_domains_enable() argument
2045 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_enable()
2047 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); in intel_power_domains_enable()
2048 intel_power_domains_verify_state(display); in intel_power_domains_enable()
2052 * intel_power_domains_disable - disable toggling of display power wells
2053 * @display: display device instance
2055 * Disable the ondemand enabling/disabling of the display power wells. See
2058 void intel_power_domains_disable(struct intel_display *display) in intel_power_domains_disable() argument
2060 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_disable()
2062 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_disable()
2064 intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_power_domains_disable()
2066 intel_power_domains_verify_state(display); in intel_power_domains_disable()
2071 * @display: display device instance
2080 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) in intel_power_domains_suspend() argument
2082 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_suspend()
2086 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); in intel_power_domains_suspend()
2096 intel_dmc_has_payload(display)) { in intel_power_domains_suspend()
2097 intel_display_power_flush_work(display); in intel_power_domains_suspend()
2098 intel_power_domains_verify_state(display); in intel_power_domains_suspend()
2106 if (!display->params.disable_power_well) in intel_power_domains_suspend()
2107 intel_display_power_put(display, POWER_DOMAIN_INIT, in intel_power_domains_suspend()
2108 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_suspend()
2110 intel_display_power_flush_work(display); in intel_power_domains_suspend()
2111 intel_power_domains_verify_state(display); in intel_power_domains_suspend()
2113 if (DISPLAY_VER(display) >= 11) in intel_power_domains_suspend()
2114 icl_display_core_uninit(display); in intel_power_domains_suspend()
2115 else if (display->platform.geminilake || display->platform.broxton) in intel_power_domains_suspend()
2116 bxt_display_core_uninit(display); in intel_power_domains_suspend()
2117 else if (DISPLAY_VER(display) == 9) in intel_power_domains_suspend()
2118 skl_display_core_uninit(display); in intel_power_domains_suspend()
2125 * @display: display device instance
2133 void intel_power_domains_resume(struct intel_display *display) in intel_power_domains_resume() argument
2135 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_resume()
2138 intel_power_domains_init_hw(display, true); in intel_power_domains_resume()
2141 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_resume()
2143 intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_power_domains_resume()
2146 intel_power_domains_verify_state(display); in intel_power_domains_resume()
2151 static void intel_power_domains_dump_info(struct intel_display *display) in intel_power_domains_dump_info() argument
2153 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_dump_info()
2156 for_each_power_well(display, power_well) { in intel_power_domains_dump_info()
2159 drm_dbg_kms(display->drm, "%-25s %d\n", in intel_power_domains_dump_info()
2163 drm_dbg_kms(display->drm, " %-23s %d\n", in intel_power_domains_dump_info()
2171 * @display: display device instance
2179 static void intel_power_domains_verify_state(struct intel_display *display) in intel_power_domains_verify_state() argument
2181 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_verify_state()
2190 for_each_power_well(display, power_well) { in intel_power_domains_verify_state()
2195 enabled = intel_power_well_is_enabled(display, power_well); in intel_power_domains_verify_state()
2199 drm_err(display->drm, in intel_power_domains_verify_state()
2209 drm_err(display->drm, in intel_power_domains_verify_state()
2223 intel_power_domains_dump_info(display); in intel_power_domains_verify_state()
2233 static void intel_power_domains_verify_state(struct intel_display *display) in intel_power_domains_verify_state() argument
2239 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) in intel_display_power_suspend_late() argument
2241 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_suspend_late()
2243 intel_power_domains_suspend(display, s2idle); in intel_display_power_suspend_late()
2245 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_suspend_late()
2246 display->platform.broxton) { in intel_display_power_suspend_late()
2247 bxt_enable_dc9(display); in intel_display_power_suspend_late()
2248 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend_late()
2249 hsw_enable_pc8(display); in intel_display_power_suspend_late()
2257 void intel_display_power_resume_early(struct intel_display *display) in intel_display_power_resume_early() argument
2259 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_resume_early()
2261 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_resume_early()
2262 display->platform.broxton) { in intel_display_power_resume_early()
2263 gen9_sanitize_dc_state(display); in intel_display_power_resume_early()
2264 bxt_disable_dc9(display); in intel_display_power_resume_early()
2265 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume_early()
2266 hsw_disable_pc8(display); in intel_display_power_resume_early()
2273 intel_power_domains_resume(display); in intel_display_power_resume_early()
2276 void intel_display_power_suspend(struct intel_display *display) in intel_display_power_suspend() argument
2278 if (DISPLAY_VER(display) >= 11) { in intel_display_power_suspend()
2279 icl_display_core_uninit(display); in intel_display_power_suspend()
2280 bxt_enable_dc9(display); in intel_display_power_suspend()
2281 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_suspend()
2282 bxt_display_core_uninit(display); in intel_display_power_suspend()
2283 bxt_enable_dc9(display); in intel_display_power_suspend()
2284 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend()
2285 hsw_enable_pc8(display); in intel_display_power_suspend()
2289 void intel_display_power_resume(struct intel_display *display) in intel_display_power_resume() argument
2291 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_resume()
2293 if (DISPLAY_VER(display) >= 11) { in intel_display_power_resume()
2294 bxt_disable_dc9(display); in intel_display_power_resume()
2295 icl_display_core_init(display, true); in intel_display_power_resume()
2296 if (intel_dmc_has_payload(display)) { in intel_display_power_resume()
2298 skl_enable_dc6(display); in intel_display_power_resume()
2300 gen9_enable_dc5(display); in intel_display_power_resume()
2302 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_resume()
2303 bxt_disable_dc9(display); in intel_display_power_resume()
2304 bxt_display_core_init(display, true); in intel_display_power_resume()
2305 if (intel_dmc_has_payload(display) && in intel_display_power_resume()
2307 gen9_enable_dc5(display); in intel_display_power_resume()
2308 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume()
2309 hsw_disable_pc8(display); in intel_display_power_resume()
2313 void intel_display_power_debug(struct intel_display *display, struct seq_file *m) in intel_display_power_debug() argument
2315 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_debug()
2463 intel_port_domains_for_platform(struct intel_display *display, in intel_port_domains_for_platform() argument
2467 if (DISPLAY_VER(display) >= 13) { in intel_port_domains_for_platform()
2470 } else if (DISPLAY_VER(display) >= 12) { in intel_port_domains_for_platform()
2473 } else if (DISPLAY_VER(display) >= 11) { in intel_port_domains_for_platform()
2483 intel_port_domains_for_port(struct intel_display *display, enum port port) in intel_port_domains_for_port() argument
2489 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_port()
2498 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port) in intel_display_power_ddi_io_domain() argument
2500 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_io_domain()
2502 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_io_domain()
2509 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port) in intel_display_power_ddi_lanes_domain() argument
2511 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_lanes_domain()
2513 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_lanes_domain()
2520 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) in intel_port_domains_for_aux_ch() argument
2526 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_aux_ch()
2535 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch) in intel_display_power_aux_io_domain() argument
2537 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_aux_io_domain()
2539 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) in intel_display_power_aux_io_domain()
2546 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch) in intel_display_power_legacy_aux_domain() argument
2548 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_legacy_aux_domain()
2550 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) in intel_display_power_legacy_aux_domain()
2557 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch) in intel_display_power_tbt_aux_domain() argument
2559 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_tbt_aux_domain()
2561 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) in intel_display_power_tbt_aux_domain()