Lines Matching full:display
28 * compressing the amount of memory used by the display. It is total
33 * and having fewer memory pages opened and accessed for refreshing the display.
95 struct intel_display *display; member
159 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
173 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
187 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
196 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
197 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
204 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride() local
209 return _intel_fbc_cfb_stride(display, cpp, width, stride); in intel_fbc_cfb_stride()
217 static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) in intel_fbc_max_cfb_height() argument
219 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
221 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_fbc_max_cfb_height()
227 static unsigned int _intel_fbc_cfb_size(struct intel_display *display, in _intel_fbc_cfb_size() argument
230 return min(height, intel_fbc_max_cfb_height(display)) * stride; in _intel_fbc_cfb_size()
235 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_size() local
238 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); in intel_fbc_cfb_size()
243 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_override_cfb_stride() local
256 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR)) in intel_fbc_override_cfb_stride()
262 static bool intel_fbc_has_fences(struct intel_display *display) in intel_fbc_has_fences() argument
264 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); in intel_fbc_has_fences()
271 struct intel_display *display = fbc->display; in i8xx_fbc_ctl() local
279 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
288 if (display->platform.i945gm) in i8xx_fbc_ctl()
313 struct intel_display *display = fbc->display; in i8xx_fbc_deactivate() local
317 fbc_ctl = intel_de_read(display, FBC_CONTROL); in i8xx_fbc_deactivate()
322 intel_de_write(display, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
325 if (intel_de_wait_for_clear(display, FBC_STATUS, in i8xx_fbc_deactivate()
327 drm_dbg_kms(display->drm, "FBC idle timed out\n"); in i8xx_fbc_deactivate()
334 struct intel_display *display = fbc->display; in i8xx_fbc_activate() local
340 intel_de_write(display, FBC_TAG(i), 0); in i8xx_fbc_activate()
342 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
343 intel_de_write(display, FBC_CONTROL2, in i8xx_fbc_activate()
345 intel_de_write(display, FBC_FENCE_OFF, in i8xx_fbc_activate()
349 intel_de_write(display, FBC_CONTROL, in i8xx_fbc_activate()
355 return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_is_active()
360 return intel_de_read(fbc->display, FBC_STATUS) & in i8xx_fbc_is_compressing()
366 struct intel_display *display = fbc->display; in i8xx_fbc_nuke() local
370 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), in i8xx_fbc_nuke()
371 intel_de_read_fw(display, DSPADDR(display, i9xx_plane))); in i8xx_fbc_nuke()
376 struct intel_display *display = fbc->display; in i8xx_fbc_program_cfb() local
377 struct drm_i915_private *i915 = to_i915(display->drm); in i8xx_fbc_program_cfb()
379 drm_WARN_ON(display->drm, in i8xx_fbc_program_cfb()
383 drm_WARN_ON(display->drm, in i8xx_fbc_program_cfb()
387 intel_de_write(display, FBC_CFB_BASE, in i8xx_fbc_program_cfb()
389 intel_de_write(display, FBC_LL_BASE, in i8xx_fbc_program_cfb()
404 struct intel_display *display = fbc->display; in i965_fbc_nuke() local
408 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in i965_fbc_nuke()
409 intel_de_read_fw(display, DSPSURF(display, i9xx_plane))); in i965_fbc_nuke()
438 struct intel_display *display = fbc->display; in g4x_dpfc_ctl() local
445 if (display->platform.g4x) in g4x_dpfc_ctl()
451 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
460 struct intel_display *display = fbc->display; in g4x_fbc_activate() local
463 intel_de_write(display, DPFC_FENCE_YOFF, in g4x_fbc_activate()
466 intel_de_write(display, DPFC_CONTROL, in g4x_fbc_activate()
472 struct intel_display *display = fbc->display; in g4x_fbc_deactivate() local
476 dpfc_ctl = intel_de_read(display, DPFC_CONTROL); in g4x_fbc_deactivate()
479 intel_de_write(display, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
485 return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_is_active()
490 return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK; in g4x_fbc_is_compressing()
495 struct intel_display *display = fbc->display; in g4x_fbc_program_cfb() local
497 intel_de_write(display, DPFC_CB_BASE, in g4x_fbc_program_cfb()
512 struct intel_display *display = fbc->display; in ilk_fbc_activate() local
515 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), in ilk_fbc_activate()
518 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), in ilk_fbc_activate()
524 struct intel_display *display = fbc->display; in ilk_fbc_deactivate() local
527 if (HAS_FBC_DIRTY_RECT(display)) in ilk_fbc_deactivate()
528 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); in ilk_fbc_deactivate()
531 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); in ilk_fbc_deactivate()
534 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); in ilk_fbc_deactivate()
540 return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; in ilk_fbc_is_active()
545 return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; in ilk_fbc_is_compressing()
550 struct intel_display *display = fbc->display; in ilk_fbc_program_cfb() local
552 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), in ilk_fbc_program_cfb()
567 struct intel_display *display = fbc->display; in snb_fbc_program_fence() local
574 intel_de_write(display, SNB_DPFC_CTL_SA, ctl); in snb_fbc_program_fence()
575 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); in snb_fbc_program_fence()
587 struct intel_display *display = fbc->display; in snb_fbc_nuke() local
589 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); in snb_fbc_nuke()
590 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id)); in snb_fbc_nuke()
604 struct intel_display *display = fbc->display; in glk_fbc_program_cfb_stride() local
612 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val); in glk_fbc_program_cfb_stride()
617 struct intel_display *display = fbc->display; in skl_fbc_program_cfb_stride() local
621 /* Display WA #0529: skl, kbl, bxt. */ in skl_fbc_program_cfb_stride()
626 intel_de_rmw(display, CHICKEN_MISC_4, in skl_fbc_program_cfb_stride()
633 struct intel_display *display = fbc->display; in ivb_dpfc_ctl() local
639 if (display->platform.ivybridge) in ivb_dpfc_ctl()
642 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
656 struct intel_display *display = fbc->display; in ivb_fbc_activate() local
659 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
661 else if (DISPLAY_VER(display) == 9) in ivb_fbc_activate()
664 if (intel_fbc_has_fences(display)) in ivb_fbc_activate()
669 if (DISPLAY_VER(display) >= 20) in ivb_fbc_activate()
670 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); in ivb_fbc_activate()
672 if (HAS_FBC_DIRTY_RECT(display)) in ivb_fbc_activate()
673 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), in ivb_fbc_activate()
676 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_activate()
682 return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; in ivb_fbc_is_compressing()
688 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_set_false_color()
733 struct intel_display *display = fbc->display; in intel_fbc_nuke() local
736 drm_WARN_ON(display->drm, fbc->flip_pending); in intel_fbc_nuke()
745 struct intel_display *display = fbc->display; in intel_fbc_activate() local
750 if (fbc->active && !intel_fbc_has_fences(display)) in intel_fbc_activate()
756 drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display)); in intel_fbc_activate()
774 static u64 intel_fbc_cfb_base_max(struct intel_display *display) in intel_fbc_cfb_base_max() argument
776 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_fbc_cfb_base_max()
782 static u64 intel_fbc_stolen_end(struct intel_display *display) in intel_fbc_stolen_end() argument
784 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); in intel_fbc_stolen_end()
791 if (display->platform.broadwell || in intel_fbc_stolen_end()
792 (DISPLAY_VER(display) == 9 && !display->platform.broxton)) in intel_fbc_stolen_end()
797 return min(end, intel_fbc_cfb_base_max(display)); in intel_fbc_stolen_end()
805 static int intel_fbc_max_limit(struct intel_display *display) in intel_fbc_max_limit() argument
808 if (display->platform.g4x) in intel_fbc_max_limit()
821 struct intel_display *display = fbc->display; in find_compression_limit() local
822 struct drm_i915_private *i915 = to_i915(display->drm); in find_compression_limit()
823 u64 end = intel_fbc_stolen_end(display); in find_compression_limit()
834 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { in find_compression_limit()
847 struct intel_display *display = fbc->display; in intel_fbc_alloc_cfb() local
848 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_alloc_cfb()
851 drm_WARN_ON(display->drm, in intel_fbc_alloc_cfb()
853 drm_WARN_ON(display->drm, in intel_fbc_alloc_cfb()
856 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) { in intel_fbc_alloc_cfb()
867 drm_info_once(display->drm, in intel_fbc_alloc_cfb()
872 drm_dbg_kms(display->drm, in intel_fbc_alloc_cfb()
882 drm_info_once(display->drm, in intel_fbc_alloc_cfb()
894 struct intel_display *display = fbc->display; in intel_fbc_program_workarounds() local
896 if (display->platform.skylake || display->platform.broxton) { in intel_fbc_program_workarounds()
899 * Display WA #0883: skl,bxt in intel_fbc_program_workarounds()
901 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
905 if (display->platform.skylake || display->platform.kabylake || in intel_fbc_program_workarounds()
906 display->platform.coffeelake || display->platform.cometlake) { in intel_fbc_program_workarounds()
909 * Display WA #0873: skl,kbl,cfl in intel_fbc_program_workarounds()
911 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
916 if (IS_DISPLAY_VER(display, 11, 12)) in intel_fbc_program_workarounds()
917 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
921 if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) in intel_fbc_program_workarounds()
922 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
928 struct intel_display *display = fbc->display; in __intel_fbc_cleanup_cfb() local
929 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_fbc_cleanup_cfb()
940 void intel_fbc_cleanup(struct intel_display *display) in intel_fbc_cleanup() argument
945 for_each_intel_fbc(display, fbc, fbc_id) { in intel_fbc_cleanup()
983 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ in skl_fbc_stride_is_valid()
997 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in stride_is_valid() local
999 if (DISPLAY_VER(display) >= 11) in stride_is_valid()
1001 else if (DISPLAY_VER(display) >= 9) in stride_is_valid()
1003 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in stride_is_valid()
1005 else if (DISPLAY_VER(display) == 4) in stride_is_valid()
1013 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in i8xx_fbc_pixel_format_is_valid() local
1023 if (DISPLAY_VER(display) == 2) in i8xx_fbc_pixel_format_is_valid()
1033 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in g4x_fbc_pixel_format_is_valid() local
1042 if (display->platform.g4x) in g4x_fbc_pixel_format_is_valid()
1068 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in pixel_format_is_valid() local
1070 if (DISPLAY_VER(display) >= 20) in pixel_format_is_valid()
1072 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in pixel_format_is_valid()
1102 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in rotation_is_valid() local
1104 if (DISPLAY_VER(display) >= 9) in rotation_is_valid()
1106 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in rotation_is_valid()
1112 static void intel_fbc_max_surface_size(struct intel_display *display, in intel_fbc_max_surface_size() argument
1115 if (DISPLAY_VER(display) >= 11) { in intel_fbc_max_surface_size()
1118 } else if (DISPLAY_VER(display) >= 10) { in intel_fbc_max_surface_size()
1121 } else if (DISPLAY_VER(display) >= 7) { in intel_fbc_max_surface_size()
1124 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { in intel_fbc_max_surface_size()
1135 * programmed as the display plane base address register. It does not look at
1141 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_surface_size_ok() local
1144 intel_fbc_max_surface_size(display, &max_w, &max_h); in intel_fbc_surface_size_ok()
1154 static void intel_fbc_max_plane_size(struct intel_display *display, in intel_fbc_max_plane_size() argument
1157 if (DISPLAY_VER(display) >= 10) { in intel_fbc_max_plane_size()
1160 } else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) { in intel_fbc_max_plane_size()
1163 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { in intel_fbc_max_plane_size()
1174 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_plane_size_valid() local
1177 intel_fbc_max_plane_size(display, &max_w, &max_h); in intel_fbc_plane_size_valid()
1199 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in tiling_is_valid() local
1201 if (DISPLAY_VER(display) >= 9) in tiling_is_valid()
1219 struct intel_display *display = fbc->display; in intel_fbc_program_dirty_rect() local
1221 drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0); in intel_fbc_program_dirty_rect()
1223 intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), in intel_fbc_program_dirty_rect()
1245 struct intel_display *display = to_intel_display(plane); in intel_fbc_dirty_rect_update_noarm() local
1248 if (!HAS_FBC_DIRTY_RECT(display)) in intel_fbc_dirty_rect_update_noarm()
1279 struct intel_display *display = to_intel_display(state->base.dev); in intel_fbc_update_state() local
1297 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && in intel_fbc_update_state()
1298 !intel_fbc_has_fences(display)); in intel_fbc_update_state()
1312 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_is_fence_ok() local
1326 return DISPLAY_VER(display) >= 9 || in intel_fbc_is_fence_ok()
1378 struct intel_display *display = to_intel_display(state); in intel_fbc_prepare_dirty_rect() local
1385 if (!HAS_FBC_DIRTY_RECT(display)) in intel_fbc_prepare_dirty_rect()
1407 struct intel_display *display = to_intel_display(state->base.dev); in intel_fbc_check_plane() local
1408 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_check_plane()
1429 if (!display->params.enable_fbc) { in intel_fbc_check_plane()
1445 if (i915_vtd_active(i915) && (display->platform.skylake || display->platform.broxton)) { in intel_fbc_check_plane()
1463 * Display 12+ is not supporting FBC with PSR2. in intel_fbc_check_plane()
1472 if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) && in intel_fbc_check_plane()
1479 if ((IS_DISPLAY_VER(display, 12, 13) || in intel_fbc_check_plane()
1480 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) && in intel_fbc_check_plane()
1506 if (DISPLAY_VER(display) < 20 && in intel_fbc_check_plane()
1528 if (DISPLAY_VER(display) >= 9 && in intel_fbc_check_plane()
1535 if (DISPLAY_VER(display) >= 11 && in intel_fbc_check_plane()
1543 if (display->platform.haswell || display->platform.broadwell) { in intel_fbc_check_plane()
1611 struct intel_display *display = to_intel_display(state->base.dev); in __intel_fbc_pre_update() local
1625 * Display WA #1198: glk+ in __intel_fbc_pre_update()
1637 if (fbc->activated && DISPLAY_VER(display) >= 10) in __intel_fbc_pre_update()
1671 struct intel_display *display = fbc->display; in __intel_fbc_disable() local
1675 drm_WARN_ON(display->drm, fbc->active); in __intel_fbc_disable()
1677 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", in __intel_fbc_disable()
1749 void intel_fbc_invalidate(struct intel_display *display, in intel_fbc_invalidate() argument
1756 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_invalidate()
1788 void intel_fbc_flush(struct intel_display *display, in intel_fbc_flush() argument
1795 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_flush()
1820 struct intel_display *display = to_intel_display(state->base.dev); in __intel_fbc_enable() local
1839 drm_WARN_ON(display->drm, fbc->active); in __intel_fbc_enable()
1861 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n", in __intel_fbc_enable()
1867 if (HAS_FBC_DIRTY_RECT(display)) in __intel_fbc_enable()
1882 struct intel_display *display = to_intel_display(crtc->base.dev); in intel_fbc_disable() local
1885 for_each_intel_plane(display->drm, plane) { in intel_fbc_disable()
1930 struct intel_display *display = fbc->display; in intel_fbc_underrun_work_fn() local
1938 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n"); in intel_fbc_underrun_work_fn()
1943 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe)); in intel_fbc_underrun_work_fn()
1951 struct intel_display *display = fbc->display; in __intel_fbc_reset_underrun() local
1958 drm_dbg_kms(display->drm, in __intel_fbc_reset_underrun()
1969 * @display: display
1974 void intel_fbc_reset_underrun(struct intel_display *display) in intel_fbc_reset_underrun() argument
1979 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_reset_underrun()
1985 struct drm_i915_private *i915 = to_i915(fbc->display->drm); in __intel_fbc_handle_fifo_underrun_irq()
2003 * @display: display
2015 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) in intel_fbc_handle_fifo_underrun_irq() argument
2020 for_each_intel_fbc(display, fbc, fbc_id) in intel_fbc_handle_fifo_underrun_irq()
2033 static int intel_sanitize_fbc_option(struct intel_display *display) in intel_sanitize_fbc_option() argument
2035 if (display->params.enable_fbc >= 0) in intel_sanitize_fbc_option()
2036 return !!display->params.enable_fbc; in intel_sanitize_fbc_option()
2038 if (!HAS_FBC(display)) in intel_sanitize_fbc_option()
2041 if (display->platform.broadwell || DISPLAY_VER(display) >= 9) in intel_sanitize_fbc_option()
2052 static struct intel_fbc *intel_fbc_create(struct intel_display *display, in intel_fbc_create() argument
2062 fbc->display = display; in intel_fbc_create()
2066 if (DISPLAY_VER(display) >= 7) in intel_fbc_create()
2068 else if (DISPLAY_VER(display) == 6) in intel_fbc_create()
2070 else if (DISPLAY_VER(display) == 5) in intel_fbc_create()
2072 else if (display->platform.g4x) in intel_fbc_create()
2074 else if (DISPLAY_VER(display) == 4) in intel_fbc_create()
2084 * @display: display
2088 void intel_fbc_init(struct intel_display *display) in intel_fbc_init() argument
2092 display->params.enable_fbc = intel_sanitize_fbc_option(display); in intel_fbc_init()
2093 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n", in intel_fbc_init()
2094 display->params.enable_fbc); in intel_fbc_init()
2096 for_each_fbc_id(display, fbc_id) in intel_fbc_init()
2097 display->fbc[fbc_id] = intel_fbc_create(display, fbc_id); in intel_fbc_init()
2102 * @display: display
2108 void intel_fbc_sanitize(struct intel_display *display) in intel_fbc_sanitize() argument
2113 for_each_intel_fbc(display, fbc, fbc_id) { in intel_fbc_sanitize()
2122 struct intel_display *display = fbc->display; in intel_fbc_debugfs_status_show() local
2123 struct drm_i915_private *i915 = to_i915(display->drm); in intel_fbc_debugfs_status_show()
2127 drm_modeset_lock_all(display->drm); in intel_fbc_debugfs_status_show()
2140 for_each_intel_plane(display->drm, plane) { in intel_fbc_debugfs_status_show()
2156 drm_modeset_unlock_all(display->drm); in intel_fbc_debugfs_status_show()
2213 void intel_fbc_debugfs_register(struct intel_display *display) in intel_fbc_debugfs_register() argument
2215 struct drm_minor *minor = display->drm->primary; in intel_fbc_debugfs_register()
2218 fbc = display->fbc[INTEL_FBC_A]; in intel_fbc_debugfs_register()