Lines Matching full:display
112 static bool i9xx_plane_has_fbc(struct intel_display *display, in i9xx_plane_has_fbc() argument
115 if (!HAS_FBC(display)) in i9xx_plane_has_fbc()
118 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
120 else if (display->platform.ivybridge) in i9xx_plane_has_fbc()
123 else if (DISPLAY_VER(display) >= 4) in i9xx_plane_has_fbc()
129 static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, in i9xx_plane_fbc() argument
132 if (i9xx_plane_has_fbc(display, i9xx_plane)) in i9xx_plane_fbc()
133 return display->fbc[INTEL_FBC_A]; in i9xx_plane_fbc()
140 struct intel_display *display = to_intel_display(plane); in i9xx_plane_has_windowing() local
143 if (display->platform.cherryview) in i9xx_plane_has_windowing()
145 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in i9xx_plane_has_windowing()
147 else if (DISPLAY_VER(display) == 4) in i9xx_plane_has_windowing()
157 struct intel_display *display = to_intel_display(plane_state); in i9xx_plane_ctl() local
164 if (display->platform.g4x || display->platform.ironlake || in i9xx_plane_ctl()
165 display->platform.sandybridge || display->platform.ivybridge) in i9xx_plane_ctl()
213 if (DISPLAY_VER(display) >= 4 && in i9xx_plane_ctl()
228 struct intel_display *display = to_intel_display(plane_state); in i9xx_check_plane_surface() local
247 if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) { in i9xx_check_plane_surface()
248 drm_dbg_kms(display->drm, in i9xx_check_plane_surface()
256 if (DISPLAY_VER(display) >= 4) in i9xx_check_plane_surface()
273 if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { in i9xx_check_plane_surface()
279 drm_dbg_kms(display->drm, in i9xx_check_plane_surface()
280 "[PLANE:%d:%s] unable to find suitable display surface offset due to X-tiling\n", in i9xx_check_plane_surface()
298 if (!display->platform.haswell && !display->platform.broadwell) { in i9xx_check_plane_surface()
311 if (display->platform.haswell || display->platform.broadwell) { in i9xx_check_plane_surface()
312 drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095); in i9xx_check_plane_surface()
313 } else if (DISPLAY_VER(display) >= 4 && in i9xx_check_plane_surface()
315 drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095); in i9xx_check_plane_surface()
361 struct intel_display *display = to_intel_display(crtc_state); in i9xx_plane_ctl_crtc() local
371 if (DISPLAY_VER(display) < 5) in i9xx_plane_ctl_crtc()
429 struct intel_display *display = to_intel_display(plane); in i9xx_plane_update_noarm() local
432 intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane), in i9xx_plane_update_noarm()
435 if (DISPLAY_VER(display) < 4) { in i9xx_plane_update_noarm()
446 intel_de_write_fw(display, DSPPOS(display, i9xx_plane), in i9xx_plane_update_noarm()
448 intel_de_write_fw(display, DSPSIZE(display, i9xx_plane), in i9xx_plane_update_noarm()
458 struct intel_display *display = to_intel_display(plane); in i9xx_plane_update_arm() local
473 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
478 if (display->platform.cherryview && i9xx_plane == PLANE_B) { in i9xx_plane_update_arm()
484 intel_de_write_fw(display, PRIMPOS(display, i9xx_plane), in i9xx_plane_update_arm()
486 intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane), in i9xx_plane_update_arm()
488 intel_de_write_fw(display, in i9xx_plane_update_arm()
489 PRIMCNSTALPHA(display, i9xx_plane), 0); in i9xx_plane_update_arm()
492 if (display->platform.haswell || display->platform.broadwell) { in i9xx_plane_update_arm()
493 intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane), in i9xx_plane_update_arm()
495 } else if (DISPLAY_VER(display) >= 4) { in i9xx_plane_update_arm()
496 intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane), in i9xx_plane_update_arm()
498 intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane), in i9xx_plane_update_arm()
507 intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); in i9xx_plane_update_arm()
509 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
510 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in i9xx_plane_update_arm()
513 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), in i9xx_plane_update_arm()
536 struct intel_display *display = to_intel_display(plane); in i9xx_plane_disable_arm() local
552 intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
554 if (DISPLAY_VER(display) >= 4) in i9xx_plane_disable_arm()
555 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0); in i9xx_plane_disable_arm()
557 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0); in i9xx_plane_disable_arm()
564 struct intel_display *display = to_intel_display(plane); in g4x_primary_capture_error() local
567 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in g4x_primary_capture_error()
568 error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); in g4x_primary_capture_error()
569 error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane)); in g4x_primary_capture_error()
576 struct intel_display *display = to_intel_display(plane); in i965_plane_capture_error() local
579 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i965_plane_capture_error()
580 error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); in i965_plane_capture_error()
587 struct intel_display *display = to_intel_display(plane); in i8xx_plane_capture_error() local
590 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i8xx_plane_capture_error()
591 error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane)); in i8xx_plane_capture_error()
601 struct intel_display *display = to_intel_display(plane); in g4x_primary_async_flip() local
609 intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); in g4x_primary_async_flip()
611 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in g4x_primary_async_flip()
622 struct intel_display *display = to_intel_display(plane); in vlv_primary_async_flip() local
626 intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), in vlv_primary_async_flip()
722 struct intel_display *display = to_intel_display(plane); in i9xx_plane_get_hw_state() local
732 * display power wells. in i9xx_plane_get_hw_state()
735 wakeref = intel_display_power_get_if_enabled(display, power_domain); in i9xx_plane_get_hw_state()
739 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_plane_get_hw_state()
743 if (DISPLAY_VER(display) >= 5) in i9xx_plane_get_hw_state()
748 intel_display_power_put(display, power_domain, wakeref); in i9xx_plane_get_hw_state()
821 struct intel_display *display = to_intel_display(plane); in vlv_plane_min_alignment() local
827 if (intel_scanout_needs_vtd_wa(display)) in vlv_plane_min_alignment()
845 struct intel_display *display = to_intel_display(plane); in g4x_primary_min_alignment() local
850 if (intel_scanout_needs_vtd_wa(display)) in g4x_primary_min_alignment()
904 intel_primary_plane_create(struct intel_display *display, enum pipe pipe) in intel_primary_plane_create() argument
923 if (HAS_FBC(display) && DISPLAY_VER(display) < 4 && in intel_primary_plane_create()
924 INTEL_NUM_PIPES(display) == 2) in intel_primary_plane_create()
931 intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane); in intel_primary_plane_create()
933 if (display->platform.valleyview || display->platform.cherryview) { in intel_primary_plane_create()
936 } else if (DISPLAY_VER(display) >= 4) { in intel_primary_plane_create()
950 if (display->platform.ivybridge) { in intel_primary_plane_create()
962 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
967 if (display->platform.valleyview || display->platform.cherryview) in intel_primary_plane_create()
969 else if (display->platform.broadwell || display->platform.haswell) in intel_primary_plane_create()
971 else if (display->platform.ivybridge) in intel_primary_plane_create()
976 if (HAS_GMCH(display)) { in intel_primary_plane_create()
977 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
979 else if (DISPLAY_VER(display) == 3) in intel_primary_plane_create()
984 if (display->platform.broadwell || display->platform.haswell) in intel_primary_plane_create()
990 if (display->platform.valleyview || display->platform.cherryview) in intel_primary_plane_create()
992 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
994 else if (DISPLAY_VER(display) == 4) in intel_primary_plane_create()
1000 if (intel_scanout_needs_vtd_wa(display)) in intel_primary_plane_create()
1003 if (display->platform.i830 || display->platform.i845g) { in intel_primary_plane_create()
1013 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
1015 else if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
1020 if (HAS_ASYNC_FLIPS(display)) { in intel_primary_plane_create()
1021 if (display->platform.valleyview || display->platform.cherryview) { in intel_primary_plane_create()
1026 } else if (display->platform.broadwell) { in intel_primary_plane_create()
1032 } else if (DISPLAY_VER(display) >= 7) { in intel_primary_plane_create()
1037 } else if (DISPLAY_VER(display) >= 5) { in intel_primary_plane_create()
1045 modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); in intel_primary_plane_create()
1047 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
1048 ret = drm_universal_plane_init(display->drm, &plane->base, in intel_primary_plane_create()
1055 ret = drm_universal_plane_init(display->drm, &plane->base, in intel_primary_plane_create()
1068 if (display->platform.cherryview && pipe == PIPE_B) { in intel_primary_plane_create()
1072 } else if (DISPLAY_VER(display) >= 4) { in intel_primary_plane_create()
1079 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
1134 struct intel_display *display = to_intel_display(crtc); in i9xx_get_initial_plane_config() local
1147 drm_WARN_ON(display->drm, pipe != crtc->pipe); in i9xx_get_initial_plane_config()
1151 drm_dbg_kms(display->drm, "failed to alloc fb\n"); in i9xx_get_initial_plane_config()
1157 fb->dev = display->drm; in i9xx_get_initial_plane_config()
1159 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1161 if (DISPLAY_VER(display) >= 4) { in i9xx_get_initial_plane_config()
1171 if (display->platform.cherryview && in i9xx_get_initial_plane_config()
1179 if (display->platform.haswell || display->platform.broadwell) { in i9xx_get_initial_plane_config()
1180 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1181 DSPOFFSET(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1182 base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1183 } else if (DISPLAY_VER(display) >= 4) { in i9xx_get_initial_plane_config()
1185 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1186 DSPTILEOFF(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1188 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1189 DSPLINOFF(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1190 base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1193 base = intel_de_read(display, DSPADDR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1197 drm_WARN_ON(display->drm, offset != 0); in i9xx_get_initial_plane_config()
1199 val = intel_de_read(display, PIPESRC(display, pipe)); in i9xx_get_initial_plane_config()
1203 val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1210 drm_dbg_kms(display->drm, in i9xx_get_initial_plane_config()
1223 struct intel_display *display = to_intel_display(crtc); in i9xx_fixup_initial_plane_config() local
1242 if (DISPLAY_VER(display) >= 4) in i9xx_fixup_initial_plane_config()
1243 intel_de_write(display, DSPSURF(display, i9xx_plane), base); in i9xx_fixup_initial_plane_config()
1245 intel_de_write(display, DSPADDR(display, i9xx_plane), base); in i9xx_fixup_initial_plane_config()