Lines Matching full:display
55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
117 void (*get_cdclk)(struct intel_display *display,
119 void (*set_cdclk)(struct intel_display *display,
126 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
132 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
141 struct intel_display *display = to_intel_display(state); in intel_cdclk_modeset_calc_cdclk() local
143 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
146 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, in intel_cdclk_calc_voltage_level() argument
149 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
152 static void fixed_133mhz_get_cdclk(struct intel_display *display, in fixed_133mhz_get_cdclk() argument
158 static void fixed_200mhz_get_cdclk(struct intel_display *display, in fixed_200mhz_get_cdclk() argument
164 static void fixed_266mhz_get_cdclk(struct intel_display *display, in fixed_266mhz_get_cdclk() argument
170 static void fixed_333mhz_get_cdclk(struct intel_display *display, in fixed_333mhz_get_cdclk() argument
176 static void fixed_400mhz_get_cdclk(struct intel_display *display, in fixed_400mhz_get_cdclk() argument
182 static void fixed_450mhz_get_cdclk(struct intel_display *display, in fixed_450mhz_get_cdclk() argument
188 static void i85x_get_cdclk(struct intel_display *display, in i85x_get_cdclk() argument
191 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i85x_get_cdclk()
230 static void i915gm_get_cdclk(struct intel_display *display, in i915gm_get_cdclk() argument
233 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i915gm_get_cdclk()
254 static void i945gm_get_cdclk(struct intel_display *display, in i945gm_get_cdclk() argument
257 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i945gm_get_cdclk()
278 static unsigned int intel_hpll_vco(struct intel_display *display) in intel_hpll_vco() argument
322 if (display->platform.gm45) in intel_hpll_vco()
324 else if (display->platform.g45) in intel_hpll_vco()
326 else if (display->platform.i965gm) in intel_hpll_vco()
328 else if (display->platform.pineview) in intel_hpll_vco()
330 else if (display->platform.g33) in intel_hpll_vco()
335 tmp = intel_de_read(display, display->platform.pineview || in intel_hpll_vco()
336 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
340 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
343 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
348 static void g33_get_cdclk(struct intel_display *display, in g33_get_cdclk() argument
351 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in g33_get_cdclk()
360 cdclk_config->vco = intel_hpll_vco(display); in g33_get_cdclk()
391 drm_err(display->drm, in g33_get_cdclk()
397 static void pnv_get_cdclk(struct intel_display *display, in pnv_get_cdclk() argument
400 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in pnv_get_cdclk()
419 drm_err(display->drm, in pnv_get_cdclk()
420 "Unknown pnv display core clock 0x%04x\n", gcfgc); in pnv_get_cdclk()
431 static void i965gm_get_cdclk(struct intel_display *display, in i965gm_get_cdclk() argument
434 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i965gm_get_cdclk()
442 cdclk_config->vco = intel_hpll_vco(display); in i965gm_get_cdclk()
470 drm_err(display->drm, in i965gm_get_cdclk()
476 static void gm45_get_cdclk(struct intel_display *display, in gm45_get_cdclk() argument
479 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in gm45_get_cdclk()
483 cdclk_config->vco = intel_hpll_vco(display); in gm45_get_cdclk()
499 drm_err(display->drm, in gm45_get_cdclk()
507 static void hsw_get_cdclk(struct intel_display *display, in hsw_get_cdclk() argument
510 u32 lcpll = intel_de_read(display, LCPLL_CTL); in hsw_get_cdclk()
515 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
519 else if (display->platform.haswell_ult) in hsw_get_cdclk()
525 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) in vlv_calc_cdclk() argument
527 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_cdclk()
536 if (display->platform.valleyview && min_cdclk > freq_320) in vlv_calc_cdclk()
546 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) in vlv_calc_voltage_level() argument
548 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_voltage_level()
550 if (display->platform.valleyview) { in vlv_calc_voltage_level()
567 static void vlv_get_cdclk(struct intel_display *display, in vlv_get_cdclk() argument
570 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_get_cdclk()
586 if (display->platform.valleyview) in vlv_get_cdclk()
594 static void vlv_program_pfi_credits(struct intel_display *display) in vlv_program_pfi_credits() argument
596 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_program_pfi_credits()
599 if (display->platform.cherryview) in vlv_program_pfi_credits()
604 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
606 if (display->platform.cherryview) in vlv_program_pfi_credits()
618 intel_de_write(display, GCI_CONTROL, in vlv_program_pfi_credits()
621 intel_de_write(display, GCI_CONTROL, in vlv_program_pfi_credits()
628 drm_WARN_ON(display->drm, in vlv_program_pfi_credits()
629 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
632 static void vlv_set_cdclk(struct intel_display *display, in vlv_set_cdclk() argument
636 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_set_cdclk()
655 * issuing a modeset without actually changing any display after in vlv_set_cdclk()
656 * a system suspend. So grab the display core domain, which covers in vlv_set_cdclk()
659 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in vlv_set_cdclk()
673 drm_err(display->drm, in vlv_set_cdclk()
692 drm_err(display->drm, in vlv_set_cdclk()
702 * so that the core display fetch happens in time to avoid underruns. in vlv_set_cdclk()
715 intel_update_cdclk(display); in vlv_set_cdclk()
717 vlv_program_pfi_credits(display); in vlv_set_cdclk()
719 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in vlv_set_cdclk()
722 static void chv_set_cdclk(struct intel_display *display, in chv_set_cdclk() argument
726 struct drm_i915_private *dev_priv = to_i915(display->drm); in chv_set_cdclk()
744 * issuing a modeset without actually changing any display after in chv_set_cdclk()
745 * a system suspend. So grab the display core domain, which covers in chv_set_cdclk()
748 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in chv_set_cdclk()
758 drm_err(display->drm, in chv_set_cdclk()
764 intel_update_cdclk(display); in chv_set_cdclk()
766 vlv_program_pfi_credits(display); in chv_set_cdclk()
768 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in chv_set_cdclk()
798 static void bdw_get_cdclk(struct intel_display *display, in bdw_get_cdclk() argument
801 u32 lcpll = intel_de_read(display, LCPLL_CTL); in bdw_get_cdclk()
806 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
842 static void bdw_set_cdclk(struct intel_display *display, in bdw_set_cdclk() argument
846 struct drm_i915_private *dev_priv = to_i915(display->drm); in bdw_set_cdclk()
850 if (drm_WARN(display->drm, in bdw_set_cdclk()
851 (intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
861 drm_err(display->drm, in bdw_set_cdclk()
866 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
873 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
875 drm_err(display->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
877 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
880 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
883 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
885 drm_err(display->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
890 intel_de_write(display, CDCLK_FREQ, in bdw_set_cdclk()
893 intel_update_cdclk(display); in bdw_set_cdclk()
931 static void skl_dpll0_update(struct intel_display *display, in skl_dpll0_update() argument
939 val = intel_de_read(display, LCPLL1_CTL); in skl_dpll0_update()
943 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
946 val = intel_de_read(display, DPLL_CTRL1); in skl_dpll0_update()
948 if (drm_WARN_ON(display->drm, in skl_dpll0_update()
972 static void skl_get_cdclk(struct intel_display *display, in skl_get_cdclk() argument
977 skl_dpll0_update(display, cdclk_config); in skl_get_cdclk()
984 cdctl = intel_de_read(display, CDCLK_CTL); in skl_get_cdclk()
1039 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) in skl_set_preferred_cdclk_vco() argument
1041 bool changed = display->cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1043 display->cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1046 intel_update_max_cdclk(display); in skl_set_preferred_cdclk_vco()
1049 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) in skl_dpll0_link_rate() argument
1051 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1068 static void skl_dpll0_enable(struct intel_display *display, int vco) in skl_dpll0_enable() argument
1070 intel_de_rmw(display, DPLL_CTRL1, in skl_dpll0_enable()
1075 skl_dpll0_link_rate(display, vco)); in skl_dpll0_enable()
1076 intel_de_posting_read(display, DPLL_CTRL1); in skl_dpll0_enable()
1078 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_enable()
1081 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1082 drm_err(display->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1084 display->cdclk.hw.vco = vco; in skl_dpll0_enable()
1087 skl_set_preferred_cdclk_vco(display, vco); in skl_dpll0_enable()
1090 static void skl_dpll0_disable(struct intel_display *display) in skl_dpll0_disable() argument
1092 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_disable()
1095 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1096 drm_err(display->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1098 display->cdclk.hw.vco = 0; in skl_dpll0_disable()
1101 static u32 skl_cdclk_freq_sel(struct intel_display *display, in skl_cdclk_freq_sel() argument
1106 drm_WARN_ON(display->drm, in skl_cdclk_freq_sel()
1107 cdclk != display->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1108 drm_WARN_ON(display->drm, vco != 0); in skl_cdclk_freq_sel()
1124 static void skl_set_cdclk(struct intel_display *display, in skl_set_cdclk() argument
1128 struct drm_i915_private *dev_priv = to_i915(display->drm); in skl_set_cdclk()
1142 drm_WARN_ON_ONCE(display->drm, in skl_set_cdclk()
1143 display->platform.skylake && vco == 8640000); in skl_set_cdclk()
1150 drm_err(display->drm, in skl_set_cdclk()
1155 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); in skl_set_cdclk()
1157 if (display->cdclk.hw.vco != 0 && in skl_set_cdclk()
1158 display->cdclk.hw.vco != vco) in skl_set_cdclk()
1159 skl_dpll0_disable(display); in skl_set_cdclk()
1161 cdclk_ctl = intel_de_read(display, CDCLK_CTL); in skl_set_cdclk()
1163 if (display->cdclk.hw.vco != vco) { in skl_set_cdclk()
1164 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1167 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1170 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1172 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1173 intel_de_posting_read(display, CDCLK_CTL); in skl_set_cdclk()
1175 if (display->cdclk.hw.vco != vco) in skl_set_cdclk()
1176 skl_dpll0_enable(display, vco); in skl_set_cdclk()
1178 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1180 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1183 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1185 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1187 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1188 intel_de_posting_read(display, CDCLK_CTL); in skl_set_cdclk()
1194 intel_update_cdclk(display); in skl_set_cdclk()
1197 static void skl_sanitize_cdclk(struct intel_display *display) in skl_sanitize_cdclk() argument
1202 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1206 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1209 intel_update_cdclk(display); in skl_sanitize_cdclk()
1210 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1213 if (display->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1214 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1221 * enable display. Verify the same as well. in skl_sanitize_cdclk()
1223 cdctl = intel_de_read(display, CDCLK_CTL); in skl_sanitize_cdclk()
1225 skl_cdclk_decimal(display->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1231 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1234 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1236 display->cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1239 static void skl_cdclk_init_hw(struct intel_display *display) in skl_cdclk_init_hw() argument
1243 skl_sanitize_cdclk(display); in skl_cdclk_init_hw()
1245 if (display->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1246 display->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1251 if (display->cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1252 skl_set_preferred_cdclk_vco(display, in skl_cdclk_init_hw()
1253 display->cdclk.hw.vco); in skl_cdclk_init_hw()
1257 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1259 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1265 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1268 static void skl_cdclk_uninit_hw(struct intel_display *display) in skl_cdclk_uninit_hw() argument
1270 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw()
1276 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1517 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) in bxt_calc_cdclk() argument
1519 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk()
1523 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1527 drm_WARN(display->drm, 1, in bxt_calc_cdclk()
1529 min_cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk()
1533 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1535 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk_pll_vco()
1538 if (cdclk == display->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1542 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1544 return display->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1546 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1547 cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1639 static void icl_readout_refclk(struct intel_display *display, in icl_readout_refclk() argument
1642 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1660 static void bxt_de_pll_readout(struct intel_display *display, in bxt_de_pll_readout() argument
1665 if (display->platform.dg2) in bxt_de_pll_readout()
1667 else if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1668 icl_readout_refclk(display, cdclk_config); in bxt_de_pll_readout()
1672 val = intel_de_read(display, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1687 if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1690 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1695 static void bxt_get_cdclk(struct intel_display *display, in bxt_get_cdclk() argument
1702 bxt_de_pll_readout(display, cdclk_config); in bxt_get_cdclk()
1704 if (DISPLAY_VER(display) >= 12) in bxt_get_cdclk()
1706 else if (DISPLAY_VER(display) >= 11) in bxt_get_cdclk()
1716 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1736 if (HAS_CDCLK_SQUASH(display)) in bxt_get_cdclk()
1737 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); in bxt_get_cdclk()
1753 if (DISPLAY_VER(display) >= 20) in bxt_get_cdclk()
1754 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1760 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1763 static void bxt_de_pll_disable(struct intel_display *display) in bxt_de_pll_disable() argument
1765 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1768 if (intel_de_wait_for_clear(display, in bxt_de_pll_disable()
1770 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1772 display->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1775 static void bxt_de_pll_enable(struct intel_display *display, int vco) in bxt_de_pll_enable() argument
1777 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in bxt_de_pll_enable()
1779 intel_de_rmw(display, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1782 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1785 if (intel_de_wait_for_set(display, in bxt_de_pll_enable()
1787 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1789 display->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1792 static void icl_cdclk_pll_disable(struct intel_display *display) in icl_cdclk_pll_disable() argument
1794 intel_de_rmw(display, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
1798 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_disable()
1799 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1801 display->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1804 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) in icl_cdclk_pll_enable() argument
1806 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in icl_cdclk_pll_enable()
1810 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1813 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1816 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1817 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1819 display->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1822 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) in adlp_cdclk_pll_crawl() argument
1824 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1829 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1833 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1836 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
1838 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1841 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1843 display->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1846 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1848 if (DISPLAY_VER(display) >= 12) { in bxt_cdclk_cd2x_pipe()
1853 } else if (DISPLAY_VER(display) >= 11) { in bxt_cdclk_cd2x_pipe()
1866 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, in bxt_cdclk_cd2x_div_sel() argument
1872 drm_WARN_ON(display->drm, in bxt_cdclk_cd2x_div_sel()
1873 cdclk != display->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1874 drm_WARN_ON(display->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1887 static u16 cdclk_squash_waveform(struct intel_display *display, in cdclk_squash_waveform() argument
1890 const struct intel_cdclk_vals *table = display->cdclk.table; in cdclk_squash_waveform()
1893 if (cdclk == display->cdclk.hw.bypass) in cdclk_squash_waveform()
1897 if (table[i].refclk == display->cdclk.hw.ref && in cdclk_squash_waveform()
1901 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1902 cdclk, display->cdclk.hw.ref); in cdclk_squash_waveform()
1907 static void icl_cdclk_pll_update(struct intel_display *display, int vco) in icl_cdclk_pll_update() argument
1909 if (display->cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1910 display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1911 icl_cdclk_pll_disable(display); in icl_cdclk_pll_update()
1913 if (display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1914 icl_cdclk_pll_enable(display, vco); in icl_cdclk_pll_update()
1917 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) in bxt_cdclk_pll_update() argument
1919 if (display->cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1920 display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1921 bxt_de_pll_disable(display); in bxt_cdclk_pll_update()
1923 if (display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1924 bxt_de_pll_enable(display, vco); in bxt_cdclk_pll_update()
1927 static void dg2_cdclk_squash_program(struct intel_display *display, in dg2_cdclk_squash_program() argument
1936 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); in dg2_cdclk_squash_program()
1949 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) in mdclk_source_is_cdclk_pll() argument
1951 return DISPLAY_VER(display) >= 20; in mdclk_source_is_cdclk_pll()
1954 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) in xe2lpd_mdclk_source_sel() argument
1956 if (mdclk_source_is_cdclk_pll(display)) in xe2lpd_mdclk_source_sel()
1962 int intel_mdclk_cdclk_ratio(struct intel_display *display, in intel_mdclk_cdclk_ratio() argument
1965 if (mdclk_source_is_cdclk_pll(display)) in intel_mdclk_cdclk_ratio()
1972 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, in xe2lpd_mdclk_cdclk_ratio_program() argument
1975 struct drm_i915_private *i915 = to_i915(display->drm); in xe2lpd_mdclk_cdclk_ratio_program()
1978 intel_mdclk_cdclk_ratio(display, cdclk_config), in xe2lpd_mdclk_cdclk_ratio_program()
1982 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, in cdclk_compute_crawl_and_squash_midpoint() argument
1995 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) in cdclk_compute_crawl_and_squash_midpoint()
1998 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1999 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2016 if (drm_WARN_ON(display->drm, old_div != new_div)) in cdclk_compute_crawl_and_squash_midpoint()
2045 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
2047 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
2048 display->cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
2049 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2055 static bool pll_enable_wa_needed(struct intel_display *display) in pll_enable_wa_needed() argument
2057 return (DISPLAY_VERx100(display) == 2000 || in pll_enable_wa_needed()
2058 DISPLAY_VERx100(display) == 1400 || in pll_enable_wa_needed()
2059 display->platform.dg2) && in pll_enable_wa_needed()
2060 display->cdclk.hw.vco > 0; in pll_enable_wa_needed()
2063 static u32 bxt_cdclk_ctl(struct intel_display *display, in bxt_cdclk_ctl() argument
2072 waveform = cdclk_squash_waveform(display, cdclk); in bxt_cdclk_ctl()
2074 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2075 bxt_cdclk_cd2x_pipe(display, pipe); in bxt_cdclk_ctl()
2081 if ((display->platform.geminilake || display->platform.broxton) && in bxt_cdclk_ctl()
2085 if (DISPLAY_VER(display) >= 20) in bxt_cdclk_ctl()
2086 val |= xe2lpd_mdclk_source_sel(display); in bxt_cdclk_ctl()
2093 static void _bxt_set_cdclk(struct intel_display *display, in _bxt_set_cdclk() argument
2100 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2101 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { in _bxt_set_cdclk()
2102 if (display->cdclk.hw.vco != vco) in _bxt_set_cdclk()
2103 adlp_cdclk_pll_crawl(display, vco); in _bxt_set_cdclk()
2104 } else if (DISPLAY_VER(display) >= 11) { in _bxt_set_cdclk()
2106 if (pll_enable_wa_needed(display)) in _bxt_set_cdclk()
2107 dg2_cdclk_squash_program(display, 0); in _bxt_set_cdclk()
2109 icl_cdclk_pll_update(display, vco); in _bxt_set_cdclk()
2111 bxt_cdclk_pll_update(display, vco); in _bxt_set_cdclk()
2114 if (HAS_CDCLK_SQUASH(display)) { in _bxt_set_cdclk()
2115 u16 waveform = cdclk_squash_waveform(display, cdclk); in _bxt_set_cdclk()
2117 dg2_cdclk_squash_program(display, waveform); in _bxt_set_cdclk()
2120 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); in _bxt_set_cdclk()
2123 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); in _bxt_set_cdclk()
2126 static void bxt_set_cdclk(struct intel_display *display, in bxt_set_cdclk() argument
2130 struct drm_i915_private *dev_priv = to_i915(display->drm); in bxt_set_cdclk()
2137 * Display versions 14 and beyond do not follow the PUnit in bxt_set_cdclk()
2141 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) in bxt_set_cdclk()
2143 else if (DISPLAY_VER(display) >= 11) in bxt_set_cdclk()
2158 drm_err(display->drm, in bxt_set_cdclk()
2164 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) in bxt_set_cdclk()
2165 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2167 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, in bxt_set_cdclk()
2169 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); in bxt_set_cdclk()
2170 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2172 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2175 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) in bxt_set_cdclk()
2176 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2178 if (DISPLAY_VER(display) >= 14) in bxt_set_cdclk()
2181 * Display versions 14 and beyond in bxt_set_cdclk()
2183 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) in bxt_set_cdclk()
2186 if (DISPLAY_VER(display) < 11) { in bxt_set_cdclk()
2199 drm_err(display->drm, in bxt_set_cdclk()
2205 intel_update_cdclk(display); in bxt_set_cdclk()
2207 if (DISPLAY_VER(display) >= 11) in bxt_set_cdclk()
2212 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2215 static void bxt_sanitize_cdclk(struct intel_display *display) in bxt_sanitize_cdclk() argument
2220 intel_update_cdclk(display); in bxt_sanitize_cdclk()
2221 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2223 if (display->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2224 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2228 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2229 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2233 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_sanitize_cdclk()
2234 if (vco != display->cdclk.hw.vco) in bxt_sanitize_cdclk()
2242 cdctl = intel_de_read(display, CDCLK_CTL); in bxt_sanitize_cdclk()
2243 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2250 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); in bxt_sanitize_cdclk()
2251 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); in bxt_sanitize_cdclk()
2258 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2261 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2264 display->cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2267 static void bxt_cdclk_init_hw(struct intel_display *display) in bxt_cdclk_init_hw() argument
2271 bxt_sanitize_cdclk(display); in bxt_cdclk_init_hw()
2273 if (display->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2274 display->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2277 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2284 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); in bxt_cdclk_init_hw()
2285 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2287 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2289 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2292 static void bxt_cdclk_uninit_hw(struct intel_display *display) in bxt_cdclk_uninit_hw() argument
2294 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw()
2299 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2301 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2306 * @display: display instance
2308 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2310 * during the display core initialization sequence, after which the DMC will
2313 void intel_cdclk_init_hw(struct intel_display *display) in intel_cdclk_init_hw() argument
2315 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) in intel_cdclk_init_hw()
2316 bxt_cdclk_init_hw(display); in intel_cdclk_init_hw()
2317 else if (DISPLAY_VER(display) == 9) in intel_cdclk_init_hw()
2318 skl_cdclk_init_hw(display); in intel_cdclk_init_hw()
2323 * @display: display instance
2325 * Uninitialize CDCLK. This is done only during the display core
2328 void intel_cdclk_uninit_hw(struct intel_display *display) in intel_cdclk_uninit_hw() argument
2330 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) in intel_cdclk_uninit_hw()
2331 bxt_cdclk_uninit_hw(display); in intel_cdclk_uninit_hw()
2332 else if (DISPLAY_VER(display) == 9) in intel_cdclk_uninit_hw()
2333 skl_cdclk_uninit_hw(display); in intel_cdclk_uninit_hw()
2336 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, in intel_cdclk_can_crawl_and_squash() argument
2343 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2348 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_crawl_and_squash()
2351 old_waveform = cdclk_squash_waveform(display, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2352 new_waveform = cdclk_squash_waveform(display, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2358 static bool intel_cdclk_can_crawl(struct intel_display *display, in intel_cdclk_can_crawl() argument
2364 if (!HAS_CDCLK_CRAWL(display)) in intel_cdclk_can_crawl()
2380 static bool intel_cdclk_can_squash(struct intel_display *display, in intel_cdclk_can_squash() argument
2390 if (!HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_squash()
2419 * @display: display instance
2427 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, in intel_cdclk_can_cd2x_update() argument
2432 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) in intel_cdclk_can_cd2x_update()
2441 if (HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_cd2x_update()
2465 void intel_cdclk_dump_config(struct intel_display *display, in intel_cdclk_dump_config() argument
2469 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2475 static void intel_pcode_notify(struct intel_display *display, in intel_pcode_notify() argument
2482 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pcode_notify()
2486 if (!display->platform.dg2) in intel_pcode_notify()
2503 drm_err(display->drm, in intel_pcode_notify()
2504 "Failed to inform PCU about display config (err %d)\n", in intel_pcode_notify()
2508 static void intel_set_cdclk(struct intel_display *display, in intel_set_cdclk() argument
2514 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2517 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2520 intel_cdclk_dump_config(display, cdclk_config, context); in intel_set_cdclk()
2522 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2528 intel_audio_cdclk_change_pre(display); in intel_set_cdclk()
2535 mutex_lock(&display->gmbus.mutex); in intel_set_cdclk()
2536 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2540 &display->gmbus.mutex); in intel_set_cdclk()
2543 intel_cdclk_set_cdclk(display, cdclk_config, pipe); in intel_set_cdclk()
2545 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2550 mutex_unlock(&display->gmbus.mutex); in intel_set_cdclk()
2552 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2558 intel_audio_cdclk_change_post(display); in intel_set_cdclk()
2560 if (drm_WARN(display->drm, in intel_set_cdclk()
2561 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2563 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2564 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); in intel_set_cdclk()
2570 struct intel_display *display = to_intel_display(state); in intel_cdclk_pcode_pre_notify() local
2609 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2615 struct intel_display *display = to_intel_display(state); in intel_cdclk_pcode_post_notify() local
2646 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2671 struct intel_display *display = to_intel_display(state); in intel_set_cdclk_pre_plane_update() local
2683 if (display->platform.dg2) in intel_set_cdclk_pre_plane_update()
2708 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2710 intel_set_cdclk(display, &cdclk_config, pipe, in intel_set_cdclk_pre_plane_update()
2724 struct intel_display *display = to_intel_display(state); in intel_set_cdclk_post_plane_update() local
2735 if (display->platform.dg2) in intel_set_cdclk_post_plane_update()
2744 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2746 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, in intel_set_cdclk_post_plane_update()
2751 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) in intel_cdclk_ppc() argument
2753 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; in intel_cdclk_ppc()
2757 static int intel_cdclk_guardband(struct intel_display *display) in intel_cdclk_guardband() argument
2759 if (DISPLAY_VER(display) >= 9 || in intel_cdclk_guardband()
2760 display->platform.broadwell || display->platform.haswell) in intel_cdclk_guardband()
2762 else if (display->platform.cherryview) in intel_cdclk_guardband()
2770 struct intel_display *display = to_intel_display(crtc_state); in intel_pixel_rate_to_cdclk() local
2771 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); in intel_pixel_rate_to_cdclk()
2772 int guardband = intel_cdclk_guardband(display); in intel_pixel_rate_to_cdclk()
2781 struct intel_display *display = to_intel_display(crtc); in intel_planes_min_cdclk() local
2785 for_each_intel_plane_on_crtc(display->drm, crtc, plane) in intel_planes_min_cdclk()
2810 struct intel_display *display = to_intel_display(state); in intel_compute_min_cdclk() local
2811 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_compute_min_cdclk()
2854 for_each_pipe(display, pipe) in intel_compute_min_cdclk()
2865 if (display->platform.geminilake && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2869 if (min_cdclk > display->cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2870 drm_dbg_kms(display->drm, in intel_compute_min_cdclk()
2872 min_cdclk, display->cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2894 struct intel_display *display = to_intel_display(state); in bxt_compute_min_voltage_level() local
2922 for_each_pipe(display, pipe) in bxt_compute_min_voltage_level()
2931 struct intel_display *display = to_intel_display(state); in vlv_modeset_calc_cdclk() local
2940 cdclk = vlv_calc_cdclk(display, min_cdclk); in vlv_modeset_calc_cdclk()
2944 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2947 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2951 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2990 struct intel_display *display = to_intel_display(state); in skl_dpll0_vco() local
2999 vco = display->cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3061 struct intel_display *display = to_intel_display(state); in bxt_modeset_calc_cdclk() local
3074 cdclk = bxt_calc_cdclk(display, min_cdclk); in bxt_modeset_calc_cdclk()
3075 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3081 intel_cdclk_calc_voltage_level(display, cdclk)); in bxt_modeset_calc_cdclk()
3084 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3085 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3090 intel_cdclk_calc_voltage_level(display, cdclk); in bxt_modeset_calc_cdclk()
3142 struct intel_display *display = to_intel_display(state); in intel_atomic_get_cdclk_state() local
3145 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); in intel_atomic_get_cdclk_state()
3201 int intel_cdclk_init(struct intel_display *display) in intel_cdclk_init() argument
3209 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3215 static bool intel_cdclk_need_serialize(struct intel_display *display, in intel_cdclk_need_serialize() argument
3227 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed); in intel_cdclk_need_serialize()
3232 struct intel_display *display = to_intel_display(state); in intel_modeset_calc_cdclk() local
3251 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { in intel_modeset_calc_cdclk()
3271 intel_cdclk_can_cd2x_update(display, in intel_modeset_calc_cdclk()
3278 crtc = intel_crtc_for_pipe(display, pipe); in intel_modeset_calc_cdclk()
3288 if (intel_cdclk_can_crawl_and_squash(display, in intel_modeset_calc_cdclk()
3291 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3293 } else if (intel_cdclk_can_squash(display, in intel_modeset_calc_cdclk()
3296 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3298 } else if (intel_cdclk_can_crawl(display, in intel_modeset_calc_cdclk()
3301 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3306 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3318 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3322 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != in intel_modeset_calc_cdclk()
3323 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3324 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); in intel_modeset_calc_cdclk()
3331 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3335 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3343 void intel_cdclk_update_hw_state(struct intel_display *display) in intel_cdclk_update_hw_state() argument
3346 to_intel_cdclk_state(display->cdclk.obj.state); in intel_cdclk_update_hw_state()
3351 for_each_intel_crtc(display->drm, crtc) { in intel_cdclk_update_hw_state()
3366 struct intel_display *display = to_intel_display(crtc); in intel_cdclk_crtc_disable_noatomic() local
3368 intel_cdclk_update_hw_state(display); in intel_cdclk_crtc_disable_noatomic()
3371 static int intel_compute_max_dotclk(struct intel_display *display) in intel_compute_max_dotclk() argument
3373 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); in intel_compute_max_dotclk()
3374 int guardband = intel_cdclk_guardband(display); in intel_compute_max_dotclk()
3375 int max_cdclk_freq = display->cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3382 * @display: display instance
3388 void intel_update_max_cdclk(struct intel_display *display) in intel_update_max_cdclk() argument
3390 if (DISPLAY_VER(display) >= 30) { in intel_update_max_cdclk()
3391 display->cdclk.max_cdclk_freq = 691200; in intel_update_max_cdclk()
3392 } else if (display->platform.jasperlake || display->platform.elkhartlake) { in intel_update_max_cdclk()
3393 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3394 display->cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3396 display->cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3397 } else if (DISPLAY_VER(display) >= 11) { in intel_update_max_cdclk()
3398 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3399 display->cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3401 display->cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3402 } else if (display->platform.geminilake) { in intel_update_max_cdclk()
3403 display->cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3404 } else if (display->platform.broxton) { in intel_update_max_cdclk()
3405 display->cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3406 } else if (DISPLAY_VER(display) == 9) { in intel_update_max_cdclk()
3407 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
3410 vco = display->cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3411 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3427 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3428 } else if (display->platform.broadwell) { in intel_update_max_cdclk()
3435 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
3436 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3437 else if (display->platform.broadwell_ulx) in intel_update_max_cdclk()
3438 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3439 else if (display->platform.broadwell_ult) in intel_update_max_cdclk()
3440 display->cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3442 display->cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3443 } else if (display->platform.cherryview) { in intel_update_max_cdclk()
3444 display->cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3445 } else if (display->platform.valleyview) { in intel_update_max_cdclk()
3446 display->cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3449 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3452 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); in intel_update_max_cdclk()
3454 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3455 display->cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3457 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3458 display->cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3463 * @display: display instance
3467 void intel_update_cdclk(struct intel_display *display) in intel_update_cdclk() argument
3469 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
3477 if (display->platform.valleyview || display->platform.cherryview) in intel_update_cdclk()
3478 intel_de_write(display, GMBUSFREQ_VLV, in intel_update_cdclk()
3479 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3482 static int dg1_rawclk(struct intel_display *display) in dg1_rawclk() argument
3488 intel_de_write(display, PCH_RAWCLK_FREQ, in dg1_rawclk()
3494 static int cnp_rawclk(struct intel_display *display) in cnp_rawclk() argument
3496 struct drm_i915_private *dev_priv = to_i915(display->drm); in cnp_rawclk()
3500 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
3520 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
3524 static int pch_rawclk(struct intel_display *display) in pch_rawclk() argument
3526 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
3529 static int vlv_hrawclk(struct intel_display *display) in vlv_hrawclk() argument
3531 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_hrawclk()
3538 static int i9xx_hrawclk(struct intel_display *display) in i9xx_hrawclk() argument
3540 struct drm_i915_private *i915 = to_i915(display->drm); in i9xx_hrawclk()
3548 * @display: display instance
3553 u32 intel_read_rawclk(struct intel_display *display) in intel_read_rawclk() argument
3555 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_read_rawclk()
3566 freq = dg1_rawclk(display); in intel_read_rawclk()
3568 freq = cnp_rawclk(display); in intel_read_rawclk()
3570 freq = pch_rawclk(display); in intel_read_rawclk()
3571 else if (display->platform.valleyview || display->platform.cherryview) in intel_read_rawclk()
3572 freq = vlv_hrawclk(display); in intel_read_rawclk()
3573 else if (DISPLAY_VER(display) >= 3) in intel_read_rawclk()
3574 freq = i9xx_hrawclk(display); in intel_read_rawclk()
3584 struct intel_display *display = m->private; in i915_cdclk_info_show() local
3586 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); in i915_cdclk_info_show()
3587 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3588 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3595 void intel_cdclk_debugfs_register(struct intel_display *display) in intel_cdclk_debugfs_register() argument
3597 struct drm_minor *minor = display->drm->primary; in intel_cdclk_debugfs_register()
3600 display, &i915_cdclk_info_fops); in intel_cdclk_debugfs_register()
3748 * @display: display instance
3750 void intel_init_cdclk_hooks(struct intel_display *display) in intel_init_cdclk_hooks() argument
3752 if (DISPLAY_VER(display) >= 30) { in intel_init_cdclk_hooks()
3753 display->funcs.cdclk = &xe3lpd_cdclk_funcs; in intel_init_cdclk_hooks()
3754 display->cdclk.table = xe3lpd_cdclk_table; in intel_init_cdclk_hooks()
3755 } else if (DISPLAY_VER(display) >= 20) { in intel_init_cdclk_hooks()
3756 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3757 display->cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3758 } else if (DISPLAY_VERx100(display) >= 1401) { in intel_init_cdclk_hooks()
3759 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3760 display->cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3761 } else if (DISPLAY_VER(display) >= 14) { in intel_init_cdclk_hooks()
3762 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3763 display->cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3764 } else if (display->platform.dg2) { in intel_init_cdclk_hooks()
3765 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3766 display->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3767 } else if (display->platform.alderlake_p) { in intel_init_cdclk_hooks()
3769 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { in intel_init_cdclk_hooks()
3770 display->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3771 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3772 } else if (display->platform.alderlake_p_raptorlake_u) { in intel_init_cdclk_hooks()
3773 display->cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3774 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3776 display->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3777 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3779 } else if (display->platform.rocketlake) { in intel_init_cdclk_hooks()
3780 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3781 display->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3782 } else if (DISPLAY_VER(display) >= 12) { in intel_init_cdclk_hooks()
3783 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3784 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3785 } else if (display->platform.jasperlake || display->platform.elkhartlake) { in intel_init_cdclk_hooks()
3786 display->funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3787 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3788 } else if (DISPLAY_VER(display) >= 11) { in intel_init_cdclk_hooks()
3789 display->funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3790 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3791 } else if (display->platform.geminilake || display->platform.broxton) { in intel_init_cdclk_hooks()
3792 display->funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3793 if (display->platform.geminilake) in intel_init_cdclk_hooks()
3794 display->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3796 display->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3797 } else if (DISPLAY_VER(display) == 9) { in intel_init_cdclk_hooks()
3798 display->funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3799 } else if (display->platform.broadwell) { in intel_init_cdclk_hooks()
3800 display->funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3801 } else if (display->platform.haswell) { in intel_init_cdclk_hooks()
3802 display->funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3803 } else if (display->platform.cherryview) { in intel_init_cdclk_hooks()
3804 display->funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3805 } else if (display->platform.valleyview) { in intel_init_cdclk_hooks()
3806 display->funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3807 } else if (display->platform.sandybridge || display->platform.ivybridge) { in intel_init_cdclk_hooks()
3808 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3809 } else if (display->platform.ironlake) { in intel_init_cdclk_hooks()
3810 display->funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3811 } else if (display->platform.gm45) { in intel_init_cdclk_hooks()
3812 display->funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3813 } else if (display->platform.g45) { in intel_init_cdclk_hooks()
3814 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3815 } else if (display->platform.i965gm) { in intel_init_cdclk_hooks()
3816 display->funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3817 } else if (display->platform.i965g) { in intel_init_cdclk_hooks()
3818 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3819 } else if (display->platform.pineview) { in intel_init_cdclk_hooks()
3820 display->funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3821 } else if (display->platform.g33) { in intel_init_cdclk_hooks()
3822 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3823 } else if (display->platform.i945gm) { in intel_init_cdclk_hooks()
3824 display->funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3825 } else if (display->platform.i945g) { in intel_init_cdclk_hooks()
3826 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3827 } else if (display->platform.i915gm) { in intel_init_cdclk_hooks()
3828 display->funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3829 } else if (display->platform.i915g) { in intel_init_cdclk_hooks()
3830 display->funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3831 } else if (display->platform.i865g) { in intel_init_cdclk_hooks()
3832 display->funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3833 } else if (display->platform.i85x) { in intel_init_cdclk_hooks()
3834 display->funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3835 } else if (display->platform.i845g) { in intel_init_cdclk_hooks()
3836 display->funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3837 } else if (display->platform.i830) { in intel_init_cdclk_hooks()
3838 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3841 if (drm_WARN(display->drm, !display->funcs.cdclk, in intel_init_cdclk_hooks()
3843 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()