Lines Matching full:display
49 void (*sync_hw)(struct intel_display *display,
56 void (*enable)(struct intel_display *display,
62 void (*disable)(struct intel_display *display,
65 bool (*is_enabled)(struct intel_display *display,
76 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
81 for_each_power_well(display, power_well) in lookup_power_well()
88 * to abort things like display initialization sequences. Just return in lookup_power_well()
92 drm_WARN(display->drm, 1, in lookup_power_well()
95 return &display->power.domains.power_wells[0]; in lookup_power_well()
98 void intel_power_well_enable(struct intel_display *display, in intel_power_well_enable() argument
101 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); in intel_power_well_enable()
102 power_well->desc->ops->enable(display, power_well); in intel_power_well_enable()
106 void intel_power_well_disable(struct intel_display *display, in intel_power_well_disable() argument
109 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); in intel_power_well_disable()
111 power_well->desc->ops->disable(display, power_well); in intel_power_well_disable()
114 void intel_power_well_sync_hw(struct intel_display *display, in intel_power_well_sync_hw() argument
117 power_well->desc->ops->sync_hw(display, power_well); in intel_power_well_sync_hw()
118 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); in intel_power_well_sync_hw()
121 void intel_power_well_get(struct intel_display *display, in intel_power_well_get() argument
125 intel_power_well_enable(display, power_well); in intel_power_well_get()
128 void intel_power_well_put(struct intel_display *display, in intel_power_well_put() argument
131 drm_WARN(display->drm, !power_well->count, in intel_power_well_put()
136 intel_power_well_disable(display, power_well); in intel_power_well_put()
139 bool intel_power_well_is_enabled(struct intel_display *display, in intel_power_well_is_enabled() argument
142 return power_well->desc->ops->is_enabled(display, power_well); in intel_power_well_is_enabled()
150 bool intel_display_power_well_is_enabled(struct intel_display *display, in intel_display_power_well_is_enabled() argument
155 power_well = lookup_power_well(display, power_well_id); in intel_display_power_well_is_enabled()
157 return intel_power_well_is_enabled(display, power_well); in intel_display_power_well_is_enabled()
186 static void hsw_power_well_post_enable(struct intel_display *display, in hsw_power_well_post_enable() argument
189 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_power_well_post_enable()
192 intel_vga_reset_io_mem(display); in hsw_power_well_post_enable()
198 static void hsw_power_well_pre_disable(struct intel_display *display, in hsw_power_well_pre_disable() argument
201 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_power_well_pre_disable()
225 aux_ch_to_digital_port(struct intel_display *display, in aux_ch_to_digital_port() argument
230 for_each_intel_encoder(display->drm, encoder) { in aux_ch_to_digital_port()
246 static enum phy icl_aux_pw_to_phy(struct intel_display *display, in icl_aux_pw_to_phy() argument
250 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); in icl_aux_pw_to_phy()
262 static void hsw_wait_for_power_well_enable(struct intel_display *display, in hsw_wait_for_power_well_enable() argument
275 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { in hsw_wait_for_power_well_enable()
281 if (intel_de_wait_for_set(display, regs->driver, in hsw_wait_for_power_well_enable()
283 drm_dbg_kms(display->drm, "%s power well enable timeout\n", in hsw_wait_for_power_well_enable()
286 drm_WARN_ON(display->drm, !timeout_expected); in hsw_wait_for_power_well_enable()
291 static u32 hsw_power_well_requesters(struct intel_display *display, in hsw_power_well_requesters() argument
298 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
299 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
301 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
302 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
307 static void hsw_wait_for_power_well_disable(struct intel_display *display, in hsw_wait_for_power_well_disable() argument
324 wait_for((disabled = !(intel_de_read(display, regs->driver) & in hsw_wait_for_power_well_disable()
326 (reqs = hsw_power_well_requesters(display, regs, pw_idx)), 1); in hsw_wait_for_power_well_disable()
330 drm_dbg_kms(display->drm, in hsw_wait_for_power_well_disable()
336 static void gen9_wait_for_power_well_fuses(struct intel_display *display, in gen9_wait_for_power_well_fuses() argument
340 drm_WARN_ON(display->drm, in gen9_wait_for_power_well_fuses()
341 intel_de_wait_for_set(display, SKL_FUSE_STATUS, in gen9_wait_for_power_well_fuses()
345 static void hsw_power_well_enable(struct intel_display *display, in hsw_power_well_enable() argument
354 pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : in hsw_power_well_enable()
358 if (display->platform.alderlake_p && pg == SKL_PG1) in hsw_power_well_enable()
359 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); in hsw_power_well_enable()
369 gen9_wait_for_power_well_fuses(display, SKL_PG0); in hsw_power_well_enable()
372 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); in hsw_power_well_enable()
374 hsw_wait_for_power_well_enable(display, power_well, false); in hsw_power_well_enable()
379 pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : in hsw_power_well_enable()
381 gen9_wait_for_power_well_fuses(display, pg); in hsw_power_well_enable()
384 hsw_power_well_post_enable(display, in hsw_power_well_enable()
389 static void hsw_power_well_disable(struct intel_display *display, in hsw_power_well_disable() argument
395 hsw_power_well_pre_disable(display, in hsw_power_well_disable()
398 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); in hsw_power_well_disable()
399 hsw_wait_for_power_well_disable(display, power_well); in hsw_power_well_disable()
402 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) in intel_aux_ch_is_edp() argument
404 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); in intel_aux_ch_is_edp()
410 icl_combo_phy_aux_power_well_enable(struct intel_display *display, in icl_combo_phy_aux_power_well_enable() argument
416 drm_WARN_ON(display->drm, !display->platform.icelake); in icl_combo_phy_aux_power_well_enable()
418 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); in icl_combo_phy_aux_power_well_enable()
424 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), in icl_combo_phy_aux_power_well_enable()
427 hsw_wait_for_power_well_enable(display, power_well, false); in icl_combo_phy_aux_power_well_enable()
429 /* Display WA #1178: icl */ in icl_combo_phy_aux_power_well_enable()
431 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) in icl_combo_phy_aux_power_well_enable()
432 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), in icl_combo_phy_aux_power_well_enable()
437 icl_combo_phy_aux_power_well_disable(struct intel_display *display, in icl_combo_phy_aux_power_well_disable() argument
443 drm_WARN_ON(display->drm, !display->platform.icelake); in icl_combo_phy_aux_power_well_disable()
449 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), in icl_combo_phy_aux_power_well_disable()
452 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); in icl_combo_phy_aux_power_well_disable()
454 hsw_wait_for_power_well_disable(display, power_well); in icl_combo_phy_aux_power_well_disable()
459 static void icl_tc_port_assert_ref_held(struct intel_display *display, in icl_tc_port_assert_ref_held() argument
463 if (drm_WARN_ON(display->drm, !dig_port)) in icl_tc_port_assert_ref_held()
466 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) in icl_tc_port_assert_ref_held()
469 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); in icl_tc_port_assert_ref_held()
474 static void icl_tc_port_assert_ref_held(struct intel_display *display, in icl_tc_port_assert_ref_held() argument
484 static void icl_tc_cold_exit(struct intel_display *display) in icl_tc_cold_exit() argument
486 struct drm_i915_private *i915 = to_i915(display->drm); in icl_tc_cold_exit()
507 icl_tc_phy_aux_power_well_enable(struct intel_display *display, in icl_tc_phy_aux_power_well_enable() argument
511 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); in icl_tc_phy_aux_power_well_enable()
516 icl_tc_port_assert_ref_held(display, power_well, dig_port); in icl_tc_phy_aux_power_well_enable()
518 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), in icl_tc_phy_aux_power_well_enable()
521 intel_de_rmw(display, regs->driver, in icl_tc_phy_aux_power_well_enable()
531 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) in icl_tc_phy_aux_power_well_enable()
532 icl_tc_cold_exit(display); in icl_tc_phy_aux_power_well_enable()
534 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); in icl_tc_phy_aux_power_well_enable()
536 if (DISPLAY_VER(display) >= 12 && !is_tbt) { in icl_tc_phy_aux_power_well_enable()
541 if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) & in icl_tc_phy_aux_power_well_enable()
543 drm_warn(display->drm, in icl_tc_phy_aux_power_well_enable()
549 icl_aux_power_well_enable(struct intel_display *display, in icl_aux_power_well_enable() argument
552 enum phy phy = icl_aux_pw_to_phy(display, power_well); in icl_aux_power_well_enable()
554 if (intel_phy_is_tc(display, phy)) in icl_aux_power_well_enable()
555 return icl_tc_phy_aux_power_well_enable(display, power_well); in icl_aux_power_well_enable()
556 else if (display->platform.icelake) in icl_aux_power_well_enable()
557 return icl_combo_phy_aux_power_well_enable(display, in icl_aux_power_well_enable()
560 return hsw_power_well_enable(display, power_well); in icl_aux_power_well_enable()
564 icl_aux_power_well_disable(struct intel_display *display, in icl_aux_power_well_disable() argument
567 enum phy phy = icl_aux_pw_to_phy(display, power_well); in icl_aux_power_well_disable()
569 if (intel_phy_is_tc(display, phy)) in icl_aux_power_well_disable()
570 return hsw_power_well_disable(display, power_well); in icl_aux_power_well_disable()
571 else if (display->platform.icelake) in icl_aux_power_well_disable()
572 return icl_combo_phy_aux_power_well_disable(display, in icl_aux_power_well_disable()
575 return hsw_power_well_disable(display, power_well); in icl_aux_power_well_disable()
583 static bool hsw_power_well_enabled(struct intel_display *display, in hsw_power_well_enabled() argument
593 val = intel_de_read(display, regs->driver); in hsw_power_well_enabled()
601 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && in hsw_power_well_enabled()
603 val |= intel_de_read(display, regs->bios); in hsw_power_well_enabled()
608 static void assert_can_enable_dc9(struct intel_display *display) in assert_can_enable_dc9() argument
610 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_can_enable_dc9()
612 drm_WARN_ONCE(display->drm, in assert_can_enable_dc9()
613 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), in assert_can_enable_dc9()
615 drm_WARN_ONCE(display->drm, in assert_can_enable_dc9()
616 intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc9()
619 drm_WARN_ONCE(display->drm, in assert_can_enable_dc9()
620 intel_de_read(display, HSW_PWR_WELL_CTL2) & in assert_can_enable_dc9()
623 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
629 * 1] Check relevant display engine registers to verify if mode set in assert_can_enable_dc9()
631 * 2] Check if display uninitialize sequence is initialized. in assert_can_enable_dc9()
635 static void assert_can_disable_dc9(struct intel_display *display) in assert_can_disable_dc9() argument
637 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_can_disable_dc9()
639 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), in assert_can_disable_dc9()
641 drm_WARN_ONCE(display->drm, in assert_can_disable_dc9()
642 intel_de_read(display, DC_STATE_EN) & in assert_can_disable_dc9()
649 * 1] Check relevant display engine registers to verify if mode in assert_can_disable_dc9()
651 * 2] Check if display uninitialize sequence is initialized. in assert_can_disable_dc9()
655 static void gen9_write_dc_state(struct intel_display *display, in gen9_write_dc_state() argument
662 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
670 v = intel_de_read(display, DC_STATE_EN); in gen9_write_dc_state()
673 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
683 drm_err(display->drm, in gen9_write_dc_state()
689 drm_dbg_kms(display->drm, in gen9_write_dc_state()
694 static u32 gen9_dc_mask(struct intel_display *display) in gen9_dc_mask() argument
700 if (DISPLAY_VER(display) >= 12) in gen9_dc_mask()
703 else if (DISPLAY_VER(display) == 11) in gen9_dc_mask()
705 else if (display->platform.geminilake || display->platform.broxton) in gen9_dc_mask()
713 void gen9_sanitize_dc_state(struct intel_display *display) in gen9_sanitize_dc_state() argument
715 struct i915_power_domains *power_domains = &display->power.domains; in gen9_sanitize_dc_state()
718 if (!HAS_DISPLAY(display)) in gen9_sanitize_dc_state()
721 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); in gen9_sanitize_dc_state()
723 drm_dbg_kms(display->drm, in gen9_sanitize_dc_state()
730 * gen9_set_dc_state - set target display C power state
731 * @display: display instance
739 * DMC/HW can turn off individual display clocks and power rails when entering
743 * depending on the active state of display pipes. The state of display
752 void gen9_set_dc_state(struct intel_display *display, u32 state) in gen9_set_dc_state() argument
754 struct i915_power_domains *power_domains = &display->power.domains; in gen9_set_dc_state()
758 if (!HAS_DISPLAY(display)) in gen9_set_dc_state()
761 if (drm_WARN_ON_ONCE(display->drm, in gen9_set_dc_state()
765 val = intel_de_read(display, DC_STATE_EN); in gen9_set_dc_state()
766 mask = gen9_dc_mask(display); in gen9_set_dc_state()
767 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", in gen9_set_dc_state()
772 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", in gen9_set_dc_state()
778 gen9_write_dc_state(display, val); in gen9_set_dc_state()
783 static void tgl_enable_dc3co(struct intel_display *display) in tgl_enable_dc3co() argument
785 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); in tgl_enable_dc3co()
786 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); in tgl_enable_dc3co()
789 static void tgl_disable_dc3co(struct intel_display *display) in tgl_disable_dc3co() argument
791 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); in tgl_disable_dc3co()
792 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); in tgl_disable_dc3co()
793 gen9_set_dc_state(display, DC_STATE_DISABLE); in tgl_disable_dc3co()
800 static void assert_can_enable_dc5(struct intel_display *display) in assert_can_enable_dc5() argument
802 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in assert_can_enable_dc5()
806 if (DISPLAY_VER(display) == 12) in assert_can_enable_dc5()
811 drm_WARN_ONCE(display->drm, in assert_can_enable_dc5()
812 intel_display_power_well_is_enabled(display, high_pg), in assert_can_enable_dc5()
815 drm_WARN_ONCE(display->drm, in assert_can_enable_dc5()
816 (intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc5()
821 assert_dmc_loaded(display); in assert_can_enable_dc5()
824 void gen9_enable_dc5(struct intel_display *display) in gen9_enable_dc5() argument
826 assert_can_enable_dc5(display); in gen9_enable_dc5()
828 drm_dbg_kms(display->drm, "Enabling DC5\n"); in gen9_enable_dc5()
830 /* Wa Display #1183: skl,kbl,cfl */ in gen9_enable_dc5()
831 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in gen9_enable_dc5()
832 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in gen9_enable_dc5()
835 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); in gen9_enable_dc5()
837 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); in gen9_enable_dc5()
840 static void assert_can_enable_dc6(struct intel_display *display) in assert_can_enable_dc6() argument
842 drm_WARN_ONCE(display->drm, in assert_can_enable_dc6()
843 (intel_de_read(display, UTIL_PIN_CTL) & in assert_can_enable_dc6()
847 drm_WARN_ONCE(display->drm, in assert_can_enable_dc6()
848 (intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc6()
852 assert_dmc_loaded(display); in assert_can_enable_dc6()
855 void skl_enable_dc6(struct intel_display *display) in skl_enable_dc6() argument
857 assert_can_enable_dc6(display); in skl_enable_dc6()
859 drm_dbg_kms(display->drm, "Enabling DC6\n"); in skl_enable_dc6()
861 /* Wa Display #1183: skl,kbl,cfl */ in skl_enable_dc6()
862 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in skl_enable_dc6()
863 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in skl_enable_dc6()
866 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); in skl_enable_dc6()
868 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); in skl_enable_dc6()
871 void bxt_enable_dc9(struct intel_display *display) in bxt_enable_dc9() argument
873 assert_can_enable_dc9(display); in bxt_enable_dc9()
875 drm_dbg_kms(display->drm, "Enabling DC9\n"); in bxt_enable_dc9()
878 * aren't always on, unlike with South Display Engine on PCH. in bxt_enable_dc9()
880 if (display->platform.broxton || display->platform.geminilake) in bxt_enable_dc9()
881 bxt_pps_reset_all(display); in bxt_enable_dc9()
882 gen9_set_dc_state(display, DC_STATE_EN_DC9); in bxt_enable_dc9()
885 void bxt_disable_dc9(struct intel_display *display) in bxt_disable_dc9() argument
887 assert_can_disable_dc9(display); in bxt_disable_dc9()
889 drm_dbg_kms(display->drm, "Disabling DC9\n"); in bxt_disable_dc9()
891 gen9_set_dc_state(display, DC_STATE_DISABLE); in bxt_disable_dc9()
893 intel_pps_unlock_regs_wa(display); in bxt_disable_dc9()
896 static void hsw_power_well_sync_hw(struct intel_display *display, in hsw_power_well_sync_hw() argument
902 u32 bios_req = intel_de_read(display, regs->bios); in hsw_power_well_sync_hw()
906 u32 drv_req = intel_de_read(display, regs->driver); in hsw_power_well_sync_hw()
909 intel_de_write(display, regs->driver, drv_req | mask); in hsw_power_well_sync_hw()
910 intel_de_write(display, regs->bios, bios_req & ~mask); in hsw_power_well_sync_hw()
914 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, in bxt_dpio_cmn_power_well_enable() argument
917 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); in bxt_dpio_cmn_power_well_enable()
920 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, in bxt_dpio_cmn_power_well_disable() argument
923 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); in bxt_dpio_cmn_power_well_disable()
926 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, in bxt_dpio_cmn_power_well_enabled() argument
929 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); in bxt_dpio_cmn_power_well_enabled()
932 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) in bxt_verify_dpio_phy_power_wells() argument
936 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); in bxt_verify_dpio_phy_power_wells()
938 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); in bxt_verify_dpio_phy_power_wells()
940 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in bxt_verify_dpio_phy_power_wells()
942 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); in bxt_verify_dpio_phy_power_wells()
944 if (display->platform.geminilake) { in bxt_verify_dpio_phy_power_wells()
945 power_well = lookup_power_well(display, in bxt_verify_dpio_phy_power_wells()
948 bxt_dpio_phy_verify_state(display, in bxt_verify_dpio_phy_power_wells()
953 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, in gen9_dc_off_power_well_enabled() argument
956 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && in gen9_dc_off_power_well_enabled()
957 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); in gen9_dc_off_power_well_enabled()
960 static void gen9_assert_dbuf_enabled(struct intel_display *display) in gen9_assert_dbuf_enabled() argument
962 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); in gen9_assert_dbuf_enabled()
963 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; in gen9_assert_dbuf_enabled()
965 drm_WARN(display->drm, in gen9_assert_dbuf_enabled()
972 void gen9_disable_dc_states(struct intel_display *display) in gen9_disable_dc_states() argument
974 struct i915_power_domains *power_domains = &display->power.domains; in gen9_disable_dc_states()
979 tgl_disable_dc3co(display); in gen9_disable_dc_states()
983 if (HAS_DISPLAY(display)) { in gen9_disable_dc_states()
984 intel_dmc_wl_get_noreg(display); in gen9_disable_dc_states()
985 gen9_set_dc_state(display, DC_STATE_DISABLE); in gen9_disable_dc_states()
986 intel_dmc_wl_put_noreg(display); in gen9_disable_dc_states()
988 gen9_set_dc_state(display, DC_STATE_DISABLE); in gen9_disable_dc_states()
994 intel_dmc_wl_disable(display); in gen9_disable_dc_states()
996 intel_cdclk_get_cdclk(display, &cdclk_config); in gen9_disable_dc_states()
998 drm_WARN_ON(display->drm, in gen9_disable_dc_states()
999 intel_cdclk_clock_changed(&display->cdclk.hw, in gen9_disable_dc_states()
1002 gen9_assert_dbuf_enabled(display); in gen9_disable_dc_states()
1004 if (display->platform.geminilake || display->platform.broxton) in gen9_disable_dc_states()
1005 bxt_verify_dpio_phy_power_wells(display); in gen9_disable_dc_states()
1007 if (DISPLAY_VER(display) >= 11) in gen9_disable_dc_states()
1013 intel_combo_phy_init(display); in gen9_disable_dc_states()
1016 static void gen9_dc_off_power_well_enable(struct intel_display *display, in gen9_dc_off_power_well_enable() argument
1019 gen9_disable_dc_states(display); in gen9_dc_off_power_well_enable()
1022 static void gen9_dc_off_power_well_disable(struct intel_display *display, in gen9_dc_off_power_well_disable() argument
1025 struct i915_power_domains *power_domains = &display->power.domains; in gen9_dc_off_power_well_disable()
1027 if (!intel_dmc_has_payload(display)) in gen9_dc_off_power_well_disable()
1032 tgl_enable_dc3co(display); in gen9_dc_off_power_well_disable()
1035 skl_enable_dc6(display); in gen9_dc_off_power_well_disable()
1038 gen9_enable_dc5(display); in gen9_dc_off_power_well_disable()
1043 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, in i9xx_power_well_sync_hw_noop() argument
1048 static void i9xx_always_on_power_well_noop(struct intel_display *display, in i9xx_always_on_power_well_noop() argument
1053 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, in i9xx_always_on_power_well_enabled() argument
1059 static void i830_pipes_power_well_enable(struct intel_display *display, in i830_pipes_power_well_enable() argument
1062 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1063 i830_enable_pipe(display, PIPE_A); in i830_pipes_power_well_enable()
1064 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1065 i830_enable_pipe(display, PIPE_B); in i830_pipes_power_well_enable()
1068 static void i830_pipes_power_well_disable(struct intel_display *display, in i830_pipes_power_well_disable() argument
1071 i830_disable_pipe(display, PIPE_B); in i830_pipes_power_well_disable()
1072 i830_disable_pipe(display, PIPE_A); in i830_pipes_power_well_disable()
1075 static bool i830_pipes_power_well_enabled(struct intel_display *display, in i830_pipes_power_well_enabled() argument
1078 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1079 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
1082 static void i830_pipes_power_well_sync_hw(struct intel_display *display, in i830_pipes_power_well_sync_hw() argument
1086 i830_pipes_power_well_enable(display, power_well); in i830_pipes_power_well_sync_hw()
1088 i830_pipes_power_well_disable(display, power_well); in i830_pipes_power_well_sync_hw()
1091 static void vlv_set_power_well(struct intel_display *display, in vlv_set_power_well() argument
1094 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_set_power_well()
1118 drm_err(display->drm, in vlv_set_power_well()
1129 static void vlv_power_well_enable(struct intel_display *display, in vlv_power_well_enable() argument
1132 vlv_set_power_well(display, power_well, true); in vlv_power_well_enable()
1135 static void vlv_power_well_disable(struct intel_display *display, in vlv_power_well_disable() argument
1138 vlv_set_power_well(display, power_well, false); in vlv_power_well_disable()
1141 static bool vlv_power_well_enabled(struct intel_display *display, in vlv_power_well_enabled() argument
1144 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_power_well_enabled()
1161 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && in vlv_power_well_enabled()
1171 drm_WARN_ON(display->drm, ctrl != state); in vlv_power_well_enabled()
1178 static void vlv_init_display_clock_gating(struct intel_display *display) in vlv_init_display_clock_gating() argument
1181 * On driver load, a pipe may be active and driving a DSI display. in vlv_init_display_clock_gating()
1184 * clear it when we turn off the display. in vlv_init_display_clock_gating()
1186 intel_de_rmw(display, DSPCLK_GATE_D(display), in vlv_init_display_clock_gating()
1192 intel_de_write(display, MI_ARB_VLV, in vlv_init_display_clock_gating()
1194 intel_de_write(display, CBR1_VLV, 0); in vlv_init_display_clock_gating()
1196 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); in vlv_init_display_clock_gating()
1197 intel_de_write(display, RAWCLK_FREQ_VLV, in vlv_init_display_clock_gating()
1198 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, in vlv_init_display_clock_gating()
1202 static void vlv_display_power_well_init(struct intel_display *display) in vlv_display_power_well_init() argument
1204 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_display_power_well_init()
1210 * display and the reference clock for VGA in vlv_display_power_well_init()
1216 for_each_pipe(display, pipe) { in vlv_display_power_well_init()
1217 u32 val = intel_de_read(display, DPLL(display, pipe)); in vlv_display_power_well_init()
1223 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_init()
1226 vlv_init_display_clock_gating(display); in vlv_display_power_well_init()
1236 if (display->power.domains.initializing) in vlv_display_power_well_init()
1243 for_each_intel_encoder(display->drm, encoder) { in vlv_display_power_well_init()
1248 intel_vga_redisable_power_on(display); in vlv_display_power_well_init()
1250 intel_pps_unlock_regs_wa(display); in vlv_display_power_well_init()
1253 static void vlv_display_power_well_deinit(struct intel_display *display) in vlv_display_power_well_deinit() argument
1255 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_display_power_well_deinit()
1261 /* make sure we're done processing display irqs */ in vlv_display_power_well_deinit()
1264 vlv_pps_reset_all(display); in vlv_display_power_well_deinit()
1267 if (!display->drm->dev->power.is_suspended) in vlv_display_power_well_deinit()
1271 static void vlv_display_power_well_enable(struct intel_display *display, in vlv_display_power_well_enable() argument
1274 vlv_set_power_well(display, power_well, true); in vlv_display_power_well_enable()
1276 vlv_display_power_well_init(display); in vlv_display_power_well_enable()
1279 static void vlv_display_power_well_disable(struct intel_display *display, in vlv_display_power_well_disable() argument
1282 vlv_display_power_well_deinit(display); in vlv_display_power_well_disable()
1284 vlv_set_power_well(display, power_well, false); in vlv_display_power_well_disable()
1287 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, in vlv_dpio_cmn_power_well_enable() argument
1293 vlv_set_power_well(display, power_well, true); in vlv_dpio_cmn_power_well_enable()
1306 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); in vlv_dpio_cmn_power_well_enable()
1309 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, in vlv_dpio_cmn_power_well_disable() argument
1314 for_each_pipe(display, pipe) in vlv_dpio_cmn_power_well_disable()
1315 assert_pll_disabled(display, pipe); in vlv_dpio_cmn_power_well_disable()
1318 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); in vlv_dpio_cmn_power_well_disable()
1320 vlv_set_power_well(display, power_well, false); in vlv_dpio_cmn_power_well_disable()
1325 static void assert_chv_phy_status(struct intel_display *display) in assert_chv_phy_status() argument
1328 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in assert_chv_phy_status()
1330 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); in assert_chv_phy_status()
1331 u32 phy_control = display->power.chv_phy_control; in assert_chv_phy_status()
1342 if (!display->power.chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1350 if (!display->power.chv_phy_assert[DPIO_PHY1]) in assert_chv_phy_status()
1355 if (intel_power_well_is_enabled(display, cmn_bc)) { in assert_chv_phy_status()
1378 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1396 if (intel_power_well_is_enabled(display, cmn_d)) { in assert_chv_phy_status()
1421 if (intel_de_wait(display, DISPLAY_PHY_STATUS, in assert_chv_phy_status()
1423 drm_err(display->drm, in assert_chv_phy_status()
1425 intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask, in assert_chv_phy_status()
1426 phy_status, display->power.chv_phy_control); in assert_chv_phy_status()
1431 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, in chv_dpio_cmn_power_well_enable() argument
1434 struct drm_i915_private *dev_priv = to_i915(display->drm); in chv_dpio_cmn_power_well_enable()
1439 drm_WARN_ON_ONCE(display->drm, in chv_dpio_cmn_power_well_enable()
1450 vlv_set_power_well(display, power_well, true); in chv_dpio_cmn_power_well_enable()
1453 if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, in chv_dpio_cmn_power_well_enable()
1455 drm_err(display->drm, "Display PHY %d is not power up\n", in chv_dpio_cmn_power_well_enable()
1483 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); in chv_dpio_cmn_power_well_enable()
1484 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_enable()
1485 display->power.chv_phy_control); in chv_dpio_cmn_power_well_enable()
1487 drm_dbg_kms(display->drm, in chv_dpio_cmn_power_well_enable()
1489 phy, display->power.chv_phy_control); in chv_dpio_cmn_power_well_enable()
1491 assert_chv_phy_status(display); in chv_dpio_cmn_power_well_enable()
1494 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, in chv_dpio_cmn_power_well_disable() argument
1500 drm_WARN_ON_ONCE(display->drm, in chv_dpio_cmn_power_well_disable()
1506 assert_pll_disabled(display, PIPE_A); in chv_dpio_cmn_power_well_disable()
1507 assert_pll_disabled(display, PIPE_B); in chv_dpio_cmn_power_well_disable()
1510 assert_pll_disabled(display, PIPE_C); in chv_dpio_cmn_power_well_disable()
1513 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); in chv_dpio_cmn_power_well_disable()
1514 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_disable()
1515 display->power.chv_phy_control); in chv_dpio_cmn_power_well_disable()
1517 vlv_set_power_well(display, power_well, false); in chv_dpio_cmn_power_well_disable()
1519 drm_dbg_kms(display->drm, in chv_dpio_cmn_power_well_disable()
1521 phy, display->power.chv_phy_control); in chv_dpio_cmn_power_well_disable()
1524 display->power.chv_phy_assert[phy] = true; in chv_dpio_cmn_power_well_disable()
1526 assert_chv_phy_status(display); in chv_dpio_cmn_power_well_disable()
1529 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, in assert_chv_phy_powergate() argument
1532 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_chv_phy_powergate()
1542 if (!display->power.chv_phy_assert[phy]) in assert_chv_phy_powergate()
1585 drm_WARN(display->drm, actual != expected, in assert_chv_phy_powergate()
1594 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, in chv_phy_powergate_ch() argument
1597 struct i915_power_domains *power_domains = &display->power.domains; in chv_phy_powergate_ch()
1602 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1608 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1610 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1612 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_phy_powergate_ch()
1613 display->power.chv_phy_control); in chv_phy_powergate_ch()
1615 drm_dbg_kms(display->drm, in chv_phy_powergate_ch()
1617 phy, ch, display->power.chv_phy_control); in chv_phy_powergate_ch()
1619 assert_chv_phy_status(display); in chv_phy_powergate_ch()
1630 struct intel_display *display = to_intel_display(encoder); in chv_phy_powergate_lanes() local
1631 struct i915_power_domains *power_domains = &display->power.domains; in chv_phy_powergate_lanes()
1637 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); in chv_phy_powergate_lanes()
1638 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); in chv_phy_powergate_lanes()
1641 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_lanes()
1643 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_lanes()
1645 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_phy_powergate_lanes()
1646 display->power.chv_phy_control); in chv_phy_powergate_lanes()
1648 drm_dbg_kms(display->drm, in chv_phy_powergate_lanes()
1650 phy, ch, mask, display->power.chv_phy_control); in chv_phy_powergate_lanes()
1652 assert_chv_phy_status(display); in chv_phy_powergate_lanes()
1654 assert_chv_phy_powergate(display, phy, ch, override, mask); in chv_phy_powergate_lanes()
1659 static bool chv_pipe_power_well_enabled(struct intel_display *display, in chv_pipe_power_well_enabled() argument
1662 struct drm_i915_private *dev_priv = to_i915(display->drm); in chv_pipe_power_well_enabled()
1674 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && in chv_pipe_power_well_enabled()
1683 drm_WARN_ON(display->drm, ctrl << 16 != state); in chv_pipe_power_well_enabled()
1690 static void chv_set_pipe_power_well(struct intel_display *display, in chv_set_pipe_power_well() argument
1694 struct drm_i915_private *dev_priv = to_i915(display->drm); in chv_set_pipe_power_well()
1715 drm_err(display->drm, in chv_set_pipe_power_well()
1726 static void chv_pipe_power_well_sync_hw(struct intel_display *display, in chv_pipe_power_well_sync_hw() argument
1729 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_pipe_power_well_sync_hw()
1730 display->power.chv_phy_control); in chv_pipe_power_well_sync_hw()
1733 static void chv_pipe_power_well_enable(struct intel_display *display, in chv_pipe_power_well_enable() argument
1736 chv_set_pipe_power_well(display, power_well, true); in chv_pipe_power_well_enable()
1738 vlv_display_power_well_init(display); in chv_pipe_power_well_enable()
1741 static void chv_pipe_power_well_disable(struct intel_display *display, in chv_pipe_power_well_disable() argument
1744 vlv_display_power_well_deinit(display); in chv_pipe_power_well_disable()
1746 chv_set_pipe_power_well(display, power_well, false); in chv_pipe_power_well_disable()
1750 tgl_tc_cold_request(struct intel_display *display, bool block) in tgl_tc_cold_request() argument
1752 struct drm_i915_private *i915 = to_i915(display->drm); in tgl_tc_cold_request()
1793 tgl_tc_cold_off_power_well_enable(struct intel_display *display, in tgl_tc_cold_off_power_well_enable() argument
1796 tgl_tc_cold_request(display, true); in tgl_tc_cold_off_power_well_enable()
1800 tgl_tc_cold_off_power_well_disable(struct intel_display *display, in tgl_tc_cold_off_power_well_disable() argument
1803 tgl_tc_cold_request(display, false); in tgl_tc_cold_off_power_well_disable()
1807 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, in tgl_tc_cold_off_power_well_sync_hw() argument
1811 tgl_tc_cold_off_power_well_enable(display, power_well); in tgl_tc_cold_off_power_well_sync_hw()
1813 tgl_tc_cold_off_power_well_disable(display, power_well); in tgl_tc_cold_off_power_well_sync_hw()
1817 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, in tgl_tc_cold_off_power_well_is_enabled() argument
1827 static void xelpdp_aux_power_well_enable(struct intel_display *display, in xelpdp_aux_power_well_enable() argument
1831 enum phy phy = icl_aux_pw_to_phy(display, power_well); in xelpdp_aux_power_well_enable()
1833 if (intel_phy_is_tc(display, phy)) in xelpdp_aux_power_well_enable()
1834 icl_tc_port_assert_ref_held(display, power_well, in xelpdp_aux_power_well_enable()
1835 aux_ch_to_digital_port(display, aux_ch)); in xelpdp_aux_power_well_enable()
1837 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), in xelpdp_aux_power_well_enable()
1850 static void xelpdp_aux_power_well_disable(struct intel_display *display, in xelpdp_aux_power_well_disable() argument
1855 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), in xelpdp_aux_power_well_disable()
1861 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, in xelpdp_aux_power_well_enabled() argument
1866 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & in xelpdp_aux_power_well_enabled()
1870 static void xe2lpd_pica_power_well_enable(struct intel_display *display, in xe2lpd_pica_power_well_enable() argument
1873 intel_de_write(display, XE2LPD_PICA_PW_CTL, in xe2lpd_pica_power_well_enable()
1876 if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL, in xe2lpd_pica_power_well_enable()
1878 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); in xe2lpd_pica_power_well_enable()
1880 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); in xe2lpd_pica_power_well_enable()
1884 static void xe2lpd_pica_power_well_disable(struct intel_display *display, in xe2lpd_pica_power_well_disable() argument
1887 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); in xe2lpd_pica_power_well_disable()
1889 if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL, in xe2lpd_pica_power_well_disable()
1891 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); in xe2lpd_pica_power_well_disable()
1893 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); in xe2lpd_pica_power_well_disable()
1897 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, in xe2lpd_pica_power_well_enabled() argument
1900 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & in xe2lpd_pica_power_well_enabled()