| /linux-6.15/drivers/gpu/drm/i915/display/ |
| D | intel_fifo_underrun.c | 41 * The i915 driver checks for display fifo underruns using the interrupt signals
43 * debug display issues, especially watermark settings.
47 * occurrence until the next modeset on a given pipe.
50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
58 static bool ivb_can_enable_err_int(struct intel_display *display) in ivb_can_enable_err_int() argument
60 struct drm_i915_private *dev_priv = to_i915(display->drm); in ivb_can_enable_err_int()
62 enum pipe pipe; in ivb_can_enable_err_int() local
64 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
66 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
67 crtc = intel_crtc_for_pipe(display, pipe); in ivb_can_enable_err_int()
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| D | intel_display_irq.c | 1 // SPDX-License-Identifier: MIT
33 intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, in intel_display_irq_regs_init() argument
36 intel_dmc_wl_get(display, regs.imr); in intel_display_irq_regs_init()
37 intel_dmc_wl_get(display, regs.ier); in intel_display_irq_regs_init()
38 intel_dmc_wl_get(display, regs.iir); in intel_display_irq_regs_init()
40 gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); in intel_display_irq_regs_init()
42 intel_dmc_wl_put(display, regs.iir); in intel_display_irq_regs_init()
43 intel_dmc_wl_put(display, regs.ier); in intel_display_irq_regs_init()
44 intel_dmc_wl_put(display, regs.imr); in intel_display_irq_regs_init()
48 intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) in intel_display_irq_regs_reset() argument
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| D | intel_fdi.c | 1 // SPDX-License-Identifier: MIT
27 static void assert_fdi_tx(struct intel_display *display, in assert_fdi_tx() argument
28 enum pipe pipe, bool state) in assert_fdi_tx() argument
32 if (HAS_DDI(display)) { in assert_fdi_tx()
37 * so pipe->transcoder cast is fine here. in assert_fdi_tx()
39 enum transcoder cpu_transcoder = (enum transcoder)pipe; in assert_fdi_tx()
40 cur_state = intel_de_read(display, in assert_fdi_tx()
41 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
43 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
45 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_fdi_tx()
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| D | intel_pch_display.c | 1 // SPDX-License-Identifier: MIT
24 enum pipe pch_transcoder) in intel_has_pch_trancoder()
30 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) in intel_crtc_pch_transcoder()
32 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_pch_transcoder()
37 return crtc->pipe; in intel_crtc_pch_transcoder()
41 enum pipe pipe, enum port port, in assert_pch_dp_disabled() argument
44 struct intel_display *display = &dev_priv->display; in assert_pch_dp_disabled() local
45 enum pipe port_pipe; in assert_pch_dp_disabled()
48 state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); in assert_pch_dp_disabled()
50 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, in assert_pch_dp_disabled()
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| D | intel_sprite.c | 51 static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite) in sprite_name() argument
53 return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A'; in sprite_name()
69 struct intel_display *display = to_intel_display(plane_state); in chv_sprite_update_csc() local
70 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in chv_sprite_update_csc()
71 const struct drm_framebuffer *fb = plane_state->hw.fb; in chv_sprite_update_csc()
72 enum plane_id plane_id = plane->id; in chv_sprite_update_csc()
84 /* BT.601 full range YCbCr -> full range RGB */ in chv_sprite_update_csc()
87 -2925, 4096, -1410, in chv_sprite_update_csc()
90 /* BT.709 full range YCbCr -> full range RGB */ in chv_sprite_update_csc()
93 -1917, 4096, -767, in chv_sprite_update_csc()
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| D | intel_color.c | 38 * Program non-arming double buffered color management registers
100 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
103 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
116 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
117 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
118 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
119 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
132 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
135 #define ILK_CSC_COEFF_LIMITED_RANGE ((235 - 16) << (12 - 8)) /* exponent 0 */
136 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 << (12 - 8))
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| D | skl_universal_plane.c | 1 // SPDX-License-Identifier: MIT
236 static u8 icl_nv12_y_plane_mask(struct intel_display *display) in icl_nv12_y_plane_mask() argument
238 if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) in icl_nv12_y_plane_mask()
244 bool icl_is_nv12_y_plane(struct intel_display *display, in icl_is_nv12_y_plane() argument
247 return DISPLAY_VER(display) >= 11 && in icl_is_nv12_y_plane()
248 icl_nv12_y_plane_mask(display) & BIT(plane_id); in icl_is_nv12_y_plane()
256 bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id) in icl_is_hdr_plane() argument
258 return DISPLAY_VER(display) >= 11 && in icl_is_hdr_plane()
275 const struct drm_framebuffer *fb = plane_state->hw.fb; in glk_plane_ratio()
277 if (fb->format->cpp[0] == 8) { in glk_plane_ratio()
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| D | intel_display.c | 2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
175 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
185 void intel_update_czclk(struct intel_display *display) in intel_update_czclk() argument
187 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_update_czclk()
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| D | intel_link_bw.c | 1 // SPDX-License-Identifier: MIT
19 * intel_link_bw_init_limits - initialize BW limits
28 struct intel_display *display = to_intel_display(state); in intel_link_bw_init_limits() local
29 enum pipe pipe; in intel_link_bw_init_limits() local
31 limits->force_fec_pipes = 0; in intel_link_bw_init_limits()
32 limits->bpp_limit_reached_pipes = 0; in intel_link_bw_init_limits()
33 for_each_pipe(display, pipe) { in intel_link_bw_init_limits()
36 intel_crtc_for_pipe(display, pipe)); in intel_link_bw_init_limits()
38 if (state->base.duplicated && crtc_state) { in intel_link_bw_init_limits()
39 limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16; in intel_link_bw_init_limits()
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| D | intel_cursor.c | 1 // SPDX-License-Identifier: MIT
38 struct intel_display *display = to_intel_display(plane_state); in intel_cursor_base() local
41 if (DISPLAY_INFO(display)->cursor_needs_physical) in intel_cursor_base()
42 base = plane_state->phys_dma_addr; in intel_cursor_base()
46 return base + plane_state->view.color_plane[0].offset; in intel_cursor_base()
53 int x = plane_state->uapi.dst.x1; in intel_cursor_position()
54 int y = plane_state->uapi.dst.y1; in intel_cursor_position()
59 * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode in intel_cursor_position()
60 * select setting> + 1, CUR_POS Y Position - Update region Y position in intel_cursor_position()
63 y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1, in intel_cursor_position()
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| D | intel_pps.c | 1 // SPDX-License-Identifier: MIT
23 static void vlv_steal_power_sequencer(struct intel_display *display,
24 enum pipe pipe);
31 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
32 struct intel_pps *pps = &intel_dp->pps; in pps_name()
34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
35 switch (pps->vlv_pps_pipe) { in pps_name()
47 MISSING_CASE(pps->vlv_pps_pipe); in pps_name()
51 switch (pps->pps_idx) { in pps_name()
57 MISSING_CASE(pps->pps_idx); in pps_name()
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| D | intel_fdi.h | 1 /* SPDX-License-Identifier: MIT */
11 enum pipe;
21 int intel_fdi_link_freq(struct intel_display *display,
32 void intel_fdi_init_hook(struct intel_display *display);
36 void intel_fdi_pll_freq_update(struct intel_display *display);
41 void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe);
42 void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe);
43 void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe);
44 void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe);
45 void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);
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| D | i9xx_plane.c | 1 // SPDX-License-Identifier: MIT
112 static bool i9xx_plane_has_fbc(struct intel_display *display, in i9xx_plane_has_fbc() argument
115 if (!HAS_FBC(display)) in i9xx_plane_has_fbc()
118 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
119 return i9xx_plane == PLANE_A; /* tied to pipe A */ in i9xx_plane_has_fbc()
120 else if (display->platform.ivybridge) in i9xx_plane_has_fbc()
123 else if (DISPLAY_VER(display) >= 4) in i9xx_plane_has_fbc()
129 static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, in i9xx_plane_fbc() argument
132 if (i9xx_plane_has_fbc(display, i9xx_plane)) in i9xx_plane_fbc()
133 return display->fbc[INTEL_FBC_A]; in i9xx_plane_fbc()
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| D | intel_pfit.c | 1 // SPDX-License-Identifier: MIT
20 struct intel_display *display = to_intel_display(crtc_state); in intel_pch_pfit_check_dst_window() local
21 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_pch_pfit_check_dst_window()
23 &crtc_state->hw.adjusted_mode; in intel_pch_pfit_check_dst_window()
24 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; in intel_pch_pfit_check_dst_window()
27 int x = dst->x1; in intel_pch_pfit_check_dst_window()
28 int y = dst->y1; in intel_pch_pfit_check_dst_window()
30 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE && in intel_pch_pfit_check_dst_window()
32 drm_dbg_kms(display->drm, in intel_pch_pfit_check_dst_window()
34 crtc->base.base.id, crtc->base.name, DRM_RECT_ARG(dst)); in intel_pch_pfit_check_dst_window()
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| D | intel_dsb.c | 1 // SPDX-License-Identifier: MIT
62 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
63 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
65 * It allows driver to batch submit display HW programming. This helps to
69 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
109 return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc); in pre_commit_is_vrr_active()
127 return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode); in dsb_vblank_delay()
139 return intel_mode_vtotal(&crtc_state->hw.adjusted_mode); in dsb_vtotal()
147 struct drm_i915_private *i915 = to_i915(state->base.dev); in dsb_dewake_scanline_start()
150 return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) - in dsb_dewake_scanline_start()
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| D | intel_display_reg_defs.h | 1 /* SPDX-License-Identifier: MIT */
11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset)
18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
32 #define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c… argument
33 #define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c… argument
39 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \ argument
40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
41 DISPLAY_MMIO_BASE(display) + (reg))
42 #define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ argument
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| D | intel_vblank.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022-2023 Intel Corporation
34 * | may be shifted forward 1-3 extra lines via TRANSCONF
41 * ----va---> <-----------------vb--------------------> <--------va-------------
42 * | | <----vs-----> |
43 …* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter …
44 …* -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter …
45 …* -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter …
60 * - most events happen at the start of horizontal sync
61 * - frame start happens at the start of horizontal blank, 1-4 lines
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| D | intel_vdsc.c | 1 // SPDX-License-Identifier: MIT
10 #include <drm/display/drm_dsc_helper.h>
25 struct intel_display *display = to_intel_display(crtc_state); in intel_dsc_source_support() local
26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
28 if (!HAS_DSC(display)) in intel_dsc_source_support()
31 if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A) in intel_dsc_source_support()
39 struct intel_display *display = to_intel_display(crtc); in is_pipe_dsc() local
41 if (DISPLAY_VER(display) >= 12) in is_pipe_dsc()
49 /* There's no pipe A DSC engine on ICL */ in is_pipe_dsc()
50 drm_WARN_ON(display->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
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| D | intel_backlight.c | 1 // SPDX-License-Identifier: MIT
28 * scale - scale values from one range to another
52 target_val = mul_u32_u32(source_val - source_min, in scale()
53 target_max - target_min); in scale()
54 target_val = DIV_ROUND_CLOSEST_ULL(target_val, source_max - source_min); in scale()
67 struct intel_panel *panel = &connector->panel; in clamp_user_to_hw()
70 hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max); in clamp_user_to_hw()
71 hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max); in clamp_user_to_hw()
80 struct intel_panel *panel = &connector->panel; in scale_hw_to_user()
82 return scale(hw_level, panel->backlight.min, panel->backlight.max, in scale_hw_to_user()
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| D | intel_display_trace.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
27 #define __dev_name_display(display) dev_name((display)->drm->dev) argument
28 #define __dev_name_drm(obj) dev_name((obj)->dev->dev)
29 #define __dev_name_kms(obj) dev_name((obj)->base.dev->dev)
32 * Using identifiers from enum pipe in TP_printk() will confuse tools that
42 * FIXME: Several TP_printk() calls below display frame and scanline numbers for
49 static_assert(I915_MAX_PIPES - 1 == _TRACE_PIPE_D);
52 "pipe A: frame=%u, scanline=%u" \
53 ", pipe B: frame=%u, scanline=%u" \
54 ", pipe C: frame=%u, scanline=%u" \
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| D | intel_crtc.c | 1 // SPDX-License-Identifier: MIT
40 struct intel_display *display = to_intel_display(crtc->dev); in assert_vblank_disabled() local
42 if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0, in assert_vblank_disabled()
44 crtc->base.id, crtc->name)) in assert_vblank_disabled()
48 struct intel_crtc *intel_first_crtc(struct intel_display *display) in intel_first_crtc() argument
50 return to_intel_crtc(drm_crtc_from_index(display->drm, 0)); in intel_first_crtc()
53 struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display, in intel_crtc_for_pipe() argument
54 enum pipe pipe) in intel_crtc_for_pipe() argument
58 for_each_intel_crtc(display->drm, crtc) { in intel_crtc_for_pipe()
59 if (crtc->pipe == pipe) in intel_crtc_for_pipe()
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| D | skl_scaler.c | 1 // SPDX-License-Identifier: MIT
18 * -0.5. That matches how the hardware calculates the scaling
19 * factors (from top-left of the first pixel to bottom-right
30 * The same behaviour is observed on pre-SKL platforms as well.
32 * Theory behind the formula (note that we ignore sub-pixel
38 * -0.5
47 * -0.5
48 * | -0.375 (initial phase)
57 int phase = -0x8000; in skl_scaler_calc_phase()
61 phase += (sub - 1) * 0x8000 / sub; in skl_scaler_calc_phase()
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| D | intel_cdclk.c | 2 * Copyright © 2006-2017 Intel Corporation
55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
77 * - We have the CDCLK PLL, which generates an output clock based on a
79 * - The CD2X Divider, which divides the output of the PLL based on a
80 * divisor selected from a set of pre-defined choices.
81 * - The CD2X Squasher, which further divides the output based on a
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| /linux-6.15/drivers/gpu/drm/i915/gvt/ |
| D | display.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
35 #include <drm/display/drm_dp.h>
41 #include "display/bxt_dpio_phy_regs.h"
42 #include "display/i9xx_plane_regs.h"
43 #include "display/intel_crt_regs.h"
44 #include "display/intel_cursor_regs.h"
45 #include "display/intel_display.h"
46 #include "display/intel_dpio_phy.h"
47 #include "display/intel_sprite_regs.h"
52 int pipe = -1; in get_edp_pipe() local
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| /linux-6.15/Documentation/devicetree/bindings/display/ |
| D | apple,h7-display-pipe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/apple,h7-display-pipe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple pre-DCP display controller
10 - Sasha Finkelstein <fnkl.kernel@gmail.com>
13 A secondary display controller used to drive the "touchbar" on
19 - enum:
20 - apple,t8112-display-pipe
21 - apple,t8103-display-pipe
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