Lines Matching +full:display +full:- +full:pipe
1 // SPDX-License-Identifier: MIT
38 struct intel_display *display = to_intel_display(plane_state); in intel_cursor_base() local
41 if (DISPLAY_INFO(display)->cursor_needs_physical) in intel_cursor_base()
42 base = plane_state->phys_dma_addr; in intel_cursor_base()
46 return base + plane_state->view.color_plane[0].offset; in intel_cursor_base()
53 int x = plane_state->uapi.dst.x1; in intel_cursor_position()
54 int y = plane_state->uapi.dst.y1; in intel_cursor_position()
59 * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode in intel_cursor_position()
60 * select setting> + 1, CUR_POS Y Position - Update region Y position in intel_cursor_position()
63 y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1, in intel_cursor_position()
64 y - crtc_state->psr2_su_area.y1); in intel_cursor_position()
68 x = -x; in intel_cursor_position()
74 y = -y; in intel_cursor_position()
84 &plane_state->uapi.plane->dev->mode_config; in intel_cursor_size_ok()
85 int width = drm_rect_width(&plane_state->uapi.dst); in intel_cursor_size_ok()
86 int height = drm_rect_height(&plane_state->uapi.dst); in intel_cursor_size_ok()
88 return width > 0 && width <= config->cursor_width && in intel_cursor_size_ok()
89 height > 0 && height <= config->cursor_height; in intel_cursor_size_ok()
94 struct intel_display *display = to_intel_display(plane_state); in intel_cursor_check_surface() local
95 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_cursor_check_surface()
96 unsigned int rotation = plane_state->hw.rotation; in intel_cursor_check_surface()
105 if (!plane_state->uapi.visible) in intel_cursor_check_surface()
108 src_x = plane_state->uapi.src.x1 >> 16; in intel_cursor_check_surface()
109 src_y = plane_state->uapi.src.y1 >> 16; in intel_cursor_check_surface()
116 drm_dbg_kms(display->drm, in intel_cursor_check_surface()
118 plane->base.base.id, plane->base.name); in intel_cursor_check_surface()
119 return -EINVAL; in intel_cursor_check_surface()
126 drm_rect_translate_to(&plane_state->uapi.src, in intel_cursor_check_surface()
130 if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) { in intel_cursor_check_surface()
131 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_cursor_check_surface()
132 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in intel_cursor_check_surface()
133 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in intel_cursor_check_surface()
135 offset += (src_h * src_w - 1) * fb->format->cpp[0]; in intel_cursor_check_surface()
138 plane_state->view.color_plane[0].offset = offset; in intel_cursor_check_surface()
139 plane_state->view.color_plane[0].x = src_x; in intel_cursor_check_surface()
140 plane_state->view.color_plane[0].y = src_y; in intel_cursor_check_surface()
148 struct intel_display *display = to_intel_display(plane_state); in intel_check_cursor() local
149 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_check_cursor()
150 const struct drm_framebuffer *fb = plane_state->hw.fb; in intel_check_cursor()
151 const struct drm_rect src = plane_state->uapi.src; in intel_check_cursor()
152 const struct drm_rect dst = plane_state->uapi.dst; in intel_check_cursor()
155 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { in intel_check_cursor()
156 drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n", in intel_check_cursor()
157 plane->base.base.id, plane->base.name); in intel_check_cursor()
158 return -EINVAL; in intel_check_cursor()
169 plane_state->uapi.src = src; in intel_check_cursor()
170 plane_state->uapi.dst = dst; in intel_check_cursor()
172 /* final plane coordinates will be relative to the plane's pipe */ in intel_check_cursor()
173 drm_rect_translate(&plane_state->uapi.dst, in intel_check_cursor()
174 -crtc_state->pipe_src.x1, in intel_check_cursor()
175 -crtc_state->pipe_src.y1); in intel_check_cursor()
181 if (!plane_state->uapi.visible) in intel_check_cursor()
210 if (crtc_state->gamma_enable) in i845_cursor_ctl_crtc()
221 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride); in i845_cursor_ctl()
226 int width = drm_rect_width(&plane_state->uapi.dst); in i845_cursor_size_ok()
238 struct intel_display *display = to_intel_display(plane_state); in i845_check_cursor() local
239 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in i845_check_cursor()
240 const struct drm_framebuffer *fb = plane_state->hw.fb; in i845_check_cursor()
253 drm_dbg_kms(display->drm, in i845_check_cursor()
255 plane->base.base.id, plane->base.name, in i845_check_cursor()
256 drm_rect_width(&plane_state->uapi.dst), in i845_check_cursor()
257 drm_rect_height(&plane_state->uapi.dst)); in i845_check_cursor()
258 return -EINVAL; in i845_check_cursor()
261 drm_WARN_ON(display->drm, plane_state->uapi.visible && in i845_check_cursor()
262 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); in i845_check_cursor()
264 switch (fb->pitches[0]) { in i845_check_cursor()
271 drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n", in i845_check_cursor()
272 plane->base.base.id, plane->base.name, in i845_check_cursor()
273 fb->pitches[0]); in i845_check_cursor()
274 return -EINVAL; in i845_check_cursor()
277 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); in i845_check_cursor()
288 struct intel_display *display = to_intel_display(plane); in i845_cursor_update_arm() local
291 if (plane_state && plane_state->uapi.visible) { in i845_cursor_update_arm()
292 unsigned int width = drm_rect_width(&plane_state->uapi.dst); in i845_cursor_update_arm()
293 unsigned int height = drm_rect_height(&plane_state->uapi.dst); in i845_cursor_update_arm()
295 cntl = plane_state->ctl | in i845_cursor_update_arm()
307 if (plane->cursor.base != base || in i845_cursor_update_arm()
308 plane->cursor.size != size || in i845_cursor_update_arm()
309 plane->cursor.cntl != cntl) { in i845_cursor_update_arm()
310 intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); in i845_cursor_update_arm()
311 intel_de_write_fw(display, CURBASE(display, PIPE_A), base); in i845_cursor_update_arm()
312 intel_de_write_fw(display, CURSIZE(display, PIPE_A), size); in i845_cursor_update_arm()
313 intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); in i845_cursor_update_arm()
314 intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); in i845_cursor_update_arm()
316 plane->cursor.base = base; in i845_cursor_update_arm()
317 plane->cursor.size = size; in i845_cursor_update_arm()
318 plane->cursor.cntl = cntl; in i845_cursor_update_arm()
320 intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); in i845_cursor_update_arm()
332 enum pipe *pipe) in i845_cursor_get_hw_state() argument
334 struct intel_display *display = to_intel_display(plane); in i845_cursor_get_hw_state() local
340 wakeref = intel_display_power_get_if_enabled(display, power_domain); in i845_cursor_get_hw_state()
344 ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
346 *pipe = PIPE_A; in i845_cursor_get_hw_state()
348 intel_display_power_put(display, power_domain, wakeref); in i845_cursor_get_hw_state()
358 return plane->base.dev->mode_config.cursor_width * 4; in i9xx_cursor_max_stride()
365 /* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned." */ in i830_cursor_min_alignment()
380 struct intel_display *display = to_intel_display(plane); in i9xx_cursor_min_alignment() local
382 if (intel_scanout_needs_vtd_wa(display)) in i9xx_cursor_min_alignment()
390 struct intel_display *display = to_intel_display(crtc_state); in i9xx_cursor_ctl_crtc() local
391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_cursor_ctl_crtc()
394 if (DISPLAY_VER(display) >= 11) in i9xx_cursor_ctl_crtc()
397 if (crtc_state->gamma_enable) in i9xx_cursor_ctl_crtc()
400 if (crtc_state->csc_enable) in i9xx_cursor_ctl_crtc()
403 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) in i9xx_cursor_ctl_crtc()
404 cntl |= MCURSOR_PIPE_SEL(crtc->pipe); in i9xx_cursor_ctl_crtc()
412 struct intel_display *display = to_intel_display(plane_state); in i9xx_cursor_ctl() local
415 if (display->platform.sandybridge || display->platform.ivybridge) in i9xx_cursor_ctl()
418 switch (drm_rect_width(&plane_state->uapi.dst)) { in i9xx_cursor_ctl()
429 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); in i9xx_cursor_ctl()
433 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) in i9xx_cursor_ctl()
436 /* Wa_22012358565:adl-p */ in i9xx_cursor_ctl()
437 if (DISPLAY_VER(display) == 13) in i9xx_cursor_ctl()
445 struct intel_display *display = to_intel_display(plane_state); in i9xx_cursor_size_ok() local
446 int width = drm_rect_width(&plane_state->uapi.dst); in i9xx_cursor_size_ok()
447 int height = drm_rect_height(&plane_state->uapi.dst); in i9xx_cursor_size_ok()
452 /* Cursor width is limited to a few power-of-two sizes */ in i9xx_cursor_size_ok()
468 if (HAS_CUR_FBC(display) && in i9xx_cursor_size_ok()
469 plane_state->hw.rotation & DRM_MODE_ROTATE_0) { in i9xx_cursor_size_ok()
483 struct intel_display *display = to_intel_display(plane_state); in i9xx_check_cursor() local
484 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in i9xx_check_cursor()
485 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_check_cursor()
486 enum pipe pipe = plane->pipe; in i9xx_check_cursor() local
499 drm_dbg_kms(display->drm, in i9xx_check_cursor()
501 plane->base.base.id, plane->base.name, in i9xx_check_cursor()
502 drm_rect_width(&plane_state->uapi.dst), in i9xx_check_cursor()
503 drm_rect_height(&plane_state->uapi.dst)); in i9xx_check_cursor()
504 return -EINVAL; in i9xx_check_cursor()
507 drm_WARN_ON(display->drm, plane_state->uapi.visible && in i9xx_check_cursor()
508 plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); in i9xx_check_cursor()
510 if (fb->pitches[0] != in i9xx_check_cursor()
511 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { in i9xx_check_cursor()
512 drm_dbg_kms(display->drm, in i9xx_check_cursor()
514 plane->base.base.id, plane->base.name, in i9xx_check_cursor()
515 fb->pitches[0], drm_rect_width(&plane_state->uapi.dst)); in i9xx_check_cursor()
516 return -EINVAL; in i9xx_check_cursor()
520 * There's something wrong with the cursor on CHV pipe C. in i9xx_check_cursor()
523 * results in a pipe underrun, and often that can lead to in i9xx_check_cursor()
524 * dead pipe (constant underrun reported, and it scans in i9xx_check_cursor()
526 * display power well must be turned off and on again. in i9xx_check_cursor()
529 if (display->platform.cherryview && pipe == PIPE_C && in i9xx_check_cursor()
530 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { in i9xx_check_cursor()
531 drm_dbg_kms(display->drm, in i9xx_check_cursor()
533 plane->base.base.id, plane->base.name); in i9xx_check_cursor()
534 return -EINVAL; in i9xx_check_cursor()
537 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); in i9xx_check_cursor()
546 struct intel_display *display = to_intel_display(plane); in i9xx_cursor_disable_sel_fetch_arm() local
547 enum pipe pipe = plane->pipe; in i9xx_cursor_disable_sel_fetch_arm() local
549 if (!crtc_state->enable_psr2_sel_fetch) in i9xx_cursor_disable_sel_fetch_arm()
552 intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0); in i9xx_cursor_disable_sel_fetch_arm()
560 struct intel_display *display = to_intel_display(plane); in wa_16021440873() local
561 u32 ctl = plane_state->ctl; in wa_16021440873()
562 int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1; in wa_16021440873()
563 enum pipe pipe = plane->pipe; in wa_16021440873() local
568 intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl); in wa_16021440873()
570 intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), in wa_16021440873()
579 struct intel_display *display = to_intel_display(plane); in i9xx_cursor_update_sel_fetch_arm() local
580 enum pipe pipe = plane->pipe; in i9xx_cursor_update_sel_fetch_arm() local
582 if (!crtc_state->enable_psr2_sel_fetch) in i9xx_cursor_update_sel_fetch_arm()
585 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) { in i9xx_cursor_update_sel_fetch_arm()
586 if (crtc_state->enable_psr2_su_region_et) { in i9xx_cursor_update_sel_fetch_arm()
590 intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val); in i9xx_cursor_update_sel_fetch_arm()
593 intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl); in i9xx_cursor_update_sel_fetch_arm()
596 if (crtc_state->enable_psr2_su_region_et) in i9xx_cursor_update_sel_fetch_arm()
605 if (!entry->end) in skl_cursor_ddb_reg_val()
608 return CUR_BUF_END(entry->end - 1) | in skl_cursor_ddb_reg_val()
609 CUR_BUF_START(entry->start); in skl_cursor_ddb_reg_val()
616 if (level->enable) in skl_cursor_wm_reg_val()
618 if (level->ignore_lines) in skl_cursor_wm_reg_val()
620 val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks); in skl_cursor_wm_reg_val()
621 val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines); in skl_cursor_wm_reg_val()
630 struct intel_display *display = to_intel_display(plane->base.dev); in skl_write_cursor_wm() local
631 enum plane_id plane_id = plane->id; in skl_write_cursor_wm()
632 enum pipe pipe = plane->pipe; in skl_write_cursor_wm() local
633 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_cursor_wm()
635 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
638 for (level = 0; level < display->wm.num_levels; level++) in skl_write_cursor_wm()
639 intel_de_write_dsb(display, dsb, CUR_WM(pipe, level), in skl_write_cursor_wm()
642 intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe), in skl_write_cursor_wm()
645 if (HAS_HW_SAGV_WM(display)) { in skl_write_cursor_wm()
646 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_write_cursor_wm()
648 intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe), in skl_write_cursor_wm()
649 skl_cursor_wm_reg_val(&wm->sagv.wm0)); in skl_write_cursor_wm()
650 intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe), in skl_write_cursor_wm()
651 skl_cursor_wm_reg_val(&wm->sagv.trans_wm)); in skl_write_cursor_wm()
654 intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe), in skl_write_cursor_wm()
664 struct intel_display *display = to_intel_display(plane); in i9xx_cursor_update_arm() local
665 enum pipe pipe = plane->pipe; in i9xx_cursor_update_arm() local
668 if (plane_state && plane_state->uapi.visible) { in i9xx_cursor_update_arm()
669 int width = drm_rect_width(&plane_state->uapi.dst); in i9xx_cursor_update_arm()
670 int height = drm_rect_height(&plane_state->uapi.dst); in i9xx_cursor_update_arm()
672 cntl = plane_state->ctl | in i9xx_cursor_update_arm()
676 fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1); in i9xx_cursor_update_arm()
702 if (DISPLAY_VER(display) >= 9) in i9xx_cursor_update_arm()
710 if (plane->cursor.base != base || in i9xx_cursor_update_arm()
711 plane->cursor.size != fbc_ctl || in i9xx_cursor_update_arm()
712 plane->cursor.cntl != cntl) { in i9xx_cursor_update_arm()
713 if (HAS_CUR_FBC(display)) in i9xx_cursor_update_arm()
714 intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl); in i9xx_cursor_update_arm()
715 intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl); in i9xx_cursor_update_arm()
716 intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); in i9xx_cursor_update_arm()
717 intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); in i9xx_cursor_update_arm()
719 plane->cursor.base = base; in i9xx_cursor_update_arm()
720 plane->cursor.size = fbc_ctl; in i9xx_cursor_update_arm()
721 plane->cursor.cntl = cntl; in i9xx_cursor_update_arm()
723 intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); in i9xx_cursor_update_arm()
724 intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); in i9xx_cursor_update_arm()
736 enum pipe *pipe) in i9xx_cursor_get_hw_state() argument
738 struct intel_display *display = to_intel_display(plane); in i9xx_cursor_get_hw_state() local
746 * but that's only the case for gen2-3 which don't have any in i9xx_cursor_get_hw_state()
747 * display power wells. in i9xx_cursor_get_hw_state()
749 power_domain = POWER_DOMAIN_PIPE(plane->pipe); in i9xx_cursor_get_hw_state()
750 wakeref = intel_display_power_get_if_enabled(display, power_domain); in i9xx_cursor_get_hw_state()
754 val = intel_de_read(display, CURCNTR(display, plane->pipe)); in i9xx_cursor_get_hw_state()
758 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in i9xx_cursor_get_hw_state()
759 *pipe = plane->pipe; in i9xx_cursor_get_hw_state()
761 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); in i9xx_cursor_get_hw_state()
763 intel_display_power_put(display, power_domain, wakeref); in i9xx_cursor_get_hw_state()
772 struct intel_display *display = to_intel_display(plane); in g4x_cursor_capture_error() local
774 error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe)); in g4x_cursor_capture_error()
775 error->surf = intel_de_read(display, CURBASE(display, crtc->pipe)); in g4x_cursor_capture_error()
776 error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe)); in g4x_cursor_capture_error()
783 struct intel_display *display = to_intel_display(plane); in i9xx_cursor_capture_error() local
785 error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe)); in i9xx_cursor_capture_error()
786 error->surf = intel_de_read(display, CURBASE(display, crtc->pipe)); in i9xx_cursor_capture_error()
803 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_cursor_unpin_work()
806 intel_plane_destroy_state(&plane->base, &plane_state->uapi); in intel_cursor_unpin_work()
821 struct intel_display *display = to_intel_display(plane); in intel_legacy_cursor_update() local
823 to_intel_plane_state(plane->base.state); in intel_legacy_cursor_update()
826 to_intel_crtc_state(crtc->base.state); in intel_legacy_cursor_update()
840 if (!crtc_state->hw.active || in intel_legacy_cursor_update()
843 crtc_state->joiner_pipes) in intel_legacy_cursor_update()
851 if (old_plane_state->uapi.commit && in intel_legacy_cursor_update()
852 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) in intel_legacy_cursor_update()
860 if (old_plane_state->uapi.crtc != &crtc->base || in intel_legacy_cursor_update()
861 old_plane_state->uapi.src_w != src_w || in intel_legacy_cursor_update()
862 old_plane_state->uapi.src_h != src_h || in intel_legacy_cursor_update()
863 old_plane_state->uapi.crtc_w != crtc_w || in intel_legacy_cursor_update()
864 old_plane_state->uapi.crtc_h != crtc_h || in intel_legacy_cursor_update()
865 !old_plane_state->uapi.fb != !fb) in intel_legacy_cursor_update()
868 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); in intel_legacy_cursor_update()
870 return -ENOMEM; in intel_legacy_cursor_update()
872 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); in intel_legacy_cursor_update()
874 ret = -ENOMEM; in intel_legacy_cursor_update()
878 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); in intel_legacy_cursor_update()
880 new_plane_state->uapi.src_x = src_x; in intel_legacy_cursor_update()
881 new_plane_state->uapi.src_y = src_y; in intel_legacy_cursor_update()
882 new_plane_state->uapi.src_w = src_w; in intel_legacy_cursor_update()
883 new_plane_state->uapi.src_h = src_h; in intel_legacy_cursor_update()
884 new_plane_state->uapi.crtc_x = crtc_x; in intel_legacy_cursor_update()
885 new_plane_state->uapi.crtc_y = crtc_y; in intel_legacy_cursor_update()
886 new_plane_state->uapi.crtc_w = crtc_w; in intel_legacy_cursor_update()
887 new_plane_state->uapi.crtc_h = crtc_h; in intel_legacy_cursor_update()
900 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), in intel_legacy_cursor_update()
902 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), in intel_legacy_cursor_update()
903 to_intel_frontbuffer(new_plane_state->hw.fb), in intel_legacy_cursor_update()
904 plane->frontbuffer_bit); in intel_legacy_cursor_update()
907 plane->base.state = &new_plane_state->uapi; in intel_legacy_cursor_update()
912 * destroy the old state, we will cause a use-after-free there. in intel_legacy_cursor_update()
919 crtc_state->active_planes = new_crtc_state->active_planes; in intel_legacy_cursor_update()
925 if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) { in intel_legacy_cursor_update()
936 drm_crtc_vblank_put(&crtc->base); in intel_legacy_cursor_update()
941 if (new_plane_state->uapi.visible) { in intel_legacy_cursor_update()
952 if (old_plane_state->ggtt_vma != new_plane_state->ggtt_vma) { in intel_legacy_cursor_update()
953 drm_vblank_work_init(&old_plane_state->unpin_work, &crtc->base, in intel_legacy_cursor_update()
956 drm_vblank_work_schedule(&old_plane_state->unpin_work, in intel_legacy_cursor_update()
957 drm_crtc_accurate_vblank_count(&crtc->base) + 1, in intel_legacy_cursor_update()
967 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); in intel_legacy_cursor_update()
969 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); in intel_legacy_cursor_update()
971 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); in intel_legacy_cursor_update()
975 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, in intel_legacy_cursor_update()
991 struct intel_display *display = to_intel_display(plane); in intel_cursor_add_size_hints_property() local
992 const struct drm_mode_config *config = &display->drm->mode_config; in intel_cursor_add_size_hints_property()
996 max_size = min(config->cursor_width, config->cursor_height); in intel_cursor_add_size_hints_property()
1000 if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints))) in intel_cursor_add_size_hints_property()
1008 drm_plane_add_size_hints_property(&plane->base, hints, num_hints); in intel_cursor_add_size_hints_property()
1012 intel_cursor_plane_create(struct intel_display *display, in intel_cursor_plane_create() argument
1013 enum pipe pipe) in intel_cursor_plane_create() argument
1023 cursor->pipe = pipe; in intel_cursor_plane_create()
1024 cursor->i9xx_plane = (enum i9xx_plane_id) pipe; in intel_cursor_plane_create()
1025 cursor->id = PLANE_CURSOR; in intel_cursor_plane_create()
1026 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); in intel_cursor_plane_create()
1028 if (display->platform.i845g || display->platform.i865g) { in intel_cursor_plane_create()
1029 cursor->max_stride = i845_cursor_max_stride; in intel_cursor_plane_create()
1030 cursor->min_alignment = i845_cursor_min_alignment; in intel_cursor_plane_create()
1031 cursor->update_arm = i845_cursor_update_arm; in intel_cursor_plane_create()
1032 cursor->disable_arm = i845_cursor_disable_arm; in intel_cursor_plane_create()
1033 cursor->get_hw_state = i845_cursor_get_hw_state; in intel_cursor_plane_create()
1034 cursor->check_plane = i845_check_cursor; in intel_cursor_plane_create()
1036 cursor->max_stride = i9xx_cursor_max_stride; in intel_cursor_plane_create()
1038 if (display->platform.i830) in intel_cursor_plane_create()
1039 cursor->min_alignment = i830_cursor_min_alignment; in intel_cursor_plane_create()
1040 else if (display->platform.i85x) in intel_cursor_plane_create()
1041 cursor->min_alignment = i85x_cursor_min_alignment; in intel_cursor_plane_create()
1043 cursor->min_alignment = i9xx_cursor_min_alignment; in intel_cursor_plane_create()
1045 if (intel_scanout_needs_vtd_wa(display)) in intel_cursor_plane_create()
1046 cursor->vtd_guard = 2; in intel_cursor_plane_create()
1048 cursor->update_arm = i9xx_cursor_update_arm; in intel_cursor_plane_create()
1049 cursor->disable_arm = i9xx_cursor_disable_arm; in intel_cursor_plane_create()
1050 cursor->get_hw_state = i9xx_cursor_get_hw_state; in intel_cursor_plane_create()
1051 cursor->check_plane = i9xx_check_cursor; in intel_cursor_plane_create()
1054 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_cursor_plane_create()
1055 cursor->capture_error = g4x_cursor_capture_error; in intel_cursor_plane_create()
1057 cursor->capture_error = i9xx_cursor_capture_error; in intel_cursor_plane_create()
1059 cursor->cursor.base = ~0; in intel_cursor_plane_create()
1060 cursor->cursor.cntl = ~0; in intel_cursor_plane_create()
1062 if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display)) in intel_cursor_plane_create()
1063 cursor->cursor.size = ~0; in intel_cursor_plane_create()
1065 modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE); in intel_cursor_plane_create()
1067 ret = drm_universal_plane_init(display->drm, &cursor->base, in intel_cursor_plane_create()
1073 "cursor %c", pipe_name(pipe)); in intel_cursor_plane_create()
1080 if (DISPLAY_VER(display) >= 4) in intel_cursor_plane_create()
1081 drm_plane_create_rotation_property(&cursor->base, in intel_cursor_plane_create()
1088 zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1; in intel_cursor_plane_create()
1089 drm_plane_create_zpos_immutable_property(&cursor->base, zpos); in intel_cursor_plane_create()
1091 if (DISPLAY_VER(display) >= 12) in intel_cursor_plane_create()
1092 drm_plane_enable_fb_damage_clips(&cursor->base); in intel_cursor_plane_create()