1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 #include <linux/kernel.h>
6 
7 #include <drm/drm_atomic_helper.h>
8 #include <drm/drm_atomic_uapi.h>
9 #include <drm/drm_blend.h>
10 #include <drm/drm_damage_helper.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_vblank.h>
13 
14 #include "i915_drv.h"
15 #include "i915_reg.h"
16 #include "intel_atomic.h"
17 #include "intel_atomic_plane.h"
18 #include "intel_cursor.h"
19 #include "intel_cursor_regs.h"
20 #include "intel_de.h"
21 #include "intel_display.h"
22 #include "intel_display_types.h"
23 #include "intel_fb.h"
24 #include "intel_fb_pin.h"
25 #include "intel_frontbuffer.h"
26 #include "intel_psr.h"
27 #include "intel_psr_regs.h"
28 #include "intel_vblank.h"
29 #include "skl_watermark.h"
30 
31 /* Cursor formats */
32 static const u32 intel_cursor_formats[] = {
33 	DRM_FORMAT_ARGB8888,
34 };
35 
intel_cursor_base(const struct intel_plane_state * plane_state)36 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
37 {
38 	struct intel_display *display = to_intel_display(plane_state);
39 	u32 base;
40 
41 	if (DISPLAY_INFO(display)->cursor_needs_physical)
42 		base = plane_state->phys_dma_addr;
43 	else
44 		base = intel_plane_ggtt_offset(plane_state);
45 
46 	return base + plane_state->view.color_plane[0].offset;
47 }
48 
intel_cursor_position(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,bool early_tpt)49 static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,
50 				 const struct intel_plane_state *plane_state,
51 				 bool early_tpt)
52 {
53 	int x = plane_state->uapi.dst.x1;
54 	int y = plane_state->uapi.dst.y1;
55 	u32 pos = 0;
56 
57 	/*
58 	 * Formula from Bspec:
59 	 * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode
60 	 * select setting> + 1, CUR_POS Y Position - Update region Y position
61 	 */
62 	if (early_tpt)
63 		y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,
64 			y - crtc_state->psr2_su_area.y1);
65 
66 	if (x < 0) {
67 		pos |= CURSOR_POS_X_SIGN;
68 		x = -x;
69 	}
70 	pos |= CURSOR_POS_X(x);
71 
72 	if (y < 0) {
73 		pos |= CURSOR_POS_Y_SIGN;
74 		y = -y;
75 	}
76 	pos |= CURSOR_POS_Y(y);
77 
78 	return pos;
79 }
80 
intel_cursor_size_ok(const struct intel_plane_state * plane_state)81 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
82 {
83 	const struct drm_mode_config *config =
84 		&plane_state->uapi.plane->dev->mode_config;
85 	int width = drm_rect_width(&plane_state->uapi.dst);
86 	int height = drm_rect_height(&plane_state->uapi.dst);
87 
88 	return width > 0 && width <= config->cursor_width &&
89 		height > 0 && height <= config->cursor_height;
90 }
91 
intel_cursor_check_surface(struct intel_plane_state * plane_state)92 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
93 {
94 	struct intel_display *display = to_intel_display(plane_state);
95 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
96 	unsigned int rotation = plane_state->hw.rotation;
97 	int src_x, src_y;
98 	u32 offset;
99 	int ret;
100 
101 	ret = intel_plane_compute_gtt(plane_state);
102 	if (ret)
103 		return ret;
104 
105 	if (!plane_state->uapi.visible)
106 		return 0;
107 
108 	src_x = plane_state->uapi.src.x1 >> 16;
109 	src_y = plane_state->uapi.src.y1 >> 16;
110 
111 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
112 	offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
113 						    plane_state, 0);
114 
115 	if (src_x != 0 || src_y != 0) {
116 		drm_dbg_kms(display->drm,
117 			    "[PLANE:%d:%s] arbitrary cursor panning not supported\n",
118 			    plane->base.base.id, plane->base.name);
119 		return -EINVAL;
120 	}
121 
122 	/*
123 	 * Put the final coordinates back so that the src
124 	 * coordinate checks will see the right values.
125 	 */
126 	drm_rect_translate_to(&plane_state->uapi.src,
127 			      src_x << 16, src_y << 16);
128 
129 	/* ILK+ do this automagically in hardware */
130 	if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) {
131 		const struct drm_framebuffer *fb = plane_state->hw.fb;
132 		int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
133 		int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
134 
135 		offset += (src_h * src_w - 1) * fb->format->cpp[0];
136 	}
137 
138 	plane_state->view.color_plane[0].offset = offset;
139 	plane_state->view.color_plane[0].x = src_x;
140 	plane_state->view.color_plane[0].y = src_y;
141 
142 	return 0;
143 }
144 
intel_check_cursor(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)145 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
146 			      struct intel_plane_state *plane_state)
147 {
148 	struct intel_display *display = to_intel_display(plane_state);
149 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
150 	const struct drm_framebuffer *fb = plane_state->hw.fb;
151 	const struct drm_rect src = plane_state->uapi.src;
152 	const struct drm_rect dst = plane_state->uapi.dst;
153 	int ret;
154 
155 	if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
156 		drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n",
157 			    plane->base.base.id, plane->base.name);
158 		return -EINVAL;
159 	}
160 
161 	ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
162 						DRM_PLANE_NO_SCALING,
163 						DRM_PLANE_NO_SCALING,
164 						true);
165 	if (ret)
166 		return ret;
167 
168 	/* Use the unclipped src/dst rectangles, which we program to hw */
169 	plane_state->uapi.src = src;
170 	plane_state->uapi.dst = dst;
171 
172 	/* final plane coordinates will be relative to the plane's pipe */
173 	drm_rect_translate(&plane_state->uapi.dst,
174 			   -crtc_state->pipe_src.x1,
175 			   -crtc_state->pipe_src.y1);
176 
177 	ret = intel_cursor_check_surface(plane_state);
178 	if (ret)
179 		return ret;
180 
181 	if (!plane_state->uapi.visible)
182 		return 0;
183 
184 	ret = intel_plane_check_src_coordinates(plane_state);
185 	if (ret)
186 		return ret;
187 
188 	return 0;
189 }
190 
191 static unsigned int
i845_cursor_max_stride(struct intel_plane * plane,u32 pixel_format,u64 modifier,unsigned int rotation)192 i845_cursor_max_stride(struct intel_plane *plane,
193 		       u32 pixel_format, u64 modifier,
194 		       unsigned int rotation)
195 {
196 	return 2048;
197 }
198 
i845_cursor_min_alignment(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane)199 static unsigned int i845_cursor_min_alignment(struct intel_plane *plane,
200 					      const struct drm_framebuffer *fb,
201 					      int color_plane)
202 {
203 	return 32;
204 }
205 
i845_cursor_ctl_crtc(const struct intel_crtc_state * crtc_state)206 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
207 {
208 	u32 cntl = 0;
209 
210 	if (crtc_state->gamma_enable)
211 		cntl |= CURSOR_PIPE_GAMMA_ENABLE;
212 
213 	return cntl;
214 }
215 
i845_cursor_ctl(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)216 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
217 			   const struct intel_plane_state *plane_state)
218 {
219 	return CURSOR_ENABLE |
220 		CURSOR_FORMAT_ARGB |
221 		CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
222 }
223 
i845_cursor_size_ok(const struct intel_plane_state * plane_state)224 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
225 {
226 	int width = drm_rect_width(&plane_state->uapi.dst);
227 
228 	/*
229 	 * 845g/865g are only limited by the width of their cursors,
230 	 * the height is arbitrary up to the precision of the register.
231 	 */
232 	return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
233 }
234 
i845_check_cursor(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)235 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
236 			     struct intel_plane_state *plane_state)
237 {
238 	struct intel_display *display = to_intel_display(plane_state);
239 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
240 	const struct drm_framebuffer *fb = plane_state->hw.fb;
241 	int ret;
242 
243 	ret = intel_check_cursor(crtc_state, plane_state);
244 	if (ret)
245 		return ret;
246 
247 	/* if we want to turn off the cursor ignore width and height */
248 	if (!fb)
249 		return 0;
250 
251 	/* Check for which cursor types we support */
252 	if (!i845_cursor_size_ok(plane_state)) {
253 		drm_dbg_kms(display->drm,
254 			    "[PLANE:%d:%s] cursor dimension %dx%d not supported\n",
255 			    plane->base.base.id, plane->base.name,
256 			    drm_rect_width(&plane_state->uapi.dst),
257 			    drm_rect_height(&plane_state->uapi.dst));
258 		return -EINVAL;
259 	}
260 
261 	drm_WARN_ON(display->drm, plane_state->uapi.visible &&
262 		    plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
263 
264 	switch (fb->pitches[0]) {
265 	case 256:
266 	case 512:
267 	case 1024:
268 	case 2048:
269 		break;
270 	default:
271 		 drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n",
272 			     plane->base.base.id, plane->base.name,
273 			     fb->pitches[0]);
274 		return -EINVAL;
275 	}
276 
277 	plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
278 
279 	return 0;
280 }
281 
282 /* TODO: split into noarm+arm pair */
i845_cursor_update_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)283 static void i845_cursor_update_arm(struct intel_dsb *dsb,
284 				   struct intel_plane *plane,
285 				   const struct intel_crtc_state *crtc_state,
286 				   const struct intel_plane_state *plane_state)
287 {
288 	struct intel_display *display = to_intel_display(plane);
289 	u32 cntl = 0, base = 0, pos = 0, size = 0;
290 
291 	if (plane_state && plane_state->uapi.visible) {
292 		unsigned int width = drm_rect_width(&plane_state->uapi.dst);
293 		unsigned int height = drm_rect_height(&plane_state->uapi.dst);
294 
295 		cntl = plane_state->ctl |
296 			i845_cursor_ctl_crtc(crtc_state);
297 
298 		size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
299 
300 		base = intel_cursor_base(plane_state);
301 		pos = intel_cursor_position(crtc_state, plane_state, false);
302 	}
303 
304 	/* On these chipsets we can only modify the base/size/stride
305 	 * whilst the cursor is disabled.
306 	 */
307 	if (plane->cursor.base != base ||
308 	    plane->cursor.size != size ||
309 	    plane->cursor.cntl != cntl) {
310 		intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0);
311 		intel_de_write_fw(display, CURBASE(display, PIPE_A), base);
312 		intel_de_write_fw(display, CURSIZE(display, PIPE_A), size);
313 		intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);
314 		intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl);
315 
316 		plane->cursor.base = base;
317 		plane->cursor.size = size;
318 		plane->cursor.cntl = cntl;
319 	} else {
320 		intel_de_write_fw(display, CURPOS(display, PIPE_A), pos);
321 	}
322 }
323 
i845_cursor_disable_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state)324 static void i845_cursor_disable_arm(struct intel_dsb *dsb,
325 				    struct intel_plane *plane,
326 				    const struct intel_crtc_state *crtc_state)
327 {
328 	i845_cursor_update_arm(dsb, plane, crtc_state, NULL);
329 }
330 
i845_cursor_get_hw_state(struct intel_plane * plane,enum pipe * pipe)331 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
332 				     enum pipe *pipe)
333 {
334 	struct intel_display *display = to_intel_display(plane);
335 	enum intel_display_power_domain power_domain;
336 	intel_wakeref_t wakeref;
337 	bool ret;
338 
339 	power_domain = POWER_DOMAIN_PIPE(PIPE_A);
340 	wakeref = intel_display_power_get_if_enabled(display, power_domain);
341 	if (!wakeref)
342 		return false;
343 
344 	ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;
345 
346 	*pipe = PIPE_A;
347 
348 	intel_display_power_put(display, power_domain, wakeref);
349 
350 	return ret;
351 }
352 
353 static unsigned int
i9xx_cursor_max_stride(struct intel_plane * plane,u32 pixel_format,u64 modifier,unsigned int rotation)354 i9xx_cursor_max_stride(struct intel_plane *plane,
355 		       u32 pixel_format, u64 modifier,
356 		       unsigned int rotation)
357 {
358 	return plane->base.dev->mode_config.cursor_width * 4;
359 }
360 
i830_cursor_min_alignment(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane)361 static unsigned int i830_cursor_min_alignment(struct intel_plane *plane,
362 					      const struct drm_framebuffer *fb,
363 					      int color_plane)
364 {
365 	/* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned." */
366 	return 16 * 1024; /* physical */
367 }
368 
i85x_cursor_min_alignment(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane)369 static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane,
370 					      const struct drm_framebuffer *fb,
371 					      int color_plane)
372 {
373 	return 256; /* physical */
374 }
375 
i9xx_cursor_min_alignment(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane)376 static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane,
377 					      const struct drm_framebuffer *fb,
378 					      int color_plane)
379 {
380 	struct intel_display *display = to_intel_display(plane);
381 
382 	if (intel_scanout_needs_vtd_wa(display))
383 		return 64 * 1024;
384 
385 	return 4 * 1024; /* physical for i915/i945 */
386 }
387 
i9xx_cursor_ctl_crtc(const struct intel_crtc_state * crtc_state)388 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
389 {
390 	struct intel_display *display = to_intel_display(crtc_state);
391 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
392 	u32 cntl = 0;
393 
394 	if (DISPLAY_VER(display) >= 11)
395 		return cntl;
396 
397 	if (crtc_state->gamma_enable)
398 		cntl = MCURSOR_PIPE_GAMMA_ENABLE;
399 
400 	if (crtc_state->csc_enable)
401 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
402 
403 	if (DISPLAY_VER(display) < 5 && !display->platform.g4x)
404 		cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
405 
406 	return cntl;
407 }
408 
i9xx_cursor_ctl(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)409 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
410 			   const struct intel_plane_state *plane_state)
411 {
412 	struct intel_display *display = to_intel_display(plane_state);
413 	u32 cntl = 0;
414 
415 	if (display->platform.sandybridge || display->platform.ivybridge)
416 		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
417 
418 	switch (drm_rect_width(&plane_state->uapi.dst)) {
419 	case 64:
420 		cntl |= MCURSOR_MODE_64_ARGB_AX;
421 		break;
422 	case 128:
423 		cntl |= MCURSOR_MODE_128_ARGB_AX;
424 		break;
425 	case 256:
426 		cntl |= MCURSOR_MODE_256_ARGB_AX;
427 		break;
428 	default:
429 		MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
430 		return 0;
431 	}
432 
433 	if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
434 		cntl |= MCURSOR_ROTATE_180;
435 
436 	/* Wa_22012358565:adl-p */
437 	if (DISPLAY_VER(display) == 13)
438 		cntl |= MCURSOR_ARB_SLOTS(1);
439 
440 	return cntl;
441 }
442 
i9xx_cursor_size_ok(const struct intel_plane_state * plane_state)443 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
444 {
445 	struct intel_display *display = to_intel_display(plane_state);
446 	int width = drm_rect_width(&plane_state->uapi.dst);
447 	int height = drm_rect_height(&plane_state->uapi.dst);
448 
449 	if (!intel_cursor_size_ok(plane_state))
450 		return false;
451 
452 	/* Cursor width is limited to a few power-of-two sizes */
453 	switch (width) {
454 	case 256:
455 	case 128:
456 	case 64:
457 		break;
458 	default:
459 		return false;
460 	}
461 
462 	/*
463 	 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
464 	 * height from 8 lines up to the cursor width, when the
465 	 * cursor is not rotated. Everything else requires square
466 	 * cursors.
467 	 */
468 	if (HAS_CUR_FBC(display) &&
469 	    plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
470 		if (height < 8 || height > width)
471 			return false;
472 	} else {
473 		if (height != width)
474 			return false;
475 	}
476 
477 	return true;
478 }
479 
i9xx_check_cursor(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)480 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
481 			     struct intel_plane_state *plane_state)
482 {
483 	struct intel_display *display = to_intel_display(plane_state);
484 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
485 	const struct drm_framebuffer *fb = plane_state->hw.fb;
486 	enum pipe pipe = plane->pipe;
487 	int ret;
488 
489 	ret = intel_check_cursor(crtc_state, plane_state);
490 	if (ret)
491 		return ret;
492 
493 	/* if we want to turn off the cursor ignore width and height */
494 	if (!fb)
495 		return 0;
496 
497 	/* Check for which cursor types we support */
498 	if (!i9xx_cursor_size_ok(plane_state)) {
499 		drm_dbg_kms(display->drm,
500 			    "[PLANE:%d:%s] cursor dimension %dx%d not supported\n",
501 			    plane->base.base.id, plane->base.name,
502 			    drm_rect_width(&plane_state->uapi.dst),
503 			    drm_rect_height(&plane_state->uapi.dst));
504 		return -EINVAL;
505 	}
506 
507 	drm_WARN_ON(display->drm, plane_state->uapi.visible &&
508 		    plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
509 
510 	if (fb->pitches[0] !=
511 	    drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
512 		drm_dbg_kms(display->drm,
513 			    "[PLANE:%d:%s] invalid cursor stride (%u) (cursor width %d)\n",
514 			    plane->base.base.id, plane->base.name,
515 			    fb->pitches[0], drm_rect_width(&plane_state->uapi.dst));
516 		return -EINVAL;
517 	}
518 
519 	/*
520 	 * There's something wrong with the cursor on CHV pipe C.
521 	 * If it straddles the left edge of the screen then
522 	 * moving it away from the edge or disabling it often
523 	 * results in a pipe underrun, and often that can lead to
524 	 * dead pipe (constant underrun reported, and it scans
525 	 * out just a solid color). To recover from that, the
526 	 * display power well must be turned off and on again.
527 	 * Refuse the put the cursor into that compromised position.
528 	 */
529 	if (display->platform.cherryview && pipe == PIPE_C &&
530 	    plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
531 		drm_dbg_kms(display->drm,
532 			    "[PLANE:%d:%s] cursor not allowed to straddle the left screen edge\n",
533 			    plane->base.base.id, plane->base.name);
534 		return -EINVAL;
535 	}
536 
537 	plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
538 
539 	return 0;
540 }
541 
i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state)542 static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
543 					      struct intel_plane *plane,
544 					      const struct intel_crtc_state *crtc_state)
545 {
546 	struct intel_display *display = to_intel_display(plane);
547 	enum pipe pipe = plane->pipe;
548 
549 	if (!crtc_state->enable_psr2_sel_fetch)
550 		return;
551 
552 	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
553 }
554 
wa_16021440873(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)555 static void wa_16021440873(struct intel_dsb *dsb,
556 			   struct intel_plane *plane,
557 			   const struct intel_crtc_state *crtc_state,
558 			   const struct intel_plane_state *plane_state)
559 {
560 	struct intel_display *display = to_intel_display(plane);
561 	u32 ctl = plane_state->ctl;
562 	int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1;
563 	enum pipe pipe = plane->pipe;
564 
565 	ctl &= ~MCURSOR_MODE_MASK;
566 	ctl |= MCURSOR_MODE_64_2B;
567 
568 	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl);
569 
570 	intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe),
571 			   CURSOR_POS_Y(et_y_position));
572 }
573 
i9xx_cursor_update_sel_fetch_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)574 static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb,
575 					     struct intel_plane *plane,
576 					     const struct intel_crtc_state *crtc_state,
577 					     const struct intel_plane_state *plane_state)
578 {
579 	struct intel_display *display = to_intel_display(plane);
580 	enum pipe pipe = plane->pipe;
581 
582 	if (!crtc_state->enable_psr2_sel_fetch)
583 		return;
584 
585 	if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {
586 		if (crtc_state->enable_psr2_su_region_et) {
587 			u32 val = intel_cursor_position(crtc_state, plane_state,
588 				true);
589 
590 			intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val);
591 		}
592 
593 		intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl);
594 	} else {
595 		/* Wa_16021440873 */
596 		if (crtc_state->enable_psr2_su_region_et)
597 			wa_16021440873(dsb, plane, crtc_state, plane_state);
598 		else
599 			i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);
600 	}
601 }
602 
skl_cursor_ddb_reg_val(const struct skl_ddb_entry * entry)603 static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
604 {
605 	if (!entry->end)
606 		return 0;
607 
608 	return CUR_BUF_END(entry->end - 1) |
609 		CUR_BUF_START(entry->start);
610 }
611 
skl_cursor_wm_reg_val(const struct skl_wm_level * level)612 static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
613 {
614 	u32 val = 0;
615 
616 	if (level->enable)
617 		val |= CUR_WM_EN;
618 	if (level->ignore_lines)
619 		val |= CUR_WM_IGNORE_LINES;
620 	val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
621 	val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
622 
623 	return val;
624 }
625 
skl_write_cursor_wm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state)626 static void skl_write_cursor_wm(struct intel_dsb *dsb,
627 				struct intel_plane *plane,
628 				const struct intel_crtc_state *crtc_state)
629 {
630 	struct intel_display *display = to_intel_display(plane->base.dev);
631 	enum plane_id plane_id = plane->id;
632 	enum pipe pipe = plane->pipe;
633 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
634 	const struct skl_ddb_entry *ddb =
635 		&crtc_state->wm.skl.plane_ddb[plane_id];
636 	int level;
637 
638 	for (level = 0; level < display->wm.num_levels; level++)
639 		intel_de_write_dsb(display, dsb, CUR_WM(pipe, level),
640 				   skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
641 
642 	intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe),
643 			   skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
644 
645 	if (HAS_HW_SAGV_WM(display)) {
646 		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
647 
648 		intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),
649 				   skl_cursor_wm_reg_val(&wm->sagv.wm0));
650 		intel_de_write_dsb(display, dsb, CUR_WM_SAGV_TRANS(pipe),
651 				   skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
652 	}
653 
654 	intel_de_write_dsb(display, dsb, CUR_BUF_CFG(pipe),
655 			   skl_cursor_ddb_reg_val(ddb));
656 }
657 
658 /* TODO: split into noarm+arm pair */
i9xx_cursor_update_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)659 static void i9xx_cursor_update_arm(struct intel_dsb *dsb,
660 				   struct intel_plane *plane,
661 				   const struct intel_crtc_state *crtc_state,
662 				   const struct intel_plane_state *plane_state)
663 {
664 	struct intel_display *display = to_intel_display(plane);
665 	enum pipe pipe = plane->pipe;
666 	u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
667 
668 	if (plane_state && plane_state->uapi.visible) {
669 		int width = drm_rect_width(&plane_state->uapi.dst);
670 		int height = drm_rect_height(&plane_state->uapi.dst);
671 
672 		cntl = plane_state->ctl |
673 			i9xx_cursor_ctl_crtc(crtc_state);
674 
675 		if (width != height)
676 			fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
677 
678 		base = intel_cursor_base(plane_state);
679 		pos = intel_cursor_position(crtc_state, plane_state, false);
680 	}
681 
682 	/*
683 	 * On some platforms writing CURCNTR first will also
684 	 * cause CURPOS to be armed by the CURBASE write.
685 	 * Without the CURCNTR write the CURPOS write would
686 	 * arm itself. Thus we always update CURCNTR before
687 	 * CURPOS.
688 	 *
689 	 * On other platforms CURPOS always requires the
690 	 * CURBASE write to arm the update. Additionally
691 	 * a write to any of the cursor register will cancel
692 	 * an already armed cursor update. Thus leaving out
693 	 * the CURBASE write after CURPOS could lead to a
694 	 * cursor that doesn't appear to move, or even change
695 	 * shape. Thus we always write CURBASE.
696 	 *
697 	 * The other registers are armed by the CURBASE write
698 	 * except when the plane is getting enabled at which time
699 	 * the CURCNTR write arms the update.
700 	 */
701 
702 	if (DISPLAY_VER(display) >= 9)
703 		skl_write_cursor_wm(dsb, plane, crtc_state);
704 
705 	if (plane_state)
706 		i9xx_cursor_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
707 	else
708 		i9xx_cursor_disable_sel_fetch_arm(dsb, plane, crtc_state);
709 
710 	if (plane->cursor.base != base ||
711 	    plane->cursor.size != fbc_ctl ||
712 	    plane->cursor.cntl != cntl) {
713 		if (HAS_CUR_FBC(display))
714 			intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl);
715 		intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl);
716 		intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);
717 		intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);
718 
719 		plane->cursor.base = base;
720 		plane->cursor.size = fbc_ctl;
721 		plane->cursor.cntl = cntl;
722 	} else {
723 		intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos);
724 		intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base);
725 	}
726 }
727 
i9xx_cursor_disable_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state)728 static void i9xx_cursor_disable_arm(struct intel_dsb *dsb,
729 				    struct intel_plane *plane,
730 				    const struct intel_crtc_state *crtc_state)
731 {
732 	i9xx_cursor_update_arm(dsb, plane, crtc_state, NULL);
733 }
734 
i9xx_cursor_get_hw_state(struct intel_plane * plane,enum pipe * pipe)735 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
736 				     enum pipe *pipe)
737 {
738 	struct intel_display *display = to_intel_display(plane);
739 	enum intel_display_power_domain power_domain;
740 	intel_wakeref_t wakeref;
741 	bool ret;
742 	u32 val;
743 
744 	/*
745 	 * Not 100% correct for planes that can move between pipes,
746 	 * but that's only the case for gen2-3 which don't have any
747 	 * display power wells.
748 	 */
749 	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
750 	wakeref = intel_display_power_get_if_enabled(display, power_domain);
751 	if (!wakeref)
752 		return false;
753 
754 	val = intel_de_read(display, CURCNTR(display, plane->pipe));
755 
756 	ret = val & MCURSOR_MODE_MASK;
757 
758 	if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
759 		*pipe = plane->pipe;
760 	else
761 		*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
762 
763 	intel_display_power_put(display, power_domain, wakeref);
764 
765 	return ret;
766 }
767 
g4x_cursor_capture_error(struct intel_crtc * crtc,struct intel_plane * plane,struct intel_plane_error * error)768 static void g4x_cursor_capture_error(struct intel_crtc *crtc,
769 				     struct intel_plane *plane,
770 				     struct intel_plane_error *error)
771 {
772 	struct intel_display *display = to_intel_display(plane);
773 
774 	error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));
775 	error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));
776 	error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));
777 }
778 
i9xx_cursor_capture_error(struct intel_crtc * crtc,struct intel_plane * plane,struct intel_plane_error * error)779 static void i9xx_cursor_capture_error(struct intel_crtc *crtc,
780 				      struct intel_plane *plane,
781 				      struct intel_plane_error *error)
782 {
783 	struct intel_display *display = to_intel_display(plane);
784 
785 	error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));
786 	error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));
787 }
788 
intel_cursor_format_mod_supported(struct drm_plane * _plane,u32 format,u64 modifier)789 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
790 					      u32 format, u64 modifier)
791 {
792 	if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
793 		return false;
794 
795 	return format == DRM_FORMAT_ARGB8888;
796 }
797 
intel_cursor_unpin_work(struct kthread_work * base)798 void intel_cursor_unpin_work(struct kthread_work *base)
799 {
800 	struct drm_vblank_work *work = to_drm_vblank_work(base);
801 	struct intel_plane_state *plane_state =
802 		container_of(work, typeof(*plane_state), unpin_work);
803 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
804 
805 	intel_plane_unpin_fb(plane_state);
806 	intel_plane_destroy_state(&plane->base, &plane_state->uapi);
807 }
808 
809 static int
intel_legacy_cursor_update(struct drm_plane * _plane,struct drm_crtc * _crtc,struct drm_framebuffer * fb,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,u32 src_x,u32 src_y,u32 src_w,u32 src_h,struct drm_modeset_acquire_ctx * ctx)810 intel_legacy_cursor_update(struct drm_plane *_plane,
811 			   struct drm_crtc *_crtc,
812 			   struct drm_framebuffer *fb,
813 			   int crtc_x, int crtc_y,
814 			   unsigned int crtc_w, unsigned int crtc_h,
815 			   u32 src_x, u32 src_y,
816 			   u32 src_w, u32 src_h,
817 			   struct drm_modeset_acquire_ctx *ctx)
818 {
819 	struct intel_plane *plane = to_intel_plane(_plane);
820 	struct intel_crtc *crtc = to_intel_crtc(_crtc);
821 	struct intel_display *display = to_intel_display(plane);
822 	struct intel_plane_state *old_plane_state =
823 		to_intel_plane_state(plane->base.state);
824 	struct intel_plane_state *new_plane_state;
825 	struct intel_crtc_state *crtc_state =
826 		to_intel_crtc_state(crtc->base.state);
827 	struct intel_crtc_state *new_crtc_state;
828 	struct intel_vblank_evade_ctx evade;
829 	int ret;
830 
831 	/*
832 	 * When crtc is inactive or there is a modeset pending,
833 	 * wait for it to complete in the slowpath.
834 	 * PSR2 selective fetch also requires the slow path as
835 	 * PSR2 plane and transcoder registers can only be updated during
836 	 * vblank.
837 	 *
838 	 * FIXME joiner fastpath would be good
839 	 */
840 	if (!crtc_state->hw.active ||
841 	    intel_crtc_needs_modeset(crtc_state) ||
842 	    intel_crtc_needs_fastset(crtc_state) ||
843 	    crtc_state->joiner_pipes)
844 		goto slow;
845 
846 	/*
847 	 * Don't do an async update if there is an outstanding commit modifying
848 	 * the plane.  This prevents our async update's changes from getting
849 	 * overridden by a previous synchronous update's state.
850 	 */
851 	if (old_plane_state->uapi.commit &&
852 	    !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
853 		goto slow;
854 
855 	/*
856 	 * If any parameters change that may affect watermarks,
857 	 * take the slowpath. Only changing fb or position should be
858 	 * in the fastpath.
859 	 */
860 	if (old_plane_state->uapi.crtc != &crtc->base ||
861 	    old_plane_state->uapi.src_w != src_w ||
862 	    old_plane_state->uapi.src_h != src_h ||
863 	    old_plane_state->uapi.crtc_w != crtc_w ||
864 	    old_plane_state->uapi.crtc_h != crtc_h ||
865 	    !old_plane_state->uapi.fb != !fb)
866 		goto slow;
867 
868 	new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
869 	if (!new_plane_state)
870 		return -ENOMEM;
871 
872 	new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
873 	if (!new_crtc_state) {
874 		ret = -ENOMEM;
875 		goto out_free;
876 	}
877 
878 	drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
879 
880 	new_plane_state->uapi.src_x = src_x;
881 	new_plane_state->uapi.src_y = src_y;
882 	new_plane_state->uapi.src_w = src_w;
883 	new_plane_state->uapi.src_h = src_h;
884 	new_plane_state->uapi.crtc_x = crtc_x;
885 	new_plane_state->uapi.crtc_y = crtc_y;
886 	new_plane_state->uapi.crtc_w = crtc_w;
887 	new_plane_state->uapi.crtc_h = crtc_h;
888 
889 	intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
890 
891 	ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
892 						  old_plane_state, new_plane_state);
893 	if (ret)
894 		goto out_free;
895 
896 	ret = intel_plane_pin_fb(new_plane_state, old_plane_state);
897 	if (ret)
898 		goto out_free;
899 
900 	intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
901 				ORIGIN_CURSOR_UPDATE);
902 	intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
903 				to_intel_frontbuffer(new_plane_state->hw.fb),
904 				plane->frontbuffer_bit);
905 
906 	/* Swap plane state */
907 	plane->base.state = &new_plane_state->uapi;
908 
909 	/*
910 	 * We cannot swap crtc_state as it may be in use by an atomic commit or
911 	 * page flip that's running simultaneously. If we swap crtc_state and
912 	 * destroy the old state, we will cause a use-after-free there.
913 	 *
914 	 * Only update active_planes, which is needed for our internal
915 	 * bookkeeping. Either value will do the right thing when updating
916 	 * planes atomically. If the cursor was part of the atomic update then
917 	 * we would have taken the slowpath.
918 	 */
919 	crtc_state->active_planes = new_crtc_state->active_planes;
920 
921 	intel_vblank_evade_init(crtc_state, crtc_state, &evade);
922 
923 	intel_psr_lock(crtc_state);
924 
925 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
926 		/*
927 		 * TODO: maybe check if we're still in PSR
928 		 * and skip the vblank evasion entirely?
929 		 */
930 		intel_psr_wait_for_idle_locked(crtc_state);
931 
932 		local_irq_disable();
933 
934 		intel_vblank_evade(&evade);
935 
936 		drm_crtc_vblank_put(&crtc->base);
937 	} else {
938 		local_irq_disable();
939 	}
940 
941 	if (new_plane_state->uapi.visible) {
942 		intel_plane_update_noarm(NULL, plane, crtc_state, new_plane_state);
943 		intel_plane_update_arm(NULL, plane, crtc_state, new_plane_state);
944 	} else {
945 		intel_plane_disable_arm(NULL, plane, crtc_state);
946 	}
947 
948 	local_irq_enable();
949 
950 	intel_psr_unlock(crtc_state);
951 
952 	if (old_plane_state->ggtt_vma != new_plane_state->ggtt_vma) {
953 		drm_vblank_work_init(&old_plane_state->unpin_work, &crtc->base,
954 				     intel_cursor_unpin_work);
955 
956 		drm_vblank_work_schedule(&old_plane_state->unpin_work,
957 					 drm_crtc_accurate_vblank_count(&crtc->base) + 1,
958 					 false);
959 
960 		old_plane_state = NULL;
961 	} else {
962 		intel_plane_unpin_fb(old_plane_state);
963 	}
964 
965 out_free:
966 	if (new_crtc_state)
967 		intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
968 	if (ret)
969 		intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
970 	else if (old_plane_state)
971 		intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
972 	return ret;
973 
974 slow:
975 	return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
976 					      crtc_x, crtc_y, crtc_w, crtc_h,
977 					      src_x, src_y, src_w, src_h, ctx);
978 }
979 
980 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
981 	.update_plane = intel_legacy_cursor_update,
982 	.disable_plane = drm_atomic_helper_disable_plane,
983 	.destroy = intel_plane_destroy,
984 	.atomic_duplicate_state = intel_plane_duplicate_state,
985 	.atomic_destroy_state = intel_plane_destroy_state,
986 	.format_mod_supported = intel_cursor_format_mod_supported,
987 };
988 
intel_cursor_add_size_hints_property(struct intel_plane * plane)989 static void intel_cursor_add_size_hints_property(struct intel_plane *plane)
990 {
991 	struct intel_display *display = to_intel_display(plane);
992 	const struct drm_mode_config *config = &display->drm->mode_config;
993 	struct drm_plane_size_hint hints[4];
994 	int size, max_size, num_hints = 0;
995 
996 	max_size = min(config->cursor_width, config->cursor_height);
997 
998 	/* for simplicity only enumerate the supported square+POT sizes */
999 	for (size = 64; size <= max_size; size *= 2) {
1000 		if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints)))
1001 			break;
1002 
1003 		hints[num_hints].width = size;
1004 		hints[num_hints].height = size;
1005 		num_hints++;
1006 	}
1007 
1008 	drm_plane_add_size_hints_property(&plane->base, hints, num_hints);
1009 }
1010 
1011 struct intel_plane *
intel_cursor_plane_create(struct intel_display * display,enum pipe pipe)1012 intel_cursor_plane_create(struct intel_display *display,
1013 			  enum pipe pipe)
1014 {
1015 	struct intel_plane *cursor;
1016 	int ret, zpos;
1017 	u64 *modifiers;
1018 
1019 	cursor = intel_plane_alloc();
1020 	if (IS_ERR(cursor))
1021 		return cursor;
1022 
1023 	cursor->pipe = pipe;
1024 	cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
1025 	cursor->id = PLANE_CURSOR;
1026 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
1027 
1028 	if (display->platform.i845g || display->platform.i865g) {
1029 		cursor->max_stride = i845_cursor_max_stride;
1030 		cursor->min_alignment = i845_cursor_min_alignment;
1031 		cursor->update_arm = i845_cursor_update_arm;
1032 		cursor->disable_arm = i845_cursor_disable_arm;
1033 		cursor->get_hw_state = i845_cursor_get_hw_state;
1034 		cursor->check_plane = i845_check_cursor;
1035 	} else {
1036 		cursor->max_stride = i9xx_cursor_max_stride;
1037 
1038 		if (display->platform.i830)
1039 			cursor->min_alignment = i830_cursor_min_alignment;
1040 		else if (display->platform.i85x)
1041 			cursor->min_alignment = i85x_cursor_min_alignment;
1042 		else
1043 			cursor->min_alignment = i9xx_cursor_min_alignment;
1044 
1045 		if (intel_scanout_needs_vtd_wa(display))
1046 			cursor->vtd_guard = 2;
1047 
1048 		cursor->update_arm = i9xx_cursor_update_arm;
1049 		cursor->disable_arm = i9xx_cursor_disable_arm;
1050 		cursor->get_hw_state = i9xx_cursor_get_hw_state;
1051 		cursor->check_plane = i9xx_check_cursor;
1052 	}
1053 
1054 	if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1055 		cursor->capture_error = g4x_cursor_capture_error;
1056 	else
1057 		cursor->capture_error = i9xx_cursor_capture_error;
1058 
1059 	cursor->cursor.base = ~0;
1060 	cursor->cursor.cntl = ~0;
1061 
1062 	if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display))
1063 		cursor->cursor.size = ~0;
1064 
1065 	modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE);
1066 
1067 	ret = drm_universal_plane_init(display->drm, &cursor->base,
1068 				       0, &intel_cursor_plane_funcs,
1069 				       intel_cursor_formats,
1070 				       ARRAY_SIZE(intel_cursor_formats),
1071 				       modifiers,
1072 				       DRM_PLANE_TYPE_CURSOR,
1073 				       "cursor %c", pipe_name(pipe));
1074 
1075 	kfree(modifiers);
1076 
1077 	if (ret)
1078 		goto fail;
1079 
1080 	if (DISPLAY_VER(display) >= 4)
1081 		drm_plane_create_rotation_property(&cursor->base,
1082 						   DRM_MODE_ROTATE_0,
1083 						   DRM_MODE_ROTATE_0 |
1084 						   DRM_MODE_ROTATE_180);
1085 
1086 	intel_cursor_add_size_hints_property(cursor);
1087 
1088 	zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1;
1089 	drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
1090 
1091 	if (DISPLAY_VER(display) >= 12)
1092 		drm_plane_enable_fb_damage_clips(&cursor->base);
1093 
1094 	intel_plane_helper_add(cursor);
1095 
1096 	return cursor;
1097 
1098 fail:
1099 	intel_plane_free(cursor);
1100 
1101 	return ERR_PTR(ret);
1102 }
1103