1 // SPDX-License-Identifier: MIT
19  * intel_link_bw_init_limits - initialize BW limits
28 	struct intel_display *display = to_intel_display(state);  in intel_link_bw_init_limits()  local
29 	enum pipe pipe;  in intel_link_bw_init_limits()  local
31 	limits->force_fec_pipes = 0;  in intel_link_bw_init_limits()
32 	limits->bpp_limit_reached_pipes = 0;  in intel_link_bw_init_limits()
33 	for_each_pipe(display, pipe) {  in intel_link_bw_init_limits()
36 							intel_crtc_for_pipe(display, pipe));  in intel_link_bw_init_limits()
38 		if (state->base.duplicated && crtc_state) {  in intel_link_bw_init_limits()
39 			limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;  in intel_link_bw_init_limits()
40 			if (crtc_state->fec_enable)  in intel_link_bw_init_limits()
41 				limits->force_fec_pipes |= BIT(pipe);  in intel_link_bw_init_limits()
43 			limits->max_bpp_x16[pipe] = INT_MAX;  in intel_link_bw_init_limits()
49  * intel_link_bw_reduce_bpp - reduce maximum link bpp for a selected pipe
55  * Select the pipe from @pipe_mask with the biggest link bpp value and set the
56  * maximum of link bpp in @limits below this value. Modeset the selected pipe,
60  * the link bpp of one pipe on the link and hence reducing the total link BW.
63  *   - 0 in case of success
64  *   - %-ENOSPC if no pipe can further reduce its link bpp
65  *   - Other negative error, if modesetting the selected pipe failed
72 	struct intel_display *display = to_intel_display(state);  in intel_link_bw_reduce_bpp()  local
73 	enum pipe max_bpp_pipe = INVALID_PIPE;  in intel_link_bw_reduce_bpp()
77 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {  in intel_link_bw_reduce_bpp()
81 		if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))  in intel_link_bw_reduce_bpp()
84 		crtc_state = intel_atomic_get_crtc_state(&state->base,  in intel_link_bw_reduce_bpp()
89 		if (crtc_state->dsc.compression_enable)  in intel_link_bw_reduce_bpp()
90 			link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;  in intel_link_bw_reduce_bpp()
94 			 * of the pipe bpp value. The MST encoder's BW allocation  in intel_link_bw_reduce_bpp()
95 			 * is based on the pipe bpp value, set the actual link bpp  in intel_link_bw_reduce_bpp()
98 			link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp);  in intel_link_bw_reduce_bpp()
102 			max_bpp_pipe = crtc->pipe;  in intel_link_bw_reduce_bpp()
107 		return -ENOSPC;  in intel_link_bw_reduce_bpp()
109 	limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1;  in intel_link_bw_reduce_bpp()
116  * intel_link_bw_set_bpp_limit_for_pipe - set link bpp limit for a pipe to its minimum
120  * @pipe: pipe
122  * Set the link bpp limit for @pipe in @new_limits to its value in
124  * called after a pipe's compute config function failed, @old_limits
128  * because the old and new limits match (and so would lead to a pipe compute
137 				     enum pipe pipe)  in intel_link_bw_set_bpp_limit_for_pipe()  argument
139 	struct intel_display *display = to_intel_display(state);  in intel_link_bw_set_bpp_limit_for_pipe()  local
141 	if (pipe == INVALID_PIPE)  in intel_link_bw_set_bpp_limit_for_pipe()
144 	if (new_limits->max_bpp_x16[pipe] ==  in intel_link_bw_set_bpp_limit_for_pipe()
145 	    old_limits->max_bpp_x16[pipe])  in intel_link_bw_set_bpp_limit_for_pipe()
148 	if (drm_WARN_ON(display->drm,  in intel_link_bw_set_bpp_limit_for_pipe()
149 			new_limits->bpp_limit_reached_pipes & BIT(pipe)))  in intel_link_bw_set_bpp_limit_for_pipe()
152 	new_limits->max_bpp_x16[pipe] =  in intel_link_bw_set_bpp_limit_for_pipe()
153 		old_limits->max_bpp_x16[pipe];  in intel_link_bw_set_bpp_limit_for_pipe()
154 	new_limits->bpp_limit_reached_pipes |= BIT(pipe);  in intel_link_bw_set_bpp_limit_for_pipe()
162 	/* TODO: Check additional shared display link configurations like MST */  in check_all_link_config()
181 assert_link_limit_change_valid(struct intel_display *display,  in assert_link_limit_change_valid()  argument
186 	enum pipe pipe;  in assert_link_limit_change_valid()  local
189 	if (drm_WARN_ON(display->drm,  in assert_link_limit_change_valid()
190 			(old_limits->force_fec_pipes & new_limits->force_fec_pipes) !=  in assert_link_limit_change_valid()
191 			old_limits->force_fec_pipes))  in assert_link_limit_change_valid()
194 	for_each_pipe(display, pipe) {  in assert_link_limit_change_valid()
196 		if (drm_WARN_ON(display->drm,  in assert_link_limit_change_valid()
197 				new_limits->max_bpp_x16[pipe] >  in assert_link_limit_change_valid()
198 				old_limits->max_bpp_x16[pipe]))  in assert_link_limit_change_valid()
201 		if (new_limits->max_bpp_x16[pipe] <  in assert_link_limit_change_valid()
202 		    old_limits->max_bpp_x16[pipe])  in assert_link_limit_change_valid()
207 	if (drm_WARN_ON(display->drm,  in assert_link_limit_change_valid()
209 			new_limits->force_fec_pipes ==  in assert_link_limit_change_valid()
210 			old_limits->force_fec_pipes))  in assert_link_limit_change_valid()
217  * intel_link_bw_atomic_check - check display link states and set a fallback config if needed
221  * Check the configuration of all shared display links in @state and set new BW
225  *   - 0 if the configuration is valid
226  *   - %-EAGAIN, if the configuration is invalid and @new_limits got updated
229  *   - Other negative error, if the configuration is invalid without a
235 	struct intel_display *display = to_intel_display(state);  in intel_link_bw_atomic_check()  local
240 	if (ret != -EAGAIN)  in intel_link_bw_atomic_check()
243 	if (!assert_link_limit_change_valid(display, &old_limits, new_limits))  in intel_link_bw_atomic_check()
244 		return -EINVAL;  in intel_link_bw_atomic_check()
246 	return -EAGAIN;  in intel_link_bw_atomic_check()