Lines Matching +full:display +full:- +full:pipe
1 // SPDX-License-Identifier: MIT
112 static bool i9xx_plane_has_fbc(struct intel_display *display, in i9xx_plane_has_fbc() argument
115 if (!HAS_FBC(display)) in i9xx_plane_has_fbc()
118 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
119 return i9xx_plane == PLANE_A; /* tied to pipe A */ in i9xx_plane_has_fbc()
120 else if (display->platform.ivybridge) in i9xx_plane_has_fbc()
123 else if (DISPLAY_VER(display) >= 4) in i9xx_plane_has_fbc()
129 static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, in i9xx_plane_fbc() argument
132 if (i9xx_plane_has_fbc(display, i9xx_plane)) in i9xx_plane_fbc()
133 return display->fbc[INTEL_FBC_A]; in i9xx_plane_fbc()
140 struct intel_display *display = to_intel_display(plane); in i9xx_plane_has_windowing() local
141 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_has_windowing()
143 if (display->platform.cherryview) in i9xx_plane_has_windowing()
145 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in i9xx_plane_has_windowing()
147 else if (DISPLAY_VER(display) == 4) in i9xx_plane_has_windowing()
157 struct intel_display *display = to_intel_display(plane_state); in i9xx_plane_ctl() local
158 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_plane_ctl()
159 unsigned int rotation = plane_state->hw.rotation; in i9xx_plane_ctl()
164 if (display->platform.g4x || display->platform.ironlake || in i9xx_plane_ctl()
165 display->platform.sandybridge || display->platform.ivybridge) in i9xx_plane_ctl()
168 switch (fb->format->format) { in i9xx_plane_ctl()
209 MISSING_CASE(fb->format->format); in i9xx_plane_ctl()
213 if (DISPLAY_VER(display) >= 4 && in i9xx_plane_ctl()
214 fb->modifier == I915_FORMAT_MOD_X_TILED) in i9xx_plane_ctl()
228 struct intel_display *display = to_intel_display(plane_state); in i9xx_check_plane_surface() local
229 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in i9xx_check_plane_surface()
230 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_check_plane_surface()
239 if (!plane_state->uapi.visible) in i9xx_check_plane_surface()
242 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in i9xx_check_plane_surface()
243 src_x = plane_state->uapi.src.x1 >> 16; in i9xx_check_plane_surface()
244 src_y = plane_state->uapi.src.y1 >> 16; in i9xx_check_plane_surface()
247 if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) { in i9xx_check_plane_surface()
248 drm_dbg_kms(display->drm, in i9xx_check_plane_surface()
250 plane->base.base.id, plane->base.name, src_w); in i9xx_check_plane_surface()
251 return -EINVAL; in i9xx_check_plane_surface()
256 if (DISPLAY_VER(display) >= 4) in i9xx_check_plane_surface()
263 * When using an X-tiled surface the plane starts to in i9xx_check_plane_surface()
273 if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { in i9xx_check_plane_surface()
274 unsigned int alignment = plane->min_alignment(plane, fb, 0); in i9xx_check_plane_surface()
275 int cpp = fb->format->cpp[0]; in i9xx_check_plane_surface()
277 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { in i9xx_check_plane_surface()
279 drm_dbg_kms(display->drm, in i9xx_check_plane_surface()
280 "[PLANE:%d:%s] unable to find suitable display surface offset due to X-tiling\n", in i9xx_check_plane_surface()
281 plane->base.base.id, plane->base.name); in i9xx_check_plane_surface()
282 return -EINVAL; in i9xx_check_plane_surface()
286 offset, offset - alignment); in i9xx_check_plane_surface()
294 drm_rect_translate_to(&plane_state->uapi.src, in i9xx_check_plane_surface()
298 if (!display->platform.haswell && !display->platform.broadwell) { in i9xx_check_plane_surface()
299 unsigned int rotation = plane_state->hw.rotation; in i9xx_check_plane_surface()
300 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; in i9xx_check_plane_surface()
301 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; in i9xx_check_plane_surface()
304 src_x += src_w - 1; in i9xx_check_plane_surface()
305 src_y += src_h - 1; in i9xx_check_plane_surface()
307 src_x += src_w - 1; in i9xx_check_plane_surface()
311 if (display->platform.haswell || display->platform.broadwell) { in i9xx_check_plane_surface()
312 drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095); in i9xx_check_plane_surface()
313 } else if (DISPLAY_VER(display) >= 4 && in i9xx_check_plane_surface()
314 fb->modifier == I915_FORMAT_MOD_X_TILED) { in i9xx_check_plane_surface()
315 drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095); in i9xx_check_plane_surface()
318 plane_state->view.color_plane[0].offset = offset; in i9xx_check_plane_surface()
319 plane_state->view.color_plane[0].x = src_x; in i9xx_check_plane_surface()
320 plane_state->view.color_plane[0].y = src_y; in i9xx_check_plane_surface()
329 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in i9xx_plane_check()
347 if (!plane_state->uapi.visible) in i9xx_plane_check()
354 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); in i9xx_plane_check()
361 struct intel_display *display = to_intel_display(crtc_state); in i9xx_plane_ctl_crtc() local
362 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_plane_ctl_crtc()
365 if (crtc_state->gamma_enable) in i9xx_plane_ctl_crtc()
368 if (crtc_state->csc_enable) in i9xx_plane_ctl_crtc()
371 if (DISPLAY_VER(display) < 5) in i9xx_plane_ctl_crtc()
372 dspcntr |= DISP_PIPE_SEL(crtc->pipe); in i9xx_plane_ctl_crtc()
381 const struct drm_framebuffer *fb = plane_state->hw.fb; in i9xx_plane_ratio()
382 unsigned int cpp = fb->format->cpp[0]; in i9xx_plane_ratio()
387 * same pipe. ilk/snb bspec says 64bpp pixel rate is in i9xx_plane_ratio()
407 * Note that crtc_state->pixel_rate accounts for both in i9xx_plane_min_cdclk()
409 * Pre-HSW bspec tells us to only consider the horizontal in i9xx_plane_min_cdclk()
413 pixel_rate = crtc_state->pixel_rate; in i9xx_plane_min_cdclk()
417 /* two pixels per clock with double wide pipe */ in i9xx_plane_min_cdclk()
418 if (crtc_state->double_wide) in i9xx_plane_min_cdclk()
429 struct intel_display *display = to_intel_display(plane); in i9xx_plane_update_noarm() local
430 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_update_noarm()
432 intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane), in i9xx_plane_update_noarm()
433 plane_state->view.color_plane[0].mapping_stride); in i9xx_plane_update_noarm()
435 if (DISPLAY_VER(display) < 4) { in i9xx_plane_update_noarm()
436 int crtc_x = plane_state->uapi.dst.x1; in i9xx_plane_update_noarm()
437 int crtc_y = plane_state->uapi.dst.y1; in i9xx_plane_update_noarm()
438 int crtc_w = drm_rect_width(&plane_state->uapi.dst); in i9xx_plane_update_noarm()
439 int crtc_h = drm_rect_height(&plane_state->uapi.dst); in i9xx_plane_update_noarm()
446 intel_de_write_fw(display, DSPPOS(display, i9xx_plane), in i9xx_plane_update_noarm()
448 intel_de_write_fw(display, DSPSIZE(display, i9xx_plane), in i9xx_plane_update_noarm()
449 DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); in i9xx_plane_update_noarm()
458 struct intel_display *display = to_intel_display(plane); in i9xx_plane_update_arm() local
459 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_update_arm()
460 int x = plane_state->view.color_plane[0].x; in i9xx_plane_update_arm()
461 int y = plane_state->view.color_plane[0].y; in i9xx_plane_update_arm()
464 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); in i9xx_plane_update_arm()
467 if (plane->need_async_flip_toggle_wa && in i9xx_plane_update_arm()
468 crtc_state->async_flip_planes & BIT(plane->id)) in i9xx_plane_update_arm()
473 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
474 dspaddr_offset = plane_state->view.color_plane[0].offset; in i9xx_plane_update_arm()
478 if (display->platform.cherryview && i9xx_plane == PLANE_B) { in i9xx_plane_update_arm()
479 int crtc_x = plane_state->uapi.dst.x1; in i9xx_plane_update_arm()
480 int crtc_y = plane_state->uapi.dst.y1; in i9xx_plane_update_arm()
481 int crtc_w = drm_rect_width(&plane_state->uapi.dst); in i9xx_plane_update_arm()
482 int crtc_h = drm_rect_height(&plane_state->uapi.dst); in i9xx_plane_update_arm()
484 intel_de_write_fw(display, PRIMPOS(display, i9xx_plane), in i9xx_plane_update_arm()
486 intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane), in i9xx_plane_update_arm()
487 PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); in i9xx_plane_update_arm()
488 intel_de_write_fw(display, in i9xx_plane_update_arm()
489 PRIMCNSTALPHA(display, i9xx_plane), 0); in i9xx_plane_update_arm()
492 if (display->platform.haswell || display->platform.broadwell) { in i9xx_plane_update_arm()
493 intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane), in i9xx_plane_update_arm()
495 } else if (DISPLAY_VER(display) >= 4) { in i9xx_plane_update_arm()
496 intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane), in i9xx_plane_update_arm()
498 intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane), in i9xx_plane_update_arm()
503 * The control register self-arms if the plane was previously in i9xx_plane_update_arm()
507 intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); in i9xx_plane_update_arm()
509 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
510 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in i9xx_plane_update_arm()
513 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), in i9xx_plane_update_arm()
523 * On i830/i845 all registers are self-arming [ALM040]. in i830_plane_update_arm()
536 struct intel_display *display = to_intel_display(plane); in i9xx_plane_disable_arm() local
537 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_disable_arm()
541 * DSPCNTR pipe gamma enable on g4x+ and pipe csc in i9xx_plane_disable_arm()
542 * enable on ilk+ affect the pipe bottom color as in i9xx_plane_disable_arm()
546 * On pre-g4x there is no way to gamma correct the in i9xx_plane_disable_arm()
547 * pipe bottom color but we'll keep on doing this in i9xx_plane_disable_arm()
552 intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
554 if (DISPLAY_VER(display) >= 4) in i9xx_plane_disable_arm()
555 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0); in i9xx_plane_disable_arm()
557 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0); in i9xx_plane_disable_arm()
564 struct intel_display *display = to_intel_display(plane); in g4x_primary_capture_error() local
565 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in g4x_primary_capture_error()
567 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in g4x_primary_capture_error()
568 error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); in g4x_primary_capture_error()
569 error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane)); in g4x_primary_capture_error()
576 struct intel_display *display = to_intel_display(plane); in i965_plane_capture_error() local
577 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i965_plane_capture_error()
579 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i965_plane_capture_error()
580 error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); in i965_plane_capture_error()
587 struct intel_display *display = to_intel_display(plane); in i8xx_plane_capture_error() local
588 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i8xx_plane_capture_error()
590 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i8xx_plane_capture_error()
591 error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane)); in i8xx_plane_capture_error()
601 struct intel_display *display = to_intel_display(plane); in g4x_primary_async_flip() local
602 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); in g4x_primary_async_flip()
603 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; in g4x_primary_async_flip()
604 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in g4x_primary_async_flip()
609 intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); in g4x_primary_async_flip()
611 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in g4x_primary_async_flip()
622 struct intel_display *display = to_intel_display(plane); in vlv_primary_async_flip() local
623 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; in vlv_primary_async_flip()
624 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in vlv_primary_async_flip()
626 intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), in vlv_primary_async_flip()
633 struct drm_i915_private *i915 = to_i915(plane->base.dev); in bdw_primary_enable_flip_done()
634 enum pipe pipe = plane->pipe; in bdw_primary_enable_flip_done() local
636 spin_lock_irq(&i915->irq_lock); in bdw_primary_enable_flip_done()
637 bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); in bdw_primary_enable_flip_done()
638 spin_unlock_irq(&i915->irq_lock); in bdw_primary_enable_flip_done()
644 struct drm_i915_private *i915 = to_i915(plane->base.dev); in bdw_primary_disable_flip_done()
645 enum pipe pipe = plane->pipe; in bdw_primary_disable_flip_done() local
647 spin_lock_irq(&i915->irq_lock); in bdw_primary_disable_flip_done()
648 bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); in bdw_primary_disable_flip_done()
649 spin_unlock_irq(&i915->irq_lock); in bdw_primary_disable_flip_done()
655 struct drm_i915_private *i915 = to_i915(plane->base.dev); in ivb_primary_enable_flip_done()
657 spin_lock_irq(&i915->irq_lock); in ivb_primary_enable_flip_done()
658 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); in ivb_primary_enable_flip_done()
659 spin_unlock_irq(&i915->irq_lock); in ivb_primary_enable_flip_done()
665 struct drm_i915_private *i915 = to_i915(plane->base.dev); in ivb_primary_disable_flip_done()
667 spin_lock_irq(&i915->irq_lock); in ivb_primary_disable_flip_done()
668 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); in ivb_primary_disable_flip_done()
669 spin_unlock_irq(&i915->irq_lock); in ivb_primary_disable_flip_done()
675 struct drm_i915_private *i915 = to_i915(plane->base.dev); in ilk_primary_enable_flip_done()
677 spin_lock_irq(&i915->irq_lock); in ilk_primary_enable_flip_done()
678 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); in ilk_primary_enable_flip_done()
679 spin_unlock_irq(&i915->irq_lock); in ilk_primary_enable_flip_done()
685 struct drm_i915_private *i915 = to_i915(plane->base.dev); in ilk_primary_disable_flip_done()
687 spin_lock_irq(&i915->irq_lock); in ilk_primary_disable_flip_done()
688 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); in ilk_primary_disable_flip_done()
689 spin_unlock_irq(&i915->irq_lock); in ilk_primary_disable_flip_done()
695 struct drm_i915_private *i915 = to_i915(plane->base.dev); in vlv_primary_enable_flip_done()
696 enum pipe pipe = plane->pipe; in vlv_primary_enable_flip_done() local
698 spin_lock_irq(&i915->irq_lock); in vlv_primary_enable_flip_done()
699 i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); in vlv_primary_enable_flip_done()
700 spin_unlock_irq(&i915->irq_lock); in vlv_primary_enable_flip_done()
706 struct drm_i915_private *i915 = to_i915(plane->base.dev); in vlv_primary_disable_flip_done()
707 enum pipe pipe = plane->pipe; in vlv_primary_disable_flip_done() local
709 spin_lock_irq(&i915->irq_lock); in vlv_primary_disable_flip_done()
710 i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); in vlv_primary_disable_flip_done()
711 spin_unlock_irq(&i915->irq_lock); in vlv_primary_disable_flip_done()
720 enum pipe *pipe) in i9xx_plane_get_hw_state() argument
722 struct intel_display *display = to_intel_display(plane); in i9xx_plane_get_hw_state() local
724 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_plane_get_hw_state()
731 * but that's only the case for gen2-4 which don't have any in i9xx_plane_get_hw_state()
732 * display power wells. in i9xx_plane_get_hw_state()
734 power_domain = POWER_DOMAIN_PIPE(plane->pipe); in i9xx_plane_get_hw_state()
735 wakeref = intel_display_power_get_if_enabled(display, power_domain); in i9xx_plane_get_hw_state()
739 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_plane_get_hw_state()
743 if (DISPLAY_VER(display) >= 5) in i9xx_plane_get_hw_state()
744 *pipe = plane->pipe; in i9xx_plane_get_hw_state()
746 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); in i9xx_plane_get_hw_state()
748 intel_display_power_put(display, power_domain, wakeref); in i9xx_plane_get_hw_state()
759 int cpp = info->cpp[0]; in hsw_primary_max_stride()
771 int cpp = info->cpp[0]; in ilk_primary_max_stride()
786 int cpp = info->cpp[0]; in i965_plane_max_stride()
811 if (plane->i9xx_plane == PLANE_C) in i8xx_plane_max_stride()
821 struct intel_display *display = to_intel_display(plane); in vlv_plane_min_alignment() local
823 if (intel_plane_can_async_flip(plane, fb->modifier)) in vlv_plane_min_alignment()
827 if (intel_scanout_needs_vtd_wa(display)) in vlv_plane_min_alignment()
830 switch (fb->modifier) { in vlv_plane_min_alignment()
836 MISSING_CASE(fb->modifier); in vlv_plane_min_alignment()
845 struct intel_display *display = to_intel_display(plane); in g4x_primary_min_alignment() local
847 if (intel_plane_can_async_flip(plane, fb->modifier)) in g4x_primary_min_alignment()
850 if (intel_scanout_needs_vtd_wa(display)) in g4x_primary_min_alignment()
853 switch (fb->modifier) { in g4x_primary_min_alignment()
858 MISSING_CASE(fb->modifier); in g4x_primary_min_alignment()
867 switch (fb->modifier) { in i965_plane_min_alignment()
873 MISSING_CASE(fb->modifier); in i965_plane_min_alignment()
904 intel_primary_plane_create(struct intel_display *display, enum pipe pipe) in intel_primary_plane_create() argument
918 plane->pipe = pipe; in intel_primary_plane_create()
921 * port is hooked to pipe B. Hence we want plane A feeding pipe B. in intel_primary_plane_create()
923 if (HAS_FBC(display) && DISPLAY_VER(display) < 4 && in intel_primary_plane_create()
924 INTEL_NUM_PIPES(display) == 2) in intel_primary_plane_create()
925 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; in intel_primary_plane_create()
927 plane->i9xx_plane = (enum i9xx_plane_id) pipe; in intel_primary_plane_create()
928 plane->id = PLANE_PRIMARY; in intel_primary_plane_create()
929 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); in intel_primary_plane_create()
931 intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane); in intel_primary_plane_create()
933 if (display->platform.valleyview || display->platform.cherryview) { in intel_primary_plane_create()
936 } else if (DISPLAY_VER(display) >= 4) { in intel_primary_plane_create()
939 * "Workaround : When using the 64-bit format, the plane in intel_primary_plane_create()
941 * It can be brought up to full amplitude by using pipe in intel_primary_plane_create()
942 * gamma correction or pipe color space conversion to in intel_primary_plane_create()
946 * and using the pipe gamma/csc could conflict with other in intel_primary_plane_create()
950 if (display->platform.ivybridge) { in intel_primary_plane_create()
962 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
967 if (display->platform.valleyview || display->platform.cherryview) in intel_primary_plane_create()
968 plane->min_cdclk = vlv_plane_min_cdclk; in intel_primary_plane_create()
969 else if (display->platform.broadwell || display->platform.haswell) in intel_primary_plane_create()
970 plane->min_cdclk = hsw_plane_min_cdclk; in intel_primary_plane_create()
971 else if (display->platform.ivybridge) in intel_primary_plane_create()
972 plane->min_cdclk = ivb_plane_min_cdclk; in intel_primary_plane_create()
974 plane->min_cdclk = i9xx_plane_min_cdclk; in intel_primary_plane_create()
976 if (HAS_GMCH(display)) { in intel_primary_plane_create()
977 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
978 plane->max_stride = i965_plane_max_stride; in intel_primary_plane_create()
979 else if (DISPLAY_VER(display) == 3) in intel_primary_plane_create()
980 plane->max_stride = i915_plane_max_stride; in intel_primary_plane_create()
982 plane->max_stride = i8xx_plane_max_stride; in intel_primary_plane_create()
984 if (display->platform.broadwell || display->platform.haswell) in intel_primary_plane_create()
985 plane->max_stride = hsw_primary_max_stride; in intel_primary_plane_create()
987 plane->max_stride = ilk_primary_max_stride; in intel_primary_plane_create()
990 if (display->platform.valleyview || display->platform.cherryview) in intel_primary_plane_create()
991 plane->min_alignment = vlv_plane_min_alignment; in intel_primary_plane_create()
992 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
993 plane->min_alignment = g4x_primary_min_alignment; in intel_primary_plane_create()
994 else if (DISPLAY_VER(display) == 4) in intel_primary_plane_create()
995 plane->min_alignment = i965_plane_min_alignment; in intel_primary_plane_create()
997 plane->min_alignment = i9xx_plane_min_alignment; in intel_primary_plane_create()
1000 if (intel_scanout_needs_vtd_wa(display)) in intel_primary_plane_create()
1001 plane->vtd_guard = 128; in intel_primary_plane_create()
1003 if (display->platform.i830 || display->platform.i845g) { in intel_primary_plane_create()
1004 plane->update_arm = i830_plane_update_arm; in intel_primary_plane_create()
1006 plane->update_noarm = i9xx_plane_update_noarm; in intel_primary_plane_create()
1007 plane->update_arm = i9xx_plane_update_arm; in intel_primary_plane_create()
1009 plane->disable_arm = i9xx_plane_disable_arm; in intel_primary_plane_create()
1010 plane->get_hw_state = i9xx_plane_get_hw_state; in intel_primary_plane_create()
1011 plane->check_plane = i9xx_plane_check; in intel_primary_plane_create()
1013 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
1014 plane->capture_error = g4x_primary_capture_error; in intel_primary_plane_create()
1015 else if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
1016 plane->capture_error = i965_plane_capture_error; in intel_primary_plane_create()
1018 plane->capture_error = i8xx_plane_capture_error; in intel_primary_plane_create()
1020 if (HAS_ASYNC_FLIPS(display)) { in intel_primary_plane_create()
1021 if (display->platform.valleyview || display->platform.cherryview) { in intel_primary_plane_create()
1022 plane->async_flip = vlv_primary_async_flip; in intel_primary_plane_create()
1023 plane->enable_flip_done = vlv_primary_enable_flip_done; in intel_primary_plane_create()
1024 plane->disable_flip_done = vlv_primary_disable_flip_done; in intel_primary_plane_create()
1025 plane->can_async_flip = i9xx_plane_can_async_flip; in intel_primary_plane_create()
1026 } else if (display->platform.broadwell) { in intel_primary_plane_create()
1027 plane->need_async_flip_toggle_wa = true; in intel_primary_plane_create()
1028 plane->async_flip = g4x_primary_async_flip; in intel_primary_plane_create()
1029 plane->enable_flip_done = bdw_primary_enable_flip_done; in intel_primary_plane_create()
1030 plane->disable_flip_done = bdw_primary_disable_flip_done; in intel_primary_plane_create()
1031 plane->can_async_flip = i9xx_plane_can_async_flip; in intel_primary_plane_create()
1032 } else if (DISPLAY_VER(display) >= 7) { in intel_primary_plane_create()
1033 plane->async_flip = g4x_primary_async_flip; in intel_primary_plane_create()
1034 plane->enable_flip_done = ivb_primary_enable_flip_done; in intel_primary_plane_create()
1035 plane->disable_flip_done = ivb_primary_disable_flip_done; in intel_primary_plane_create()
1036 plane->can_async_flip = i9xx_plane_can_async_flip; in intel_primary_plane_create()
1037 } else if (DISPLAY_VER(display) >= 5) { in intel_primary_plane_create()
1038 plane->async_flip = g4x_primary_async_flip; in intel_primary_plane_create()
1039 plane->enable_flip_done = ilk_primary_enable_flip_done; in intel_primary_plane_create()
1040 plane->disable_flip_done = ilk_primary_disable_flip_done; in intel_primary_plane_create()
1041 plane->can_async_flip = i9xx_plane_can_async_flip; in intel_primary_plane_create()
1045 modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); in intel_primary_plane_create()
1047 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
1048 ret = drm_universal_plane_init(display->drm, &plane->base, in intel_primary_plane_create()
1053 "primary %c", pipe_name(pipe)); in intel_primary_plane_create()
1055 ret = drm_universal_plane_init(display->drm, &plane->base, in intel_primary_plane_create()
1061 plane_name(plane->i9xx_plane)); in intel_primary_plane_create()
1068 if (display->platform.cherryview && pipe == PIPE_B) { in intel_primary_plane_create()
1072 } else if (DISPLAY_VER(display) >= 4) { in intel_primary_plane_create()
1079 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
1080 drm_plane_create_rotation_property(&plane->base, in intel_primary_plane_create()
1085 drm_plane_create_zpos_immutable_property(&plane->base, zpos); in intel_primary_plane_create()
1134 struct intel_display *display = to_intel_display(crtc); in i9xx_get_initial_plane_config() local
1135 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in i9xx_get_initial_plane_config()
1136 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_get_initial_plane_config()
1137 enum pipe pipe; in i9xx_get_initial_plane_config() local
1144 if (!plane->get_hw_state(plane, &pipe)) in i9xx_get_initial_plane_config()
1147 drm_WARN_ON(display->drm, pipe != crtc->pipe); in i9xx_get_initial_plane_config()
1151 drm_dbg_kms(display->drm, "failed to alloc fb\n"); in i9xx_get_initial_plane_config()
1155 fb = &intel_fb->base; in i9xx_get_initial_plane_config()
1157 fb->dev = display->drm; in i9xx_get_initial_plane_config()
1159 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1161 if (DISPLAY_VER(display) >= 4) { in i9xx_get_initial_plane_config()
1163 plane_config->tiling = I915_TILING_X; in i9xx_get_initial_plane_config()
1164 fb->modifier = I915_FORMAT_MOD_X_TILED; in i9xx_get_initial_plane_config()
1168 plane_config->rotation = DRM_MODE_ROTATE_180; in i9xx_get_initial_plane_config()
1171 if (display->platform.cherryview && in i9xx_get_initial_plane_config()
1172 pipe == PIPE_B && val & DISP_MIRROR) in i9xx_get_initial_plane_config()
1173 plane_config->rotation |= DRM_MODE_REFLECT_X; in i9xx_get_initial_plane_config()
1177 fb->format = drm_format_info(fourcc); in i9xx_get_initial_plane_config()
1179 if (display->platform.haswell || display->platform.broadwell) { in i9xx_get_initial_plane_config()
1180 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1181 DSPOFFSET(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1182 base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1183 } else if (DISPLAY_VER(display) >= 4) { in i9xx_get_initial_plane_config()
1184 if (plane_config->tiling) in i9xx_get_initial_plane_config()
1185 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1186 DSPTILEOFF(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1188 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1189 DSPLINOFF(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1190 base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; in i9xx_get_initial_plane_config()
1193 base = intel_de_read(display, DSPADDR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1195 plane_config->base = base; in i9xx_get_initial_plane_config()
1197 drm_WARN_ON(display->drm, offset != 0); in i9xx_get_initial_plane_config()
1199 val = intel_de_read(display, PIPESRC(display, pipe)); in i9xx_get_initial_plane_config()
1200 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; in i9xx_get_initial_plane_config()
1201 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; in i9xx_get_initial_plane_config()
1203 val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1204 fb->pitches[0] = val & 0xffffffc0; in i9xx_get_initial_plane_config()
1206 aligned_height = intel_fb_align_height(fb, 0, fb->height); in i9xx_get_initial_plane_config()
1208 plane_config->size = fb->pitches[0] * aligned_height; in i9xx_get_initial_plane_config()
1210 drm_dbg_kms(display->drm, in i9xx_get_initial_plane_config()
1212 crtc->base.base.id, crtc->base.name, in i9xx_get_initial_plane_config()
1213 plane->base.base.id, plane->base.name, in i9xx_get_initial_plane_config()
1214 fb->width, fb->height, fb->format->cpp[0] * 8, in i9xx_get_initial_plane_config()
1215 base, fb->pitches[0], plane_config->size); in i9xx_get_initial_plane_config()
1217 plane_config->fb = intel_fb; in i9xx_get_initial_plane_config()
1223 struct intel_display *display = to_intel_display(crtc); in i9xx_fixup_initial_plane_config() local
1224 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in i9xx_fixup_initial_plane_config()
1226 to_intel_plane_state(plane->base.state); in i9xx_fixup_initial_plane_config()
1227 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; in i9xx_fixup_initial_plane_config()
1230 if (!plane_state->uapi.visible) in i9xx_fixup_initial_plane_config()
1239 if (plane_config->base == base) in i9xx_fixup_initial_plane_config()
1242 if (DISPLAY_VER(display) >= 4) in i9xx_fixup_initial_plane_config()
1243 intel_de_write(display, DSPSURF(display, i9xx_plane), base); in i9xx_fixup_initial_plane_config()
1245 intel_de_write(display, DSPADDR(display, i9xx_plane), base); in i9xx_fixup_initial_plane_config()