Lines Matching +full:display +full:- +full:pipe
1 // SPDX-License-Identifier: MIT
62 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
63 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
65 * It allows driver to batch submit display HW programming. This helps to
69 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
109 return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc); in pre_commit_is_vrr_active()
127 return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode); in dsb_vblank_delay()
139 return intel_mode_vtotal(&crtc_state->hw.adjusted_mode); in dsb_vtotal()
147 struct drm_i915_private *i915 = to_i915(state->base.dev); in dsb_dewake_scanline_start()
150 return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) - in dsb_dewake_scanline_start()
151 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency); in dsb_dewake_scanline_start()
160 return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode); in dsb_dewake_scanline_end()
170 return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; in dsb_scanline_to_hw()
177 * happens and this interrupt is considered as indication of completion -> we
197 struct intel_crtc *crtc = dsb->crtc; in assert_dsb_has_room()
198 struct intel_display *display = to_intel_display(crtc->base.dev); in assert_dsb_has_room() local
201 return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2, in assert_dsb_has_room()
203 crtc->base.base.id, crtc->base.name, dsb->id); in assert_dsb_has_room()
208 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_dump()
209 struct intel_display *display = to_intel_display(crtc->base.dev); in intel_dsb_dump() local
212 drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n", in intel_dsb_dump()
213 crtc->base.base.id, crtc->base.name, dsb->id); in intel_dsb_dump()
214 for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) in intel_dsb_dump()
215 drm_dbg_kms(display->drm, in intel_dsb_dump()
217 intel_dsb_buffer_read(&dsb->dsb_buf, i), in intel_dsb_dump()
218 intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), in intel_dsb_dump()
219 intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), in intel_dsb_dump()
220 intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); in intel_dsb_dump()
221 drm_dbg_kms(display->drm, "}\n"); in intel_dsb_dump()
224 static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, in is_dsb_busy() argument
227 return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; in is_dsb_busy()
236 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_emit()
238 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_emit()
239 dsb->ins[0] = ldw; in intel_dsb_emit()
240 dsb->ins[1] = udw; in intel_dsb_emit()
242 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]); in intel_dsb_emit()
243 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]); in intel_dsb_emit()
256 if (dsb->free_pos == 0) in intel_dsb_prev_ins_is_write()
259 prev_opcode = dsb->ins[1] & ~DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
260 prev_reg = dsb->ins[1] & DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
273 * intel_dsb_reg_write_indexed() - Emit indexed register write to the DSB context
278 * This function is used for writing register-value pair in command
291 * +--------------------------------------------------------+ in intel_dsb_reg_write_indexed()
294 * +--------------------------------------------------------+ in intel_dsb_reg_write_indexed()
313 dsb->ins[0]++; in intel_dsb_reg_write_indexed()
314 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, in intel_dsb_reg_write_indexed()
315 dsb->ins[0]); in intel_dsb_reg_write_indexed()
317 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); in intel_dsb_reg_write_indexed()
319 if (dsb->free_pos & 0x1) in intel_dsb_reg_write_indexed()
320 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); in intel_dsb_reg_write_indexed()
361 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_start()
362 enum pipe pipe = crtc->pipe; in intel_dsb_nonpost_start() local
364 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_start()
371 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_end()
372 enum pipe pipe = crtc->pipe; in intel_dsb_nonpost_end() local
374 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_end()
414 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait_dsl()
429 drm_WARN_ON(crtc->base.dev, 1); /* assert_dsl_ok() should have caught it already */ in intel_dsb_wait_dsl()
436 struct intel_crtc *crtc = dsb->crtc; in assert_dsl_ok()
443 drm_WARN(crtc->base.dev, (end - start + vtotal) % vtotal == vtotal - 1, in assert_dsl_ok()
444 "[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d (vt=%d)\n", in assert_dsl_ok()
445 crtc->base.base.id, crtc->base.name, dsb->id, in assert_dsl_ok()
457 end + 1, start - 1); in intel_dsb_wait_scanline_in()
467 end + 1, start - 1, in intel_dsb_wait_scanline_out()
475 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_poll()
476 enum pipe pipe = crtc->pipe; in intel_dsb_poll() local
478 intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask); in intel_dsb_poll()
479 intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id), in intel_dsb_poll()
494 tail = dsb->free_pos * 4; in intel_dsb_align_tail()
498 intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, in intel_dsb_align_tail()
499 aligned_tail - tail); in intel_dsb_align_tail()
501 dsb->free_pos = aligned_tail / 4; in intel_dsb_align_tail()
506 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_finish()
514 intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0); in intel_dsb_finish()
515 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), in intel_dsb_finish()
520 intel_dsb_buffer_flush_map(&dsb->dsb_buf); in intel_dsb_finish()
523 static u32 dsb_error_int_status(struct intel_display *display) in dsb_error_int_status() argument
532 * All the non-existing status bits operate as in dsb_error_int_status()
537 if (DISPLAY_VER(display) >= 14) in dsb_error_int_status()
543 static u32 dsb_error_int_en(struct intel_display *display) in dsb_error_int_en() argument
551 if (DISPLAY_VER(display) >= 14) in dsb_error_int_en()
560 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_vblank_evade()
564 int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20); in intel_dsb_vblank_evade()
569 * wake-up scanline counting starts from vblank_start - 1. We don't know in intel_dsb_vblank_evade()
570 * if wake-up is already ongoing when evasion starts. In worst case in intel_dsb_vblank_evade()
576 if (crtc_state->has_psr) in intel_dsb_vblank_evade()
583 start = end - vblank_delay - latency; in intel_dsb_vblank_evade()
587 start = end - vblank_delay - latency; in intel_dsb_vblank_evade()
590 int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode); in intel_dsb_vblank_evade()
592 end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode); in intel_dsb_vblank_evade()
593 start = end - vblank_delay - latency; in intel_dsb_vblank_evade()
603 struct intel_display *display = to_intel_display(state->base.dev); in _intel_dsb_chain() local
604 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_chain()
605 enum pipe pipe = crtc->pipe; in _intel_dsb_chain() local
608 if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) in _intel_dsb_chain()
611 tail = chained_dsb->free_pos * 4; in _intel_dsb_chain()
612 if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) in _intel_dsb_chain()
615 intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), in _intel_dsb_chain()
618 intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id), in _intel_dsb_chain()
621 intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id), in _intel_dsb_chain()
622 dsb_error_int_status(display) | DSB_PROG_INT_STATUS | in _intel_dsb_chain()
623 dsb_error_int_en(display) | DSB_PROG_INT_EN); in _intel_dsb_chain()
629 intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), in _intel_dsb_chain()
634 intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), in _intel_dsb_chain()
635 intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); in _intel_dsb_chain()
637 intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), in _intel_dsb_chain()
638 intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); in _intel_dsb_chain()
647 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_chain()
668 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait_vblank_delay()
671 int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode, in intel_dsb_wait_vblank_delay()
680 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_commit()
681 struct intel_display *display = to_intel_display(crtc->base.dev); in _intel_dsb_commit() local
682 enum pipe pipe = crtc->pipe; in _intel_dsb_commit() local
685 tail = dsb->free_pos * 4; in _intel_dsb_commit()
686 if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) in _intel_dsb_commit()
689 if (is_dsb_busy(display, pipe, dsb->id)) { in _intel_dsb_commit()
690 drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", in _intel_dsb_commit()
691 crtc->base.base.id, crtc->base.name, dsb->id); in _intel_dsb_commit()
695 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), in _intel_dsb_commit()
698 intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), in _intel_dsb_commit()
699 dsb->chicken); in _intel_dsb_commit()
701 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), in _intel_dsb_commit()
702 dsb_error_int_status(display) | DSB_PROG_INT_STATUS | in _intel_dsb_commit()
703 dsb_error_int_en(display) | DSB_PROG_INT_EN); in _intel_dsb_commit()
705 intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), in _intel_dsb_commit()
706 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); in _intel_dsb_commit()
711 intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), in _intel_dsb_commit()
719 position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; in _intel_dsb_commit()
721 diff = hw_dewake_scanline - position; in _intel_dsb_commit()
722 intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_commit()
727 intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), in _intel_dsb_commit()
728 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); in _intel_dsb_commit()
732 * intel_dsb_commit() - Trigger workload execution of DSB.
743 wait_for_vblank ? dsb->hw_dewake_scanline : -1); in intel_dsb_commit()
748 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait()
749 struct intel_display *display = to_intel_display(crtc->base.dev); in intel_dsb_wait() local
750 enum pipe pipe = crtc->pipe; in intel_dsb_wait() local
752 if (wait_for(!is_dsb_busy(display, pipe, dsb->id), 1)) { in intel_dsb_wait()
753 u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); in intel_dsb_wait()
755 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), in intel_dsb_wait()
758 drm_err(display->drm, in intel_dsb_wait()
760 crtc->base.base.id, crtc->base.name, dsb->id, in intel_dsb_wait()
761 intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
762 intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
763 intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset); in intel_dsb_wait()
769 dsb->free_pos = 0; in intel_dsb_wait()
770 dsb->ins_start_offset = 0; in intel_dsb_wait()
771 dsb->ins[0] = 0; in intel_dsb_wait()
772 dsb->ins[1] = 0; in intel_dsb_wait()
774 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); in intel_dsb_wait()
776 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), in intel_dsb_wait()
777 dsb_error_int_status(display) | DSB_PROG_INT_STATUS); in intel_dsb_wait()
781 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
798 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dsb_prepare()
806 if (!i915->display.params.enable_dsb) in intel_dsb_prepare()
813 wakeref = intel_runtime_pm_get(&i915->runtime_pm); in intel_dsb_prepare()
818 if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size)) in intel_dsb_prepare()
821 intel_runtime_pm_put(&i915->runtime_pm, wakeref); in intel_dsb_prepare()
823 dsb->id = dsb_id; in intel_dsb_prepare()
824 dsb->crtc = crtc; in intel_dsb_prepare()
825 dsb->size = size / 4; /* in dwords */ in intel_dsb_prepare()
827 dsb->chicken = dsb_chicken(state, crtc); in intel_dsb_prepare()
828 dsb->hw_dewake_scanline = in intel_dsb_prepare()
834 intel_runtime_pm_put(&i915->runtime_pm, wakeref); in intel_dsb_prepare()
837 drm_info_once(&i915->drm, in intel_dsb_prepare()
838 … "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", in intel_dsb_prepare()
839 crtc->base.base.id, crtc->base.name, dsb_id); in intel_dsb_prepare()
845 * intel_dsb_cleanup() - To cleanup DSB context.
853 intel_dsb_buffer_cleanup(&dsb->dsb_buf); in intel_dsb_cleanup()
857 void intel_dsb_irq_handler(struct intel_display *display, in intel_dsb_irq_handler() argument
858 enum pipe pipe, enum intel_dsb_id dsb_id) in intel_dsb_irq_handler() argument
860 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_dsb_irq_handler()
863 tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id)); in intel_dsb_irq_handler()
864 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp); in intel_dsb_irq_handler()
867 spin_lock(&display->drm->event_lock); in intel_dsb_irq_handler()
869 if (crtc->dsb_event) { in intel_dsb_irq_handler()
874 drm_crtc_accurate_vblank_count(&crtc->base); in intel_dsb_irq_handler()
876 drm_crtc_send_vblank_event(&crtc->base, crtc->dsb_event); in intel_dsb_irq_handler()
877 crtc->dsb_event = NULL; in intel_dsb_irq_handler()
880 spin_unlock(&display->drm->event_lock); in intel_dsb_irq_handler()
883 errors = tmp & dsb_error_int_status(display); in intel_dsb_irq_handler()
885 drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n", in intel_dsb_irq_handler()
886 crtc->base.base.id, crtc->base.name, dsb_id); in intel_dsb_irq_handler()
888 drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n", in intel_dsb_irq_handler()
889 crtc->base.base.id, crtc->base.name, dsb_id); in intel_dsb_irq_handler()
891 drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n", in intel_dsb_irq_handler()
892 crtc->base.base.id, crtc->base.name, dsb_id); in intel_dsb_irq_handler()
894 drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", in intel_dsb_irq_handler()
895 crtc->base.base.id, crtc->base.name, dsb_id); in intel_dsb_irq_handler()