Lines Matching +full:display +full:- +full:pipe
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
35 #include <drm/display/drm_dp.h>
41 #include "display/bxt_dpio_phy_regs.h"
42 #include "display/i9xx_plane_regs.h"
43 #include "display/intel_crt_regs.h"
44 #include "display/intel_cursor_regs.h"
45 #include "display/intel_display.h"
46 #include "display/intel_dpio_phy.h"
47 #include "display/intel_sprite_regs.h"
52 int pipe = -1; in get_edp_pipe() local
57 pipe = PIPE_A; in get_edp_pipe()
60 pipe = PIPE_B; in get_edp_pipe()
63 pipe = PIPE_C; in get_edp_pipe()
66 return pipe; in get_edp_pipe()
71 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in edp_pipe_is_enabled()
72 struct intel_display *display = &dev_priv->display; in edp_pipe_is_enabled() local
74 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) in edp_pipe_is_enabled()
82 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) in pipe_is_enabled() argument
84 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in pipe_is_enabled()
85 struct intel_display *display = &dev_priv->display; in pipe_is_enabled() local
87 if (drm_WARN_ON(&dev_priv->drm, in pipe_is_enabled()
88 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
89 return -EINVAL; in pipe_is_enabled()
91 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) in pipe_is_enabled()
95 get_edp_pipe(vgpu) == pipe) in pipe_is_enabled()
109 /* Basic Display Parameters & Features */
143 /* Basic Display Parameters & Features */
178 /* let the virtual display supports DP1.2 */
185 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_monitor_status_change()
186 struct intel_display *display = &dev_priv->display; in emulate_monitor_status_change() local
187 int pipe; in emulate_monitor_status_change() local
193 /* Clear PIPE, DDI, PHY, HPD before setting new */ in emulate_monitor_status_change()
199 for_each_pipe(display, pipe) { in emulate_monitor_status_change()
200 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= in emulate_monitor_status_change()
202 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
203 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
204 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
205 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
209 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= in emulate_monitor_status_change()
213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
256 * Only 1 PIPE enabled in current vGPU display and PIPE_A is in emulate_monitor_status_change()
261 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
262 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; in emulate_monitor_status_change()
267 * DP link clk 1620 MHz and non-constant_n. in emulate_monitor_status_change()
270 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
271 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
272 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
274 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
276 /* Enable per-DDI/PORT vreg */ in emulate_monitor_status_change()
297 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |= in emulate_monitor_status_change()
327 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
358 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
387 * Only 1 PIPE enabled in current vGPU display and PIPE_A is in emulate_monitor_status_change()
404 * DP link clk 1620 MHz and non-constant_n. in emulate_monitor_status_change()
407 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
408 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
409 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
410 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
411 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
422 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
425 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
448 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
451 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
474 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
477 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
515 for_each_pipe(display, pipe) { in emulate_monitor_status_change()
516 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
517 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; in emulate_monitor_status_change()
518 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; in emulate_monitor_status_change()
519 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; in emulate_monitor_status_change()
522 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
529 kfree(port->edid); in clean_virtual_dp_monitor()
530 port->edid = NULL; in clean_virtual_dp_monitor()
532 kfree(port->dpcd); in clean_virtual_dp_monitor()
533 port->dpcd = NULL; in clean_virtual_dp_monitor()
544 /* Set vblank emulation request per-vGPU bit */ in vblank_timer_fn()
545 intel_gvt_request_service(vgpu->gvt, in vblank_timer_fn()
546 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); in vblank_timer_fn()
547 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); in vblank_timer_fn()
554 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in setup_virtual_dp_monitor()
556 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; in setup_virtual_dp_monitor()
558 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) in setup_virtual_dp_monitor()
559 return -EINVAL; in setup_virtual_dp_monitor()
561 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); in setup_virtual_dp_monitor()
562 if (!port->edid) in setup_virtual_dp_monitor()
563 return -ENOMEM; in setup_virtual_dp_monitor()
565 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); in setup_virtual_dp_monitor()
566 if (!port->dpcd) { in setup_virtual_dp_monitor()
567 kfree(port->edid); in setup_virtual_dp_monitor()
568 return -ENOMEM; in setup_virtual_dp_monitor()
571 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], in setup_virtual_dp_monitor()
573 port->edid->data_valid = true; in setup_virtual_dp_monitor()
575 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
576 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
577 port->dpcd->data[DP_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
578 port->type = type; in setup_virtual_dp_monitor()
579 port->id = resolution; in setup_virtual_dp_monitor()
580 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; in setup_virtual_dp_monitor()
581 vgpu->display.port_num = port_num; in setup_virtual_dp_monitor()
584 hrtimer_setup(&vblank_timer->timer, vblank_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); in setup_virtual_dp_monitor()
585 vblank_timer->vrefresh_k = port->vrefresh_k; in setup_virtual_dp_monitor()
586 …vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh… in setup_virtual_dp_monitor()
594 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
598 * This function is used to turn on/off or update the per-vGPU vblank_timer
605 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; in vgpu_update_vblank_emulation()
607 intel_vgpu_port(vgpu, vgpu->display.port_num); in vgpu_update_vblank_emulation()
611 * Skip the re-enable if already active and vrefresh unchanged. in vgpu_update_vblank_emulation()
615 if (vblank_timer->vrefresh_k != port->vrefresh_k || in vgpu_update_vblank_emulation()
616 !hrtimer_active(&vblank_timer->timer)) { in vgpu_update_vblank_emulation()
618 if (hrtimer_active(&vblank_timer->timer)) in vgpu_update_vblank_emulation()
619 hrtimer_cancel(&vblank_timer->timer); in vgpu_update_vblank_emulation()
622 vblank_timer->vrefresh_k = port->vrefresh_k; in vgpu_update_vblank_emulation()
623 …vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh… in vgpu_update_vblank_emulation()
624 hrtimer_start(&vblank_timer->timer, in vgpu_update_vblank_emulation()
625 ktime_add_ns(ktime_get(), vblank_timer->period), in vgpu_update_vblank_emulation()
630 hrtimer_cancel(&vblank_timer->timer); in vgpu_update_vblank_emulation()
634 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) in emulate_vblank_on_pipe() argument
636 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_vblank_on_pipe()
637 struct intel_display *display = &dev_priv->display; in emulate_vblank_on_pipe() local
638 struct intel_vgpu_irq *irq = &vgpu->irq; in emulate_vblank_on_pipe()
646 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
649 for_each_set_bit(event, irq->flip_done_event[pipe], in emulate_vblank_on_pipe()
651 clear_bit(event, irq->flip_done_event[pipe]); in emulate_vblank_on_pipe()
652 if (!pipe_is_enabled(vgpu, pipe)) in emulate_vblank_on_pipe()
658 if (pipe_is_enabled(vgpu, pipe)) { in emulate_vblank_on_pipe()
659 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++; in emulate_vblank_on_pipe()
660 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); in emulate_vblank_on_pipe()
666 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_vblank()
667 struct intel_display *display = &i915->display; in intel_vgpu_emulate_vblank() local
668 int pipe; in intel_vgpu_emulate_vblank() local
670 mutex_lock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
671 for_each_pipe(display, pipe) in intel_vgpu_emulate_vblank()
672 emulate_vblank_on_pipe(vgpu, pipe); in intel_vgpu_emulate_vblank()
673 mutex_unlock(&vgpu->vgpu_lock); in intel_vgpu_emulate_vblank()
677 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
686 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_hotplug()
767 * intel_vgpu_clean_display - clean vGPU virtual display emulation
770 * This function is used to clean vGPU virtual display emulation stuffs
775 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_clean_display()
789 * intel_vgpu_init_display- initialize vGPU virtual display emulation
793 * This function is used to initialize vGPU virtual display emulation stuffs
801 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_init_display()
817 * intel_vgpu_reset_display- reset vGPU virtual display emulation
820 * This function is used to reset vGPU virtual display emulation stuffs