1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8 #include <linux/limits.h>
9
10 #include <drm/display/drm_dsc_helper.h>
11 #include <drm/drm_fixed.h>
12
13 #include "i915_utils.h"
14 #include "intel_crtc.h"
15 #include "intel_de.h"
16 #include "intel_display_types.h"
17 #include "intel_dp.h"
18 #include "intel_dsi.h"
19 #include "intel_qp_tables.h"
20 #include "intel_vdsc.h"
21 #include "intel_vdsc_regs.h"
22
intel_dsc_source_support(const struct intel_crtc_state * crtc_state)23 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
24 {
25 struct intel_display *display = to_intel_display(crtc_state);
26 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
27
28 if (!HAS_DSC(display))
29 return false;
30
31 if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
32 return false;
33
34 return true;
35 }
36
is_pipe_dsc(struct intel_crtc * crtc,enum transcoder cpu_transcoder)37 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
38 {
39 struct intel_display *display = to_intel_display(crtc);
40
41 if (DISPLAY_VER(display) >= 12)
42 return true;
43
44 if (cpu_transcoder == TRANSCODER_EDP ||
45 cpu_transcoder == TRANSCODER_DSI_0 ||
46 cpu_transcoder == TRANSCODER_DSI_1)
47 return false;
48
49 /* There's no pipe A DSC engine on ICL */
50 drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
51
52 return true;
53 }
54
55 static void
intel_vdsc_set_min_max_qp(struct drm_dsc_config * vdsc_cfg,int buf,int bpp)56 intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
57 int bpp)
58 {
59 int bpc = vdsc_cfg->bits_per_component;
60
61 /* Read range_minqp and range_max_qp from qp tables */
62 vdsc_cfg->rc_range_params[buf].range_min_qp =
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420);
64 vdsc_cfg->rc_range_params[buf].range_max_qp =
65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
66 }
67
68 static int
get_range_bpg_offset(int bpp_low,int offset_low,int bpp_high,int offset_high,int bpp)69 get_range_bpg_offset(int bpp_low, int offset_low, int bpp_high, int offset_high, int bpp)
70 {
71 return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low),
72 (bpp_low - bpp_high));
73 }
74
75 /*
76 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
77 * Above method use a common formula to derive values for any combination of DSC
78 * variables. The formula approach may yield slight differences in the derived PPS
79 * parameters from the original parameter sets. These differences are not consequential
80 * to the coding performance because all parameter sets have been shown to produce
81 * visually lossless quality (provides the same PPS values as
82 * DSCParameterValuesVESA V1-2 spreadsheet).
83 */
84 static void
calculate_rc_params(struct drm_dsc_config * vdsc_cfg)85 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
86 {
87 int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel);
88 int bpc = vdsc_cfg->bits_per_component;
89 int qp_bpc_modifier = (bpc - 8) * 2;
90 int uncompressed_bpg_rate;
91 int first_line_bpg_offset;
92 u32 buf_i, bpp_i;
93
94 if (vdsc_cfg->slice_height >= 8)
95 first_line_bpg_offset =
96 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100;
97 else
98 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
99
100 uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3;
101 vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0,
102 uncompressed_bpg_rate - 3 * bpp);
103
104 /*
105 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:
106 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
107 * height < 8.
108 * -second_line_offset_adj is 512 as shown by empirical values to yield best chroma
109 * preservation in second line.
110 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
111 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
112 * fractional bits.
113 */
114 if (vdsc_cfg->native_420) {
115 if (vdsc_cfg->slice_height >= 8)
116 vdsc_cfg->second_line_bpg_offset = 12;
117 else
118 vdsc_cfg->second_line_bpg_offset =
119 2 * (vdsc_cfg->slice_height - 1);
120
121 vdsc_cfg->second_line_offset_adj = 512;
122 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
123 vdsc_cfg->slice_height - 1);
124 }
125
126 if (bpp >= 12)
127 vdsc_cfg->initial_offset = 2048;
128 else if (bpp >= 10)
129 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
130 else if (bpp >= 8)
131 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
132 else
133 vdsc_cfg->initial_offset = 6144;
134
135 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
136 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
137
138 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
139 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
140
141 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
142 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
143
144 if (vdsc_cfg->native_420) {
145 static const s8 ofs_und4[] = {
146 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
147 };
148 static const s8 ofs_und5[] = {
149 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
150 };
151 static const s8 ofs_und6[] = {
152 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
153 };
154 static const s8 ofs_und8[] = {
155 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
156 };
157 /*
158 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
159 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
160 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
161 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
162 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
163 */
164 bpp_i = bpp - 8;
165 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
166 u8 range_bpg_offset;
167
168 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
169
170 /* Calculate range_bpg_offset */
171 if (bpp <= 8)
172 range_bpg_offset = ofs_und4[buf_i];
173 else if (bpp <= 10)
174 range_bpg_offset = get_range_bpg_offset(8, ofs_und4[buf_i],
175 10, ofs_und5[buf_i], bpp);
176 else if (bpp <= 12)
177 range_bpg_offset = get_range_bpg_offset(10, ofs_und5[buf_i],
178 12, ofs_und6[buf_i], bpp);
179 else if (bpp <= 16)
180 range_bpg_offset = get_range_bpg_offset(12, ofs_und6[buf_i],
181 16, ofs_und8[buf_i], bpp);
182 else
183 range_bpg_offset = ofs_und8[buf_i];
184
185 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
186 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
187 }
188 } else {
189 /* fractional bpp part * 10000 (for precision up to 4 decimal places) */
190 int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel);
191
192 static const s8 ofs_und6[] = {
193 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
194 };
195 static const s8 ofs_und8[] = {
196 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
197 };
198 static const s8 ofs_und12[] = {
199 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
200 };
201 static const s8 ofs_und15[] = {
202 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
203 };
204
205 /*
206 * QP table rows have values in increment of 0.5.
207 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
208 * and so on.
209 * 0.5 fractional part with 4 decimal precision becomes 5000
210 */
211 bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
212
213 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
214 u8 range_bpg_offset;
215
216 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
217
218 /* Calculate range_bpg_offset */
219 if (bpp <= 6)
220 range_bpg_offset = ofs_und6[buf_i];
221 else if (bpp <= 8)
222 range_bpg_offset = get_range_bpg_offset(6, ofs_und6[buf_i],
223 8, ofs_und8[buf_i], bpp);
224 else if (bpp <= 12)
225 range_bpg_offset = get_range_bpg_offset(8, ofs_und8[buf_i],
226 12, ofs_und12[buf_i], bpp);
227 else if (bpp <= 15)
228 range_bpg_offset = get_range_bpg_offset(12, ofs_und12[buf_i],
229 15, ofs_und15[buf_i], bpp);
230 else
231 range_bpg_offset = ofs_und15[buf_i];
232
233 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
234 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
235 }
236 }
237 }
238
intel_dsc_slice_dimensions_valid(struct intel_crtc_state * pipe_config,struct drm_dsc_config * vdsc_cfg)239 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
240 struct drm_dsc_config *vdsc_cfg)
241 {
242 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
243 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
244 if (vdsc_cfg->slice_height > 4095)
245 return -EINVAL;
246 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
247 return -EINVAL;
248 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
249 if (vdsc_cfg->slice_width % 2)
250 return -EINVAL;
251 if (vdsc_cfg->slice_height % 2)
252 return -EINVAL;
253 if (vdsc_cfg->slice_height > 4094)
254 return -EINVAL;
255 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
256 return -EINVAL;
257 }
258
259 return 0;
260 }
261
intel_dsc_compute_params(struct intel_crtc_state * pipe_config)262 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
263 {
264 struct intel_display *display = to_intel_display(pipe_config);
265 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
266 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
267 int err;
268 int ret;
269
270 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
271 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
272 pipe_config->dsc.slice_count);
273
274 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
275
276 if (err) {
277 drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");
278 return err;
279 }
280
281 /*
282 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
283 * else 1
284 */
285 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
286 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
287
288 if (DISPLAY_VER(display) >= 14 &&
289 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
290 vdsc_cfg->native_420 = true;
291 /* We do not support YcBCr422 as of now */
292 vdsc_cfg->native_422 = false;
293 vdsc_cfg->simple_422 = false;
294 /* Gen 11 does not support VBR */
295 vdsc_cfg->vbr_enable = false;
296
297 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
298
299 /*
300 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
301 * we need to double the current bpp.
302 */
303 if (vdsc_cfg->native_420)
304 vdsc_cfg->bits_per_pixel <<= 1;
305
306 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
307
308 if (vdsc_cfg->bits_per_component < 8) {
309 drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",
310 vdsc_cfg->bits_per_component);
311 return -EINVAL;
312 }
313
314 drm_dsc_set_rc_buf_thresh(vdsc_cfg);
315
316 /*
317 * From XE_LPD onwards we supports compression bpps in steps of 1
318 * upto uncompressed bpp-1, hence add calculations for all the rc
319 * parameters
320 */
321 if (DISPLAY_VER(display) >= 13) {
322 calculate_rc_params(vdsc_cfg);
323 } else {
324 if ((compressed_bpp == 8 ||
325 compressed_bpp == 12) &&
326 (vdsc_cfg->bits_per_component == 8 ||
327 vdsc_cfg->bits_per_component == 10 ||
328 vdsc_cfg->bits_per_component == 12))
329 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
330 else
331 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
332
333 if (ret)
334 return ret;
335 }
336
337 /*
338 * BitsPerComponent value determines mux_word_size:
339 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
340 * 48 bits otherwise 64
341 */
342 if (vdsc_cfg->bits_per_component <= 10)
343 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
344 else
345 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
346
347 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
348 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
349 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
350
351 return 0;
352 }
353
354 enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc * crtc,enum transcoder cpu_transcoder)355 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
356 {
357 struct intel_display *display = to_intel_display(crtc);
358 enum pipe pipe = crtc->pipe;
359
360 /*
361 * VDSC/joining uses a separate power well, PW2, and requires
362 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
363 *
364 * - ICL eDP/DSI transcoder
365 * - Display version 12 (except RKL) pipe A
366 *
367 * For any other pipe, VDSC/joining uses the power well associated with
368 * the pipe in use. Hence another reference on the pipe power domain
369 * will suffice. (Except no VDSC/joining on ICL pipe A.)
370 */
371 if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
372 pipe == PIPE_A)
373 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
374 else if (is_pipe_dsc(crtc, cpu_transcoder))
375 return POWER_DOMAIN_PIPE(pipe);
376 else
377 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
378 }
379
intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state * crtc_state)380 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
381 {
382 return crtc_state->dsc.num_streams;
383 }
384
intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state * crtc_state)385 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
386 {
387 int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
388 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
389
390 num_vdsc_instances *= num_joined_pipes;
391
392 return num_vdsc_instances;
393 }
394
intel_dsc_get_pps_reg(const struct intel_crtc_state * crtc_state,int pps,i915_reg_t * dsc_reg,int dsc_reg_num)395 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
396 i915_reg_t *dsc_reg, int dsc_reg_num)
397 {
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
399 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
400 enum pipe pipe = crtc->pipe;
401 bool pipe_dsc;
402
403 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
404
405 if (dsc_reg_num >= 4)
406 MISSING_CASE(dsc_reg_num);
407 if (dsc_reg_num >= 3)
408 dsc_reg[2] = BMG_DSC2_PPS(pipe, pps);
409 if (dsc_reg_num >= 2)
410 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);
411 if (dsc_reg_num >= 1)
412 dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);
413 }
414
intel_dsc_pps_write(const struct intel_crtc_state * crtc_state,int pps,u32 pps_val)415 static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
416 int pps, u32 pps_val)
417 {
418 struct intel_display *display = to_intel_display(crtc_state);
419 i915_reg_t dsc_reg[3];
420 int i, vdsc_per_pipe, dsc_reg_num;
421
422 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
423 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
424
425 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
426
427 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
428
429 for (i = 0; i < dsc_reg_num; i++)
430 intel_de_write(display, dsc_reg[i], pps_val);
431 }
432
intel_dsc_pps_configure(const struct intel_crtc_state * crtc_state)433 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
434 {
435 struct intel_display *display = to_intel_display(crtc_state);
436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
437 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
438 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
439 enum pipe pipe = crtc->pipe;
440 u32 pps_val;
441 u32 rc_buf_thresh_dword[4];
442 u32 rc_range_params_dword[8];
443 int i = 0;
444 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
445 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
446
447 /* PPS 0 */
448 pps_val = DSC_PPS0_VER_MAJOR(1) |
449 DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
450 DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
451 DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
452 if (vdsc_cfg->dsc_version_minor == 2) {
453 pps_val |= DSC_PPS0_ALT_ICH_SEL;
454 if (vdsc_cfg->native_420)
455 pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
456 if (vdsc_cfg->native_422)
457 pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
458 }
459 if (vdsc_cfg->block_pred_enable)
460 pps_val |= DSC_PPS0_BLOCK_PREDICTION;
461 if (vdsc_cfg->convert_rgb)
462 pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
463 if (vdsc_cfg->simple_422)
464 pps_val |= DSC_PPS0_422_ENABLE;
465 if (vdsc_cfg->vbr_enable)
466 pps_val |= DSC_PPS0_VBR_ENABLE;
467 intel_dsc_pps_write(crtc_state, 0, pps_val);
468
469 /* PPS 1 */
470 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
471 intel_dsc_pps_write(crtc_state, 1, pps_val);
472
473 /* PPS 2 */
474 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
475 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
476 intel_dsc_pps_write(crtc_state, 2, pps_val);
477
478 /* PPS 3 */
479 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
480 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
481 intel_dsc_pps_write(crtc_state, 3, pps_val);
482
483 /* PPS 4 */
484 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
485 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
486 intel_dsc_pps_write(crtc_state, 4, pps_val);
487
488 /* PPS 5 */
489 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
490 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
491 intel_dsc_pps_write(crtc_state, 5, pps_val);
492
493 /* PPS 6 */
494 pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
495 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
496 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
497 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
498 intel_dsc_pps_write(crtc_state, 6, pps_val);
499
500 /* PPS 7 */
501 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
502 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
503 intel_dsc_pps_write(crtc_state, 7, pps_val);
504
505 /* PPS 8 */
506 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
507 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
508 intel_dsc_pps_write(crtc_state, 8, pps_val);
509
510 /* PPS 9 */
511 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
512 DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
513 intel_dsc_pps_write(crtc_state, 9, pps_val);
514
515 /* PPS 10 */
516 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
517 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
518 DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
519 DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
520 intel_dsc_pps_write(crtc_state, 10, pps_val);
521
522 /* PPS 16 */
523 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
524 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
525 vdsc_cfg->slice_width) |
526 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
527 vdsc_cfg->slice_height);
528 intel_dsc_pps_write(crtc_state, 16, pps_val);
529
530 if (DISPLAY_VER(display) >= 14) {
531 /* PPS 17 */
532 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
533 intel_dsc_pps_write(crtc_state, 17, pps_val);
534
535 /* PPS 18 */
536 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
537 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
538 intel_dsc_pps_write(crtc_state, 18, pps_val);
539 }
540
541 /* Populate the RC_BUF_THRESH registers */
542 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
543 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
544 rc_buf_thresh_dword[i / 4] |=
545 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
546 BITS_PER_BYTE * (i % 4));
547 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
548 intel_de_write(display, DSCA_RC_BUF_THRESH_0,
549 rc_buf_thresh_dword[0]);
550 intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
551 rc_buf_thresh_dword[1]);
552 intel_de_write(display, DSCA_RC_BUF_THRESH_1,
553 rc_buf_thresh_dword[2]);
554 intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
555 rc_buf_thresh_dword[3]);
556 if (vdsc_instances_per_pipe > 1) {
557 intel_de_write(display, DSCC_RC_BUF_THRESH_0,
558 rc_buf_thresh_dword[0]);
559 intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,
560 rc_buf_thresh_dword[1]);
561 intel_de_write(display, DSCC_RC_BUF_THRESH_1,
562 rc_buf_thresh_dword[2]);
563 intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,
564 rc_buf_thresh_dword[3]);
565 }
566 } else {
567 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
568 rc_buf_thresh_dword[0]);
569 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
570 rc_buf_thresh_dword[1]);
571 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
572 rc_buf_thresh_dword[2]);
573 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
574 rc_buf_thresh_dword[3]);
575 if (vdsc_instances_per_pipe > 1) {
576 intel_de_write(display,
577 ICL_DSC1_RC_BUF_THRESH_0(pipe),
578 rc_buf_thresh_dword[0]);
579 intel_de_write(display,
580 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
581 rc_buf_thresh_dword[1]);
582 intel_de_write(display,
583 ICL_DSC1_RC_BUF_THRESH_1(pipe),
584 rc_buf_thresh_dword[2]);
585 intel_de_write(display,
586 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
587 rc_buf_thresh_dword[3]);
588 }
589 }
590
591 /* Populate the RC_RANGE_PARAMETERS registers */
592 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
593 for (i = 0; i < DSC_NUM_BUF_RANGES; i++)
594 rc_range_params_dword[i / 2] |=
595 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
596 RC_BPG_OFFSET_SHIFT) |
597 (vdsc_cfg->rc_range_params[i].range_max_qp <<
598 RC_MAX_QP_SHIFT) |
599 (vdsc_cfg->rc_range_params[i].range_min_qp <<
600 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
601 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
602 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
603 rc_range_params_dword[0]);
604 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,
605 rc_range_params_dword[1]);
606 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
607 rc_range_params_dword[2]);
608 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,
609 rc_range_params_dword[3]);
610 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
611 rc_range_params_dword[4]);
612 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,
613 rc_range_params_dword[5]);
614 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
615 rc_range_params_dword[6]);
616 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,
617 rc_range_params_dword[7]);
618 if (vdsc_instances_per_pipe > 1) {
619 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,
620 rc_range_params_dword[0]);
621 intel_de_write(display,
622 DSCC_RC_RANGE_PARAMETERS_0_UDW,
623 rc_range_params_dword[1]);
624 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,
625 rc_range_params_dword[2]);
626 intel_de_write(display,
627 DSCC_RC_RANGE_PARAMETERS_1_UDW,
628 rc_range_params_dword[3]);
629 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,
630 rc_range_params_dword[4]);
631 intel_de_write(display,
632 DSCC_RC_RANGE_PARAMETERS_2_UDW,
633 rc_range_params_dword[5]);
634 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,
635 rc_range_params_dword[6]);
636 intel_de_write(display,
637 DSCC_RC_RANGE_PARAMETERS_3_UDW,
638 rc_range_params_dword[7]);
639 }
640 } else {
641 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
642 rc_range_params_dword[0]);
643 intel_de_write(display,
644 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
645 rc_range_params_dword[1]);
646 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
647 rc_range_params_dword[2]);
648 intel_de_write(display,
649 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
650 rc_range_params_dword[3]);
651 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
652 rc_range_params_dword[4]);
653 intel_de_write(display,
654 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
655 rc_range_params_dword[5]);
656 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
657 rc_range_params_dword[6]);
658 intel_de_write(display,
659 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
660 rc_range_params_dword[7]);
661 if (vdsc_instances_per_pipe > 1) {
662 intel_de_write(display,
663 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
664 rc_range_params_dword[0]);
665 intel_de_write(display,
666 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
667 rc_range_params_dword[1]);
668 intel_de_write(display,
669 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
670 rc_range_params_dword[2]);
671 intel_de_write(display,
672 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
673 rc_range_params_dword[3]);
674 intel_de_write(display,
675 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
676 rc_range_params_dword[4]);
677 intel_de_write(display,
678 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
679 rc_range_params_dword[5]);
680 intel_de_write(display,
681 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
682 rc_range_params_dword[6]);
683 intel_de_write(display,
684 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
685 rc_range_params_dword[7]);
686 }
687 }
688 }
689
intel_dsc_dsi_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)690 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
691 const struct intel_crtc_state *crtc_state)
692 {
693 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
694 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
695 struct mipi_dsi_device *dsi;
696 struct drm_dsc_picture_parameter_set pps;
697 enum port port;
698
699 if (!crtc_state->dsc.compression_enable)
700 return;
701
702 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
703
704 for_each_dsi_port(port, intel_dsi->ports) {
705 dsi = intel_dsi->dsi_hosts[port]->device;
706
707 mipi_dsi_picture_parameter_set(dsi, &pps);
708 mipi_dsi_compression_mode(dsi, true);
709 }
710 }
711
intel_dsc_dp_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)712 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
713 const struct intel_crtc_state *crtc_state)
714 {
715 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
716 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
717 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
718
719 if (!crtc_state->dsc.compression_enable)
720 return;
721
722 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
723 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
724
725 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
726 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
727
728 dig_port->write_infoframe(encoder, crtc_state,
729 DP_SDP_PPS, &dp_dsc_pps_sdp,
730 sizeof(dp_dsc_pps_sdp));
731 }
732
dss_ctl1_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)733 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
734 {
735 return is_pipe_dsc(crtc, cpu_transcoder) ?
736 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
737 }
738
dss_ctl2_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)739 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
740 {
741 return is_pipe_dsc(crtc, cpu_transcoder) ?
742 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
743 }
744
intel_uncompressed_joiner_enable(const struct intel_crtc_state * crtc_state)745 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
746 {
747 struct intel_display *display = to_intel_display(crtc_state);
748 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
749 u32 dss_ctl1_val = 0;
750
751 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
752 if (intel_crtc_is_bigjoiner_secondary(crtc_state))
753 dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY;
754 else
755 dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
756
757 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
758 dss_ctl1_val);
759 }
760 }
761
intel_dsc_enable(const struct intel_crtc_state * crtc_state)762 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
763 {
764 struct intel_display *display = to_intel_display(crtc_state);
765 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
766 u32 dss_ctl1_val = 0;
767 u32 dss_ctl2_val = 0;
768 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
769
770 if (!crtc_state->dsc.compression_enable)
771 return;
772
773 intel_dsc_pps_configure(crtc_state);
774
775 dss_ctl2_val |= VDSC0_ENABLE;
776 if (vdsc_instances_per_pipe > 1) {
777 dss_ctl2_val |= VDSC1_ENABLE;
778 dss_ctl1_val |= JOINER_ENABLE;
779 }
780
781 if (vdsc_instances_per_pipe > 2) {
782 dss_ctl2_val |= VDSC2_ENABLE;
783 dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
784 }
785
786 if (crtc_state->joiner_pipes) {
787 if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
788 dss_ctl1_val |= ULTRA_JOINER_ENABLE;
789
790 if (intel_crtc_is_ultrajoiner_primary(crtc_state))
791 dss_ctl1_val |= PRIMARY_ULTRA_JOINER_ENABLE;
792
793 dss_ctl1_val |= BIG_JOINER_ENABLE;
794
795 if (intel_crtc_is_bigjoiner_primary(crtc_state))
796 dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
797 }
798 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
799 intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
800 }
801
intel_dsc_disable(const struct intel_crtc_state * old_crtc_state)802 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
803 {
804 struct intel_display *display = to_intel_display(old_crtc_state);
805 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
806
807 /* Disable only if either of them is enabled */
808 if (old_crtc_state->dsc.compression_enable ||
809 old_crtc_state->joiner_pipes) {
810 intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
811 intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
812 }
813 }
814
intel_dsc_pps_read(struct intel_crtc_state * crtc_state,int pps,bool * all_equal)815 static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
816 bool *all_equal)
817 {
818 struct intel_display *display = to_intel_display(crtc_state);
819 i915_reg_t dsc_reg[3];
820 int i, vdsc_per_pipe, dsc_reg_num;
821 u32 val;
822
823 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
824 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
825
826 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
827
828 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
829
830 *all_equal = true;
831
832 val = intel_de_read(display, dsc_reg[0]);
833
834 for (i = 1; i < dsc_reg_num; i++) {
835 if (intel_de_read(display, dsc_reg[i]) != val) {
836 *all_equal = false;
837 break;
838 }
839 }
840
841 return val;
842 }
843
intel_dsc_pps_read_and_verify(struct intel_crtc_state * crtc_state,int pps)844 static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
845 {
846 struct intel_display *display = to_intel_display(crtc_state);
847 u32 val;
848 bool all_equal;
849
850 val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
851 drm_WARN_ON(display->drm, !all_equal);
852
853 return val;
854 }
855
intel_dsc_get_pps_config(struct intel_crtc_state * crtc_state)856 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
857 {
858 struct intel_display *display = to_intel_display(crtc_state);
859 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
860 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
861 u32 pps_temp;
862
863 /* PPS 0 */
864 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
865
866 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
867 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);
868 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
869 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
870 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
871 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
872 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
873 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
874
875 /* PPS 1 */
876 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
877
878 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
879
880 if (vdsc_cfg->native_420)
881 vdsc_cfg->bits_per_pixel >>= 1;
882
883 crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
884
885 /* PPS 2 */
886 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
887
888 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances;
889 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);
890
891 /* PPS 3 */
892 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
893
894 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
895 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);
896
897 /* PPS 4 */
898 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
899
900 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
901 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
902
903 /* PPS 5 */
904 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
905
906 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
907 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
908
909 /* PPS 6 */
910 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
911
912 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
913 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
914 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
915 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
916
917 /* PPS 7 */
918 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
919
920 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
921 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
922
923 /* PPS 8 */
924 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
925
926 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
927 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);
928
929 /* PPS 9 */
930 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
931
932 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);
933
934 /* PPS 10 */
935 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
936
937 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
938 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
939
940 /* PPS 16 */
941 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
942
943 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
944
945 if (DISPLAY_VER(display) >= 14) {
946 /* PPS 17 */
947 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
948
949 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
950
951 /* PPS 18 */
952 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
953
954 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
955 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
956 }
957 }
958
intel_dsc_get_config(struct intel_crtc_state * crtc_state)959 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
960 {
961 struct intel_display *display = to_intel_display(crtc_state);
962 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
963 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
964 enum intel_display_power_domain power_domain;
965 intel_wakeref_t wakeref;
966 u32 dss_ctl1, dss_ctl2;
967
968 if (!intel_dsc_source_support(crtc_state))
969 return;
970
971 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
972
973 wakeref = intel_display_power_get_if_enabled(display, power_domain);
974 if (!wakeref)
975 return;
976
977 dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
978 dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));
979
980 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
981 if (!crtc_state->dsc.compression_enable)
982 goto out;
983
984 if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES))
985 crtc_state->dsc.num_streams = 3;
986 else if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
987 crtc_state->dsc.num_streams = 2;
988 else
989 crtc_state->dsc.num_streams = 1;
990
991 intel_dsc_get_pps_config(crtc_state);
992 out:
993 intel_display_power_put(display, power_domain, wakeref);
994 }
995
intel_vdsc_dump_state(struct drm_printer * p,int indent,const struct intel_crtc_state * crtc_state)996 static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
997 const struct intel_crtc_state *crtc_state)
998 {
999 drm_printf_indent(p, indent,
1000 "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n",
1001 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
1002 crtc_state->dsc.slice_count,
1003 crtc_state->dsc.num_streams);
1004 }
1005
intel_vdsc_state_dump(struct drm_printer * p,int indent,const struct intel_crtc_state * crtc_state)1006 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
1007 const struct intel_crtc_state *crtc_state)
1008 {
1009 if (!crtc_state->dsc.compression_enable)
1010 return;
1011
1012 intel_vdsc_dump_state(p, indent, crtc_state);
1013 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
1014 }
1015
intel_vdsc_min_cdclk(const struct intel_crtc_state * crtc_state)1016 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
1017 {
1018 struct intel_display *display = to_intel_display(crtc_state);
1019 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
1020 int min_cdclk;
1021
1022 if (!crtc_state->dsc.compression_enable)
1023 return 0;
1024
1025 /*
1026 * When we decide to use only one VDSC engine, since
1027 * each VDSC operates with 1 ppc throughput, pixel clock
1028 * cannot be higher than the VDSC clock (cdclk)
1029 * If there 2 VDSC engines, then pixel clock can't be higher than
1030 * VDSC clock(cdclk) * 2 and so on.
1031 */
1032 min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
1033
1034 if (crtc_state->joiner_pipes) {
1035 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
1036
1037 /*
1038 * According to Bigjoiner bw check:
1039 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
1040 *
1041 * We have already computed compressed_bpp, so now compute the min CDCLK that
1042 * is required to support this compressed_bpp.
1043 *
1044 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
1045 *
1046 * Since PPC = 2 with bigjoiner
1047 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
1048 */
1049 int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
1050 int min_cdclk_bj =
1051 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
1052 pixel_clock) / (2 * bigjoiner_interface_bits);
1053
1054 min_cdclk = max(min_cdclk, min_cdclk_bj);
1055 }
1056
1057 return min_cdclk;
1058 }
1059