Lines Matching +full:display +full:- +full:pipe
1 // SPDX-License-Identifier: MIT
24 enum pipe pch_transcoder) in intel_has_pch_trancoder()
30 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) in intel_crtc_pch_transcoder()
32 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_pch_transcoder()
37 return crtc->pipe; in intel_crtc_pch_transcoder()
41 enum pipe pipe, enum port port, in assert_pch_dp_disabled() argument
44 struct intel_display *display = &dev_priv->display; in assert_pch_dp_disabled() local
45 enum pipe port_pipe; in assert_pch_dp_disabled()
48 state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); in assert_pch_dp_disabled()
50 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, in assert_pch_dp_disabled()
52 port_name(port), pipe_name(pipe)); in assert_pch_dp_disabled()
54 INTEL_DISPLAY_STATE_WARN(display, in assert_pch_dp_disabled()
61 enum pipe pipe, enum port port, in assert_pch_hdmi_disabled() argument
64 struct intel_display *display = &dev_priv->display; in assert_pch_hdmi_disabled() local
65 enum pipe port_pipe; in assert_pch_hdmi_disabled()
68 state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe); in assert_pch_hdmi_disabled()
70 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, in assert_pch_hdmi_disabled()
72 port_name(port), pipe_name(pipe)); in assert_pch_hdmi_disabled()
74 INTEL_DISPLAY_STATE_WARN(display, in assert_pch_hdmi_disabled()
81 enum pipe pipe) in assert_pch_ports_disabled() argument
83 struct intel_display *display = &dev_priv->display; in assert_pch_ports_disabled() local
84 enum pipe port_pipe; in assert_pch_ports_disabled()
86 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); in assert_pch_ports_disabled()
87 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C); in assert_pch_ports_disabled()
88 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D); in assert_pch_ports_disabled()
90 INTEL_DISPLAY_STATE_WARN(display, in assert_pch_ports_disabled()
91 intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe, in assert_pch_ports_disabled()
93 pipe_name(pipe)); in assert_pch_ports_disabled()
95 INTEL_DISPLAY_STATE_WARN(display, in assert_pch_ports_disabled()
96 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe, in assert_pch_ports_disabled()
98 pipe_name(pipe)); in assert_pch_ports_disabled()
101 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); in assert_pch_ports_disabled()
102 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC); in assert_pch_ports_disabled()
103 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID); in assert_pch_ports_disabled()
107 enum pipe pipe) in assert_pch_transcoder_disabled() argument
109 struct intel_display *display = &dev_priv->display; in assert_pch_transcoder_disabled() local
113 val = intel_de_read(display, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
115 INTEL_DISPLAY_STATE_WARN(display, enabled, in assert_pch_transcoder_disabled()
116 "transcoder assertion failed, should be off on pipe %c but is still active\n", in assert_pch_transcoder_disabled()
117 pipe_name(pipe)); in assert_pch_transcoder_disabled()
129 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_hdmi_port()
148 drm_dbg_kms(&dev_priv->drm, in ibx_sanitize_pch_dp_port()
184 struct intel_display *display = to_intel_display(crtc); in intel_pch_transcoder_set_m1_n1() local
185 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_set_m1_n1() local
187 intel_set_m_n(display, m_n, in intel_pch_transcoder_set_m1_n1()
188 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), in intel_pch_transcoder_set_m1_n1()
189 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_set_m1_n1()
195 struct intel_display *display = to_intel_display(crtc); in intel_pch_transcoder_set_m2_n2() local
196 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_set_m2_n2() local
198 intel_set_m_n(display, m_n, in intel_pch_transcoder_set_m2_n2()
199 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), in intel_pch_transcoder_set_m2_n2()
200 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); in intel_pch_transcoder_set_m2_n2()
206 struct intel_display *display = to_intel_display(crtc); in intel_pch_transcoder_get_m1_n1() local
207 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m1_n1() local
209 intel_get_m_n(display, m_n, in intel_pch_transcoder_get_m1_n1()
210 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), in intel_pch_transcoder_get_m1_n1()
211 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m1_n1()
217 struct intel_display *display = to_intel_display(crtc); in intel_pch_transcoder_get_m2_n2() local
218 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m2_n2() local
220 intel_get_m_n(display, m_n, in intel_pch_transcoder_get_m2_n2()
221 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), in intel_pch_transcoder_get_m2_n2()
222 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); in intel_pch_transcoder_get_m2_n2()
226 enum pipe pch_transcoder) in ilk_pch_transcoder_set_timings()
228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pch_transcoder_set_timings()
229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pch_transcoder_set_timings()
230 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in ilk_pch_transcoder_set_timings()
251 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_enable_pch_transcoder()
252 struct intel_display *display = to_intel_display(crtc); in ilk_enable_pch_transcoder() local
253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_enable_pch_transcoder()
254 enum pipe pipe = crtc->pipe; in ilk_enable_pch_transcoder() local
259 assert_shared_dpll_enabled(display, crtc_state->shared_dpll); in ilk_enable_pch_transcoder()
262 assert_fdi_tx_enabled(display, pipe); in ilk_enable_pch_transcoder()
263 assert_fdi_rx_enabled(display, pipe); in ilk_enable_pch_transcoder()
266 reg = TRANS_CHICKEN2(pipe); in ilk_enable_pch_transcoder()
267 val = intel_de_read(display, reg); in ilk_enable_pch_transcoder()
275 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in ilk_enable_pch_transcoder()
276 intel_de_write(display, reg, val); in ilk_enable_pch_transcoder()
279 reg = PCH_TRANSCONF(pipe); in ilk_enable_pch_transcoder()
280 val = intel_de_read(display, reg); in ilk_enable_pch_transcoder()
281 pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe)); in ilk_enable_pch_transcoder()
286 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in ilk_enable_pch_transcoder()
311 intel_de_write(display, reg, val | TRANS_ENABLE); in ilk_enable_pch_transcoder()
312 if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100)) in ilk_enable_pch_transcoder()
313 drm_err(display->drm, "failed to enable transcoder %c\n", in ilk_enable_pch_transcoder()
314 pipe_name(pipe)); in ilk_enable_pch_transcoder()
319 struct intel_display *display = to_intel_display(crtc); in ilk_disable_pch_transcoder() local
320 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_disable_pch_transcoder()
321 enum pipe pipe = crtc->pipe; in ilk_disable_pch_transcoder() local
325 assert_fdi_tx_disabled(display, pipe); in ilk_disable_pch_transcoder()
326 assert_fdi_rx_disabled(display, pipe); in ilk_disable_pch_transcoder()
329 assert_pch_ports_disabled(dev_priv, pipe); in ilk_disable_pch_transcoder()
331 reg = PCH_TRANSCONF(pipe); in ilk_disable_pch_transcoder()
335 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", in ilk_disable_pch_transcoder()
336 pipe_name(pipe)); in ilk_disable_pch_transcoder()
340 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), in ilk_disable_pch_transcoder()
360 * - PCH PLLs
361 * - FDI training & RX/TX
362 * - update transcoder timings
363 * - DP transcoding bits
364 * - transcoder
369 struct intel_display *display = to_intel_display(state); in ilk_pch_enable() local
370 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pch_enable()
373 enum pipe pipe = crtc->pipe; in ilk_pch_enable() local
376 assert_pch_transcoder_disabled(dev_priv, pipe); in ilk_pch_enable()
388 temp = intel_de_read(display, PCH_DPLL_SEL); in ilk_pch_enable()
389 temp |= TRANS_DPLL_ENABLE(pipe); in ilk_pch_enable()
390 sel = TRANS_DPLLB_SEL(pipe); in ilk_pch_enable()
391 if (crtc_state->shared_dpll == in ilk_pch_enable()
392 intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) in ilk_pch_enable()
396 intel_de_write(display, PCH_DPLL_SEL, temp); in ilk_pch_enable()
405 * get_shared_dpll unconditionally resets the pll - we need that in ilk_pch_enable()
411 assert_pps_unlocked(display, pipe); in ilk_pch_enable()
413 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); in ilk_pch_enable()
414 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2); in ilk_pch_enable()
416 ilk_pch_transcoder_set_timings(crtc_state, pipe); in ilk_pch_enable()
424 &crtc_state->hw.adjusted_mode; in ilk_pch_enable()
425 u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe)) in ilk_pch_enable()
427 i915_reg_t reg = TRANS_DP_CTL(pipe); in ilk_pch_enable()
430 temp = intel_de_read(display, reg); in ilk_pch_enable()
438 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in ilk_pch_enable()
440 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in ilk_pch_enable()
443 port = intel_get_crtc_new_encoder(state, crtc_state)->port; in ilk_pch_enable()
444 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); in ilk_pch_enable()
447 intel_de_write(display, reg, temp); in ilk_pch_enable()
462 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pch_post_disable()
463 enum pipe pipe = crtc->pipe; in ilk_pch_post_disable() local
469 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), in ilk_pch_post_disable()
475 TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0); in ilk_pch_post_disable()
483 struct intel_display *display = to_intel_display(crtc_state); in ilk_pch_clock_get() local
489 * In case there is an active pipe without active ports, in ilk_pch_clock_get()
493 crtc_state->hw.adjusted_mode.crtc_clock = in ilk_pch_clock_get()
494 intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state), in ilk_pch_clock_get()
495 &crtc_state->fdi_m_n); in ilk_pch_clock_get()
500 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_pch_get_config()
501 struct intel_display *display = to_intel_display(crtc); in ilk_pch_get_config() local
502 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_pch_get_config()
504 enum pipe pipe = crtc->pipe; in ilk_pch_get_config() local
509 if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) in ilk_pch_get_config()
512 crtc_state->has_pch_encoder = true; in ilk_pch_get_config()
514 tmp = intel_de_read(display, FDI_RX_CTL(pipe)); in ilk_pch_get_config()
515 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in ilk_pch_get_config()
518 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, in ilk_pch_get_config()
519 &crtc_state->fdi_m_n); in ilk_pch_get_config()
523 * The pipe->pch transcoder and pch transcoder->pll in ilk_pch_get_config()
526 pll_id = (enum intel_dpll_id) pipe; in ilk_pch_get_config()
528 tmp = intel_de_read(display, PCH_DPLL_SEL); in ilk_pch_get_config()
529 if (tmp & TRANS_DPLLB_SEL(pipe)) in ilk_pch_get_config()
535 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); in ilk_pch_get_config()
536 pll = crtc_state->shared_dpll; in ilk_pch_get_config()
538 pll_active = intel_dpll_get_hw_state(display, pll, in ilk_pch_get_config()
539 &crtc_state->dpll_hw_state); in ilk_pch_get_config()
540 drm_WARN_ON(display->drm, !pll_active); in ilk_pch_get_config()
542 tmp = crtc_state->dpll_hw_state.i9xx.dpll; in ilk_pch_get_config()
543 crtc_state->pixel_multiplier = in ilk_pch_get_config()
552 struct intel_display *display = to_intel_display(crtc_state); in lpt_enable_pch_transcoder() local
553 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in lpt_enable_pch_transcoder()
554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_enable_pch_transcoder()
555 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in lpt_enable_pch_transcoder()
559 assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder); in lpt_enable_pch_transcoder()
560 assert_fdi_rx_enabled(display, PIPE_A); in lpt_enable_pch_transcoder()
567 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); in lpt_enable_pch_transcoder()
582 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); in lpt_enable_pch_transcoder()
591 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); in lpt_disable_pch_transcoder()
600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_pch_enable()
617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_pch_disable()
626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in lpt_pch_get_config()
627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in lpt_pch_get_config()
633 crtc_state->has_pch_encoder = true; in lpt_pch_get_config()
636 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> in lpt_pch_get_config()
639 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, in lpt_pch_get_config()
640 &crtc_state->fdi_m_n); in lpt_pch_get_config()
642 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); in lpt_pch_get_config()