Lines Matching +full:display +full:- +full:pipe
41 * The i915 driver checks for display fifo underruns using the interrupt signals
43 * debug display issues, especially watermark settings.
47 * occurrence until the next modeset on a given pipe.
50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
58 static bool ivb_can_enable_err_int(struct intel_display *display) in ivb_can_enable_err_int() argument
60 struct drm_i915_private *dev_priv = to_i915(display->drm); in ivb_can_enable_err_int()
62 enum pipe pipe; in ivb_can_enable_err_int() local
64 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
66 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
67 crtc = intel_crtc_for_pipe(display, pipe); in ivb_can_enable_err_int()
69 if (crtc->cpu_fifo_underrun_disabled) in ivb_can_enable_err_int()
76 static bool cpt_can_enable_serr_int(struct intel_display *display) in cpt_can_enable_serr_int() argument
78 struct drm_i915_private *dev_priv = to_i915(display->drm); in cpt_can_enable_serr_int()
79 enum pipe pipe; in cpt_can_enable_serr_int() local
82 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
84 for_each_pipe(display, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(display, pipe); in cpt_can_enable_serr_int()
87 if (crtc->pch_fifo_underrun_disabled) in cpt_can_enable_serr_int()
96 struct intel_display *display = to_intel_display(crtc); in i9xx_check_fifo_underruns() local
97 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns()
98 i915_reg_t reg = PIPESTAT(display, crtc->pipe); in i9xx_check_fifo_underruns()
101 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
103 if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
106 enable_mask = i915_pipestat_enable_mask(display, crtc->pipe); in i9xx_check_fifo_underruns()
107 intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
108 intel_de_posting_read(display, reg); in i9xx_check_fifo_underruns()
110 trace_intel_cpu_fifo_underrun(display, crtc->pipe); in i9xx_check_fifo_underruns()
111 drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
114 static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, in i9xx_set_fifo_underrun_reporting() argument
115 enum pipe pipe, in i9xx_set_fifo_underrun_reporting() argument
118 struct drm_i915_private *dev_priv = to_i915(display->drm); in i9xx_set_fifo_underrun_reporting()
119 i915_reg_t reg = PIPESTAT(display, pipe); in i9xx_set_fifo_underrun_reporting()
121 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_set_fifo_underrun_reporting()
124 u32 enable_mask = i915_pipestat_enable_mask(display, pipe); in i9xx_set_fifo_underrun_reporting()
126 intel_de_write(display, reg, in i9xx_set_fifo_underrun_reporting()
128 intel_de_posting_read(display, reg); in i9xx_set_fifo_underrun_reporting()
130 if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
131 drm_err(display->drm, "pipe %c underrun\n", in i9xx_set_fifo_underrun_reporting()
132 pipe_name(pipe)); in i9xx_set_fifo_underrun_reporting()
136 static void ilk_set_fifo_underrun_reporting(struct intel_display *display, in ilk_set_fifo_underrun_reporting() argument
137 enum pipe pipe, bool enable) in ilk_set_fifo_underrun_reporting() argument
139 struct drm_i915_private *dev_priv = to_i915(display->drm); in ilk_set_fifo_underrun_reporting()
140 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
151 struct intel_display *display = to_intel_display(crtc); in ivb_check_fifo_underruns() local
152 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ivb_check_fifo_underruns()
153 enum pipe pipe = crtc->pipe; in ivb_check_fifo_underruns() local
154 u32 err_int = intel_de_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
156 lockdep_assert_held(&dev_priv->irq_lock); in ivb_check_fifo_underruns()
158 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) in ivb_check_fifo_underruns()
161 intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
162 intel_de_posting_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
164 trace_intel_cpu_fifo_underrun(display, pipe); in ivb_check_fifo_underruns()
165 drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); in ivb_check_fifo_underruns()
168 static void ivb_set_fifo_underrun_reporting(struct intel_display *display, in ivb_set_fifo_underrun_reporting() argument
169 enum pipe pipe, bool enable, in ivb_set_fifo_underrun_reporting() argument
172 struct drm_i915_private *dev_priv = to_i915(display->drm); in ivb_set_fifo_underrun_reporting()
174 intel_de_write(display, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
175 ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_set_fifo_underrun_reporting()
177 if (!ivb_can_enable_err_int(display)) in ivb_set_fifo_underrun_reporting()
185 intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
186 drm_err(display->drm, in ivb_set_fifo_underrun_reporting()
187 "uncleared fifo underrun on pipe %c\n", in ivb_set_fifo_underrun_reporting()
188 pipe_name(pipe)); in ivb_set_fifo_underrun_reporting()
193 static void bdw_set_fifo_underrun_reporting(struct intel_display *display, in bdw_set_fifo_underrun_reporting() argument
194 enum pipe pipe, bool enable) in bdw_set_fifo_underrun_reporting() argument
196 struct drm_i915_private *dev_priv = to_i915(display->drm); in bdw_set_fifo_underrun_reporting()
199 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); in bdw_set_fifo_underrun_reporting()
201 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); in bdw_set_fifo_underrun_reporting()
204 static void ibx_set_fifo_underrun_reporting(struct intel_display *display, in ibx_set_fifo_underrun_reporting() argument
205 enum pipe pch_transcoder, in ibx_set_fifo_underrun_reporting()
208 struct drm_i915_private *dev_priv = to_i915(display->drm); in ibx_set_fifo_underrun_reporting()
220 struct intel_display *display = to_intel_display(crtc); in cpt_check_pch_fifo_underruns() local
221 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in cpt_check_pch_fifo_underruns()
222 enum pipe pch_transcoder = crtc->pipe; in cpt_check_pch_fifo_underruns()
223 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
225 lockdep_assert_held(&dev_priv->irq_lock); in cpt_check_pch_fifo_underruns()
230 intel_de_write(display, SERR_INT, in cpt_check_pch_fifo_underruns()
232 intel_de_posting_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
234 trace_intel_pch_fifo_underrun(display, pch_transcoder); in cpt_check_pch_fifo_underruns()
235 drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n", in cpt_check_pch_fifo_underruns()
239 static void cpt_set_fifo_underrun_reporting(struct intel_display *display, in cpt_set_fifo_underrun_reporting() argument
240 enum pipe pch_transcoder, in cpt_set_fifo_underrun_reporting()
243 struct drm_i915_private *dev_priv = to_i915(display->drm); in cpt_set_fifo_underrun_reporting()
246 intel_de_write(display, SERR_INT, in cpt_set_fifo_underrun_reporting()
249 if (!cpt_can_enable_serr_int(display)) in cpt_set_fifo_underrun_reporting()
256 if (old && intel_de_read(display, SERR_INT) & in cpt_set_fifo_underrun_reporting()
258 drm_err(display->drm, in cpt_set_fifo_underrun_reporting()
265 static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, in __intel_set_cpu_fifo_underrun_reporting() argument
266 enum pipe pipe, bool enable) in __intel_set_cpu_fifo_underrun_reporting() argument
268 struct drm_i915_private *dev_priv = to_i915(display->drm); in __intel_set_cpu_fifo_underrun_reporting()
269 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in __intel_set_cpu_fifo_underrun_reporting()
272 lockdep_assert_held(&dev_priv->irq_lock); in __intel_set_cpu_fifo_underrun_reporting()
274 old = !crtc->cpu_fifo_underrun_disabled; in __intel_set_cpu_fifo_underrun_reporting()
275 crtc->cpu_fifo_underrun_disabled = !enable; in __intel_set_cpu_fifo_underrun_reporting()
277 if (HAS_GMCH(display)) in __intel_set_cpu_fifo_underrun_reporting()
278 i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
279 else if (display->platform.ironlake || display->platform.sandybridge) in __intel_set_cpu_fifo_underrun_reporting()
280 ilk_set_fifo_underrun_reporting(display, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
281 else if (DISPLAY_VER(display) == 7) in __intel_set_cpu_fifo_underrun_reporting()
282 ivb_set_fifo_underrun_reporting(display, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
283 else if (DISPLAY_VER(display) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
284 bdw_set_fifo_underrun_reporting(display, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
290 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting state
291 * @display: display device instance
292 * @pipe: (CPU) pipe to set state for
295 * This function sets the fifo underrun state for @pipe. It is used in the
297 * expected when disabling or enabling the pipe.
299 * Notice that on some platforms disabling underrun reports for one pipe
300 * disables for all due to shared interrupts. Actual reporting is still per-pipe
305 bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, in intel_set_cpu_fifo_underrun_reporting() argument
306 enum pipe pipe, bool enable) in intel_set_cpu_fifo_underrun_reporting() argument
308 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_set_cpu_fifo_underrun_reporting()
312 spin_lock_irqsave(&dev_priv->irq_lock, flags); in intel_set_cpu_fifo_underrun_reporting()
313 ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable); in intel_set_cpu_fifo_underrun_reporting()
314 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); in intel_set_cpu_fifo_underrun_reporting()
320 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
321 * @display: display device instance
322 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
333 bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, in intel_set_pch_fifo_underrun_reporting() argument
334 enum pipe pch_transcoder, in intel_set_pch_fifo_underrun_reporting()
337 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_set_pch_fifo_underrun_reporting()
338 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder); in intel_set_pch_fifo_underrun_reporting()
343 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT in intel_set_pch_fifo_underrun_reporting()
345 * pch transcoder -> pipe lookups from interrupt code simply store the in intel_set_pch_fifo_underrun_reporting()
351 spin_lock_irqsave(&dev_priv->irq_lock, flags); in intel_set_pch_fifo_underrun_reporting()
353 old = !crtc->pch_fifo_underrun_disabled; in intel_set_pch_fifo_underrun_reporting()
354 crtc->pch_fifo_underrun_disabled = !enable; in intel_set_pch_fifo_underrun_reporting()
357 ibx_set_fifo_underrun_reporting(display, in intel_set_pch_fifo_underrun_reporting()
361 cpt_set_fifo_underrun_reporting(display, in intel_set_pch_fifo_underrun_reporting()
365 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); in intel_set_pch_fifo_underrun_reporting()
370 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
371 * @display: display device instance
372 * @pipe: (CPU) pipe to set state for
378 void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, in intel_cpu_fifo_underrun_irq_handler() argument
379 enum pipe pipe) in intel_cpu_fifo_underrun_irq_handler() argument
381 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_cpu_fifo_underrun_irq_handler()
388 if (HAS_GMCH(display) && in intel_cpu_fifo_underrun_irq_handler()
389 crtc->cpu_fifo_underrun_disabled) in intel_cpu_fifo_underrun_irq_handler()
392 if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) { in intel_cpu_fifo_underrun_irq_handler()
393 trace_intel_cpu_fifo_underrun(display, pipe); in intel_cpu_fifo_underrun_irq_handler()
395 drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); in intel_cpu_fifo_underrun_irq_handler()
398 intel_fbc_handle_fifo_underrun_irq(display); in intel_cpu_fifo_underrun_irq_handler()
402 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
403 * @display: display device instance
404 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
410 void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, in intel_pch_fifo_underrun_irq_handler() argument
411 enum pipe pch_transcoder) in intel_pch_fifo_underrun_irq_handler()
413 if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, in intel_pch_fifo_underrun_irq_handler()
415 trace_intel_pch_fifo_underrun(display, pch_transcoder); in intel_pch_fifo_underrun_irq_handler()
416 drm_err(display->drm, "PCH transcoder %c FIFO underrun\n", in intel_pch_fifo_underrun_irq_handler()
422 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
423 * @display: display device instance
430 void intel_check_cpu_fifo_underruns(struct intel_display *display) in intel_check_cpu_fifo_underruns() argument
432 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_check_cpu_fifo_underruns()
435 spin_lock_irq(&dev_priv->irq_lock); in intel_check_cpu_fifo_underruns()
437 for_each_intel_crtc(display->drm, crtc) { in intel_check_cpu_fifo_underruns()
438 if (crtc->cpu_fifo_underrun_disabled) in intel_check_cpu_fifo_underruns()
441 if (HAS_GMCH(display)) in intel_check_cpu_fifo_underruns()
443 else if (DISPLAY_VER(display) == 7) in intel_check_cpu_fifo_underruns()
447 spin_unlock_irq(&dev_priv->irq_lock); in intel_check_cpu_fifo_underruns()
451 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
452 * @display: display device instance
458 void intel_check_pch_fifo_underruns(struct intel_display *display) in intel_check_pch_fifo_underruns() argument
460 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_check_pch_fifo_underruns()
463 spin_lock_irq(&dev_priv->irq_lock); in intel_check_pch_fifo_underruns()
465 for_each_intel_crtc(display->drm, crtc) { in intel_check_pch_fifo_underruns()
466 if (crtc->pch_fifo_underrun_disabled) in intel_check_pch_fifo_underruns()
473 spin_unlock_irq(&dev_priv->irq_lock); in intel_check_pch_fifo_underruns()
476 void intel_init_fifo_underrun_reporting(struct intel_display *display, in intel_init_fifo_underrun_reporting() argument
480 struct drm_i915_private *i915 = to_i915(display->drm); in intel_init_fifo_underrun_reporting()
482 crtc->cpu_fifo_underrun_disabled = !enable; in intel_init_fifo_underrun_reporting()
486 * within the crtc. With crtc for pipe A housing the underrun in intel_init_fifo_underrun_reporting()
487 * reporting state for PCH transcoder A, crtc for pipe B housing in intel_init_fifo_underrun_reporting()
488 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, in intel_init_fifo_underrun_reporting()
489 * and marking underrun reporting as disabled for the non-existing in intel_init_fifo_underrun_reporting()
493 if (intel_has_pch_trancoder(i915, crtc->pipe)) in intel_init_fifo_underrun_reporting()
494 crtc->pch_fifo_underrun_disabled = !enable; in intel_init_fifo_underrun_reporting()