Lines Matching +full:display +full:- +full:pipe
1 // SPDX-License-Identifier: MIT
23 static void vlv_steal_power_sequencer(struct intel_display *display,
24 enum pipe pipe);
31 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
32 struct intel_pps *pps = &intel_dp->pps; in pps_name()
34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
35 switch (pps->vlv_pps_pipe) { in pps_name()
47 MISSING_CASE(pps->vlv_pps_pipe); in pps_name()
51 switch (pps->pps_idx) { in pps_name()
57 MISSING_CASE(pps->pps_idx); in pps_name()
67 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
73 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); in intel_pps_lock()
74 mutex_lock(&display->pps.mutex); in intel_pps_lock()
82 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
84 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
85 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); in intel_pps_unlock()
93 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
94 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_power_sequencer_kick()
96 enum pipe pipe = intel_dp->pps.vlv_pps_pipe; in vlv_power_sequencer_kick() local
98 enum dpio_phy phy = vlv_pipe_to_phy(pipe); in vlv_power_sequencer_kick()
99 enum dpio_channel ch = vlv_pipe_to_channel(pipe); in vlv_power_sequencer_kick()
102 if (drm_WARN(display->drm, in vlv_power_sequencer_kick()
103 intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
106 dig_port->base.base.base.id, dig_port->base.base.name)) in vlv_power_sequencer_kick()
109 drm_dbg_kms(display->drm, in vlv_power_sequencer_kick()
112 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_power_sequencer_kick()
114 /* Preserve the BIOS-computed detected bit. This is in vlv_power_sequencer_kick()
115 * supposed to be read-only. in vlv_power_sequencer_kick()
117 DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
122 if (display->platform.cherryview) in vlv_power_sequencer_kick()
123 DP |= DP_PIPE_SEL_CHV(pipe); in vlv_power_sequencer_kick()
125 DP |= DP_PIPE_SEL(pipe); in vlv_power_sequencer_kick()
127 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
130 * The DPLL for the pipe must be enabled for this to work. in vlv_power_sequencer_kick()
134 release_cl_override = display->platform.cherryview && in vlv_power_sequencer_kick()
135 !chv_phy_powergate_ch(display, phy, ch, true); in vlv_power_sequencer_kick()
137 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) { in vlv_power_sequencer_kick()
138 drm_err(display->drm, in vlv_power_sequencer_kick()
139 "Failed to force on PLL for pipe %c!\n", in vlv_power_sequencer_kick()
140 pipe_name(pipe)); in vlv_power_sequencer_kick()
151 intel_de_write(display, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
152 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
154 intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
155 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
157 intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
158 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
161 vlv_force_pll_off(dev_priv, pipe); in vlv_power_sequencer_kick()
164 chv_phy_powergate_ch(display, phy, ch, false); in vlv_power_sequencer_kick()
168 static enum pipe vlv_find_free_pps(struct intel_display *display) in vlv_find_free_pps() argument
177 for_each_intel_dp(display->drm, encoder) { in vlv_find_free_pps()
180 if (encoder->type == INTEL_OUTPUT_EDP) { in vlv_find_free_pps()
181 drm_WARN_ON(display->drm, in vlv_find_free_pps()
182 intel_dp->pps.vlv_active_pipe != INVALID_PIPE && in vlv_find_free_pps()
183 intel_dp->pps.vlv_active_pipe != in vlv_find_free_pps()
184 intel_dp->pps.vlv_pps_pipe); in vlv_find_free_pps()
186 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE) in vlv_find_free_pps()
187 pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe); in vlv_find_free_pps()
189 drm_WARN_ON(display->drm, in vlv_find_free_pps()
190 intel_dp->pps.vlv_pps_pipe != INVALID_PIPE); in vlv_find_free_pps()
192 if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE) in vlv_find_free_pps()
193 pipes &= ~(1 << intel_dp->pps.vlv_active_pipe); in vlv_find_free_pps()
200 return ffs(pipes) - 1; in vlv_find_free_pps()
203 static enum pipe
206 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_pipe() local
208 enum pipe pipe; in vlv_power_sequencer_pipe() local
210 lockdep_assert_held(&display->pps.mutex); in vlv_power_sequencer_pipe()
213 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in vlv_power_sequencer_pipe()
215 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE && in vlv_power_sequencer_pipe()
216 intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe); in vlv_power_sequencer_pipe()
218 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE) in vlv_power_sequencer_pipe()
219 return intel_dp->pps.vlv_pps_pipe; in vlv_power_sequencer_pipe()
221 pipe = vlv_find_free_pps(display); in vlv_power_sequencer_pipe()
227 if (drm_WARN_ON(display->drm, pipe == INVALID_PIPE)) in vlv_power_sequencer_pipe()
228 pipe = PIPE_A; in vlv_power_sequencer_pipe()
230 vlv_steal_power_sequencer(display, pipe); in vlv_power_sequencer_pipe()
231 intel_dp->pps.vlv_pps_pipe = pipe; in vlv_power_sequencer_pipe()
233 drm_dbg_kms(display->drm, in vlv_power_sequencer_pipe()
236 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_power_sequencer_pipe()
238 /* init power sequencer on this pipe and port */ in vlv_power_sequencer_pipe()
248 return intel_dp->pps.vlv_pps_pipe; in vlv_power_sequencer_pipe()
254 struct intel_display *display = to_intel_display(intel_dp); in bxt_power_sequencer_idx() local
255 int pps_idx = intel_dp->pps.pps_idx; in bxt_power_sequencer_idx()
257 lockdep_assert_held(&display->pps.mutex); in bxt_power_sequencer_idx()
260 drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp)); in bxt_power_sequencer_idx()
262 if (!intel_dp->pps.bxt_pps_reset) in bxt_power_sequencer_idx()
265 intel_dp->pps.bxt_pps_reset = false; in bxt_power_sequencer_idx()
276 typedef bool (*pps_check)(struct intel_display *display, int pps_idx);
278 static bool pps_has_pp_on(struct intel_display *display, int pps_idx) in pps_has_pp_on() argument
280 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON; in pps_has_pp_on()
283 static bool pps_has_vdd_on(struct intel_display *display, int pps_idx) in pps_has_vdd_on() argument
285 return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on()
288 static bool pps_any(struct intel_display *display, int pps_idx) in pps_any() argument
293 static enum pipe
294 vlv_initial_pps_pipe(struct intel_display *display, in vlv_initial_pps_pipe() argument
297 enum pipe pipe; in vlv_initial_pps_pipe() local
299 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
300 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe()
301 PP_ON_DELAYS(display, pipe)) & in vlv_initial_pps_pipe()
307 if (!check(display, pipe)) in vlv_initial_pps_pipe()
310 return pipe; in vlv_initial_pps_pipe()
319 struct intel_display *display = to_intel_display(intel_dp); in vlv_initial_power_sequencer_setup() local
321 enum port port = dig_port->base.port; in vlv_initial_power_sequencer_setup()
323 lockdep_assert_held(&display->pps.mutex); in vlv_initial_power_sequencer_setup()
325 /* try to find a pipe with this port selected */ in vlv_initial_power_sequencer_setup()
327 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
330 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
331 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
334 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in vlv_initial_power_sequencer_setup()
335 intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port, in vlv_initial_power_sequencer_setup()
339 if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) { in vlv_initial_power_sequencer_setup()
340 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
342 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_initial_power_sequencer_setup()
346 drm_dbg_kms(display->drm, in vlv_initial_power_sequencer_setup()
348 dig_port->base.base.base.id, dig_port->base.base.name, in vlv_initial_power_sequencer_setup()
352 static int intel_num_pps(struct intel_display *display) in intel_num_pps() argument
354 struct drm_i915_private *i915 = to_i915(display->drm); in intel_num_pps()
356 if (display->platform.valleyview || display->platform.cherryview) in intel_num_pps()
359 if (display->platform.geminilake || display->platform.broxton) in intel_num_pps()
376 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_is_valid() local
377 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_is_valid()
379 if (intel_dp->pps.pps_idx == 1 && in intel_pps_is_valid()
382 return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; in intel_pps_is_valid()
388 bxt_initial_pps_idx(struct intel_display *display, pps_check check) in bxt_initial_pps_idx() argument
390 int pps_idx, pps_num = intel_num_pps(display); in bxt_initial_pps_idx()
393 if (check(display, pps_idx)) in bxt_initial_pps_idx()
397 return -1; in bxt_initial_pps_idx()
403 struct intel_display *display = to_intel_display(intel_dp); in pps_initial_setup() local
404 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in pps_initial_setup()
405 struct intel_connector *connector = intel_dp->attached_connector; in pps_initial_setup()
407 lockdep_assert_held(&display->pps.mutex); in pps_initial_setup()
409 if (display->platform.valleyview || display->platform.cherryview) { in pps_initial_setup()
415 if (intel_num_pps(display) > 1) in pps_initial_setup()
416 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_initial_setup()
418 intel_dp->pps.pps_idx = 0; in pps_initial_setup()
420 if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display))) in pps_initial_setup()
421 intel_dp->pps.pps_idx = -1; in pps_initial_setup()
424 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
425 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on); in pps_initial_setup()
427 if (intel_dp->pps.pps_idx < 0) in pps_initial_setup()
428 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on); in pps_initial_setup()
430 if (intel_dp->pps.pps_idx < 0) { in pps_initial_setup()
431 intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any); in pps_initial_setup()
433 drm_dbg_kms(display->drm, in pps_initial_setup()
435 encoder->base.base.id, encoder->base.name, in pps_initial_setup()
438 drm_dbg_kms(display->drm, in pps_initial_setup()
440 encoder->base.base.id, encoder->base.name, in pps_initial_setup()
447 void vlv_pps_reset_all(struct intel_display *display) in vlv_pps_reset_all() argument
451 if (!HAS_DISPLAY(display)) in vlv_pps_reset_all()
464 for_each_intel_dp(display->drm, encoder) { in vlv_pps_reset_all()
467 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_reset_all()
469 if (encoder->type == INTEL_OUTPUT_EDP) in vlv_pps_reset_all()
470 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; in vlv_pps_reset_all()
474 void bxt_pps_reset_all(struct intel_display *display) in bxt_pps_reset_all() argument
478 if (!HAS_DISPLAY(display)) in bxt_pps_reset_all()
483 for_each_intel_dp(display->drm, encoder) { in bxt_pps_reset_all()
486 if (encoder->type == INTEL_OUTPUT_EDP) in bxt_pps_reset_all()
487 intel_dp->pps.bxt_pps_reset = true; in bxt_pps_reset_all()
502 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_get_registers() local
503 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_get_registers()
508 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_get_registers()
510 else if (display->platform.geminilake || display->platform.broxton) in intel_pps_get_registers()
513 pps_idx = intel_dp->pps.pps_idx; in intel_pps_get_registers()
515 regs->pp_ctrl = PP_CONTROL(display, pps_idx); in intel_pps_get_registers()
516 regs->pp_stat = PP_STATUS(display, pps_idx); in intel_pps_get_registers()
517 regs->pp_on = PP_ON_DELAYS(display, pps_idx); in intel_pps_get_registers()
518 regs->pp_off = PP_OFF_DELAYS(display, pps_idx); in intel_pps_get_registers()
521 if (display->platform.geminilake || display->platform.broxton || in intel_pps_get_registers()
523 regs->pp_div = INVALID_MMIO_REG; in intel_pps_get_registers()
525 regs->pp_div = PP_DIVISOR(display, pps_idx); in intel_pps_get_registers()
550 struct intel_display *display = to_intel_display(intel_dp); in edp_have_panel_power() local
552 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_power()
554 if ((display->platform.valleyview || display->platform.cherryview) && in edp_have_panel_power()
555 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in edp_have_panel_power()
558 return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
563 struct intel_display *display = to_intel_display(intel_dp); in edp_have_panel_vdd() local
565 lockdep_assert_held(&display->pps.mutex); in edp_have_panel_vdd()
567 if ((display->platform.valleyview || display->platform.cherryview) && in edp_have_panel_vdd()
568 intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) in edp_have_panel_vdd()
571 return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
576 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_check_power_unlocked() local
583 drm_WARN(display->drm, 1, in intel_pps_check_power_unlocked()
585 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_check_power_unlocked()
587 drm_dbg_kms(display->drm, in intel_pps_check_power_unlocked()
589 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_check_power_unlocked()
591 intel_de_read(display, _pp_stat_reg(intel_dp)), in intel_pps_check_power_unlocked()
592 intel_de_read(display, _pp_ctrl_reg(intel_dp))); in intel_pps_check_power_unlocked()
610 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_status() local
614 lockdep_assert_held(&display->pps.mutex); in wait_panel_status()
621 drm_dbg_kms(display->drm, in wait_panel_status()
623 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_status()
626 intel_de_read(display, pp_stat_reg), in wait_panel_status()
627 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
629 if (intel_de_wait(display, pp_stat_reg, mask, value, 5000)) in wait_panel_status()
630 drm_err(display->drm, in wait_panel_status()
632 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_status()
634 intel_de_read(display, pp_stat_reg), in wait_panel_status()
635 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
637 drm_dbg_kms(display->drm, "Wait complete\n"); in wait_panel_status()
642 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_on() local
645 drm_dbg_kms(display->drm, in wait_panel_on()
647 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_on()
654 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_off() local
657 drm_dbg_kms(display->drm, in wait_panel_off()
659 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_off()
666 struct intel_display *display = to_intel_display(intel_dp); in wait_panel_power_cycle() local
674 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); in wait_panel_power_cycle()
676 remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); in wait_panel_power_cycle()
678 drm_dbg_kms(display->drm, in wait_panel_power_cycle()
680 dig_port->base.base.base.id, dig_port->base.base.name, in wait_panel_power_cycle()
704 wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on, in wait_backlight_on()
705 intel_dp->pps.backlight_on_delay); in wait_backlight_on()
710 wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off, in edp_wait_backlight_off()
711 intel_dp->pps.backlight_off_delay); in edp_wait_backlight_off()
720 struct intel_display *display = to_intel_display(intel_dp); in ilk_get_pp_control() local
723 lockdep_assert_held(&display->pps.mutex); in ilk_get_pp_control()
725 control = intel_de_read(display, _pp_ctrl_reg(intel_dp)); in ilk_get_pp_control()
726 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
741 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_on_unlocked() local
745 bool need_to_disable = !intel_dp->pps.want_panel_vdd; in intel_pps_vdd_on_unlocked()
747 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_on_unlocked()
752 cancel_delayed_work(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_on_unlocked()
753 intel_dp->pps.want_panel_vdd = true; in intel_pps_vdd_on_unlocked()
758 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in intel_pps_vdd_on_unlocked()
759 intel_dp->pps.vdd_wakeref = intel_display_power_get(display, in intel_pps_vdd_on_unlocked()
765 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD on\n", in intel_pps_vdd_on_unlocked()
766 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
775 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
776 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
777 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
779 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
781 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_on_unlocked()
782 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
787 drm_dbg_kms(display->drm, in intel_pps_vdd_on_unlocked()
789 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_on_unlocked()
791 msleep(intel_dp->pps.panel_power_up_delay); in intel_pps_vdd_on_unlocked()
798 * Must be paired with intel_pps_vdd_off() or - to disable
799 * both VDD and panel power - intel_pps_off().
806 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_on() local
816 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", in intel_pps_vdd_on()
817 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_on()
818 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_vdd_on()
824 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_off_sync_unlocked() local
829 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_sync_unlocked()
831 drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd); in intel_pps_vdd_off_sync_unlocked()
836 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n", in intel_pps_vdd_off_sync_unlocked()
837 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_off_sync_unlocked()
846 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
847 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
850 drm_dbg_kms(display->drm, in intel_pps_vdd_off_sync_unlocked()
852 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_vdd_off_sync_unlocked()
854 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
855 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_off_sync_unlocked()
858 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_vdd_off_sync_unlocked()
862 intel_display_power_put(display, in intel_pps_vdd_off_sync_unlocked()
864 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_vdd_off_sync_unlocked()
874 cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work); in intel_pps_vdd_off_sync()
891 if (!intel_dp->pps.want_panel_vdd) in edp_panel_vdd_work()
898 struct intel_display *display = to_intel_display(intel_dp); in edp_panel_vdd_schedule_off() local
899 struct drm_i915_private *i915 = to_i915(display->drm); in edp_panel_vdd_schedule_off()
906 if (intel_dp->pps.initializing) in edp_panel_vdd_schedule_off()
914 delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5); in edp_panel_vdd_schedule_off()
915 queue_delayed_work(i915->unordered_wq, in edp_panel_vdd_schedule_off()
916 &intel_dp->pps.panel_vdd_work, delay); in edp_panel_vdd_schedule_off()
926 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_vdd_off_unlocked() local
928 lockdep_assert_held(&display->pps.mutex); in intel_pps_vdd_off_unlocked()
933 INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd, in intel_pps_vdd_off_unlocked()
935 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_vdd_off_unlocked()
936 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_vdd_off_unlocked()
939 intel_dp->pps.want_panel_vdd = false; in intel_pps_vdd_off_unlocked()
960 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_on_unlocked() local
964 lockdep_assert_held(&display->pps.mutex); in intel_pps_on_unlocked()
969 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power on\n", in intel_pps_on_unlocked()
970 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
971 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_on_unlocked()
974 if (drm_WARN(display->drm, edp_have_panel_power(intel_dp), in intel_pps_on_unlocked()
976 dp_to_dig_port(intel_dp)->base.base.base.id, in intel_pps_on_unlocked()
977 dp_to_dig_port(intel_dp)->base.base.name, in intel_pps_on_unlocked()
985 if (display->platform.ironlake) { in intel_pps_on_unlocked()
988 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
989 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
996 if (IS_DISPLAY_VER(display, 13, 14)) in intel_pps_on_unlocked()
997 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in intel_pps_on_unlocked()
1001 if (!display->platform.ironlake) in intel_pps_on_unlocked()
1004 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1005 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1008 intel_dp->pps.last_power_on = jiffies; in intel_pps_on_unlocked()
1010 if (IS_DISPLAY_VER(display, 13, 14)) in intel_pps_on_unlocked()
1011 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in intel_pps_on_unlocked()
1014 if (display->platform.ironlake) { in intel_pps_on_unlocked()
1016 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1017 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1034 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_off_unlocked() local
1039 lockdep_assert_held(&display->pps.mutex); in intel_pps_off_unlocked()
1044 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turn panel power off\n", in intel_pps_off_unlocked()
1045 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_off_unlocked()
1048 drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd, in intel_pps_off_unlocked()
1050 dig_port->base.base.base.id, dig_port->base.base.name, in intel_pps_off_unlocked()
1061 intel_dp->pps.want_panel_vdd = false; in intel_pps_off_unlocked()
1063 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
1064 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_off_unlocked()
1067 intel_dp->pps.panel_power_off_time = ktime_get_boottime(); in intel_pps_off_unlocked()
1072 intel_display_power_put(display, in intel_pps_off_unlocked()
1074 fetch_and_zero(&intel_dp->pps.vdd_wakeref)); in intel_pps_off_unlocked()
1091 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_backlight_on() local
1109 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_on()
1110 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_on()
1117 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_backlight_off() local
1130 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_off()
1131 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_off()
1134 intel_dp->pps.last_backlight_off = jiffies; in intel_pps_backlight_off()
1144 struct intel_display *display = to_intel_display(connector); in intel_pps_backlight_power() local
1155 drm_dbg_kms(display->drm, "panel power control backlight %s\n", in intel_pps_backlight_power()
1166 struct intel_display *display = to_intel_display(intel_dp); in vlv_detach_power_sequencer() local
1168 enum pipe pipe = intel_dp->pps.vlv_pps_pipe; in vlv_detach_power_sequencer() local
1169 i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); in vlv_detach_power_sequencer()
1171 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_detach_power_sequencer()
1173 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1187 drm_dbg_kms(display->drm, in vlv_detach_power_sequencer()
1190 dig_port->base.base.base.id, dig_port->base.base.name); in vlv_detach_power_sequencer()
1191 intel_de_write(display, pp_on_reg, 0); in vlv_detach_power_sequencer()
1192 intel_de_posting_read(display, pp_on_reg); in vlv_detach_power_sequencer()
1194 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; in vlv_detach_power_sequencer()
1197 static void vlv_steal_power_sequencer(struct intel_display *display, in vlv_steal_power_sequencer() argument
1198 enum pipe pipe) in vlv_steal_power_sequencer() argument
1202 lockdep_assert_held(&display->pps.mutex); in vlv_steal_power_sequencer()
1204 for_each_intel_dp(display->drm, encoder) { in vlv_steal_power_sequencer()
1207 drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe, in vlv_steal_power_sequencer()
1209 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1210 encoder->base.name); in vlv_steal_power_sequencer()
1212 if (intel_dp->pps.vlv_pps_pipe != pipe) in vlv_steal_power_sequencer()
1215 drm_dbg_kms(display->drm, in vlv_steal_power_sequencer()
1217 pipe_name(pipe), encoder->base.base.id, in vlv_steal_power_sequencer()
1218 encoder->base.name); in vlv_steal_power_sequencer()
1225 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) in vlv_active_pipe()
1227 struct intel_display *display = to_intel_display(intel_dp); in vlv_active_pipe() local
1228 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in vlv_active_pipe()
1229 enum pipe pipe; in vlv_active_pipe() local
1231 if (g4x_dp_port_enabled(display, intel_dp->output_reg, in vlv_active_pipe()
1232 encoder->port, &pipe)) in vlv_active_pipe()
1233 return pipe; in vlv_active_pipe()
1241 intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; in vlv_pps_pipe_init()
1242 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); in vlv_pps_pipe_init()
1251 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); in vlv_pps_pipe_reset()
1254 enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp) in vlv_pps_backlight_initial_pipe()
1256 enum pipe pipe; in vlv_pps_backlight_initial_pipe() local
1259 * Figure out the current pipe for the initial backlight setup. If the in vlv_pps_backlight_initial_pipe()
1260 * current pipe isn't valid, try the PPS pipe, and if that fails just in vlv_pps_backlight_initial_pipe()
1261 * assume pipe A. in vlv_pps_backlight_initial_pipe()
1263 pipe = vlv_active_pipe(intel_dp); in vlv_pps_backlight_initial_pipe()
1265 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1266 pipe = intel_dp->pps.vlv_pps_pipe; in vlv_pps_backlight_initial_pipe()
1268 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1269 pipe = PIPE_A; in vlv_pps_backlight_initial_pipe()
1271 return pipe; in vlv_pps_backlight_initial_pipe()
1278 struct intel_display *display = to_intel_display(encoder); in vlv_pps_port_enable_unlocked() local
1280 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_pps_port_enable_unlocked()
1282 lockdep_assert_held(&display->pps.mutex); in vlv_pps_port_enable_unlocked()
1284 drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); in vlv_pps_port_enable_unlocked()
1286 if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE && in vlv_pps_port_enable_unlocked()
1287 intel_dp->pps.vlv_pps_pipe != crtc->pipe) { in vlv_pps_port_enable_unlocked()
1300 vlv_steal_power_sequencer(display, crtc->pipe); in vlv_pps_port_enable_unlocked()
1302 intel_dp->pps.vlv_active_pipe = crtc->pipe; in vlv_pps_port_enable_unlocked()
1308 intel_dp->pps.vlv_pps_pipe = crtc->pipe; in vlv_pps_port_enable_unlocked()
1310 drm_dbg_kms(display->drm, in vlv_pps_port_enable_unlocked()
1313 encoder->base.base.id, encoder->base.name); in vlv_pps_port_enable_unlocked()
1315 /* init power sequencer on this pipe and port */ in vlv_pps_port_enable_unlocked()
1329 intel_dp->pps.vlv_active_pipe = INVALID_PIPE; in vlv_pps_port_disable()
1334 struct intel_display *display = to_intel_display(intel_dp); in pps_vdd_init() local
1337 lockdep_assert_held(&display->pps.mutex); in pps_vdd_init()
1348 drm_dbg_kms(display->drm, in pps_vdd_init()
1350 dig_port->base.base.base.id, dig_port->base.base.name, in pps_vdd_init()
1352 drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); in pps_vdd_init()
1353 intel_dp->pps.vdd_wakeref = intel_display_power_get(display, in pps_vdd_init()
1378 intel_dp->pps.panel_power_off_time = 0; in pps_init_timestamps()
1379 intel_dp->pps.last_power_on = jiffies; in pps_init_timestamps()
1380 intel_dp->pps.last_backlight_off = jiffies; in pps_init_timestamps()
1386 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_readout_hw_state() local
1395 if (!HAS_DDI(display)) in intel_pps_readout_hw_state()
1396 intel_de_write(display, regs.pp_ctrl, pp_ctl); in intel_pps_readout_hw_state()
1398 pp_on = intel_de_read(display, regs.pp_on); in intel_pps_readout_hw_state()
1399 pp_off = intel_de_read(display, regs.pp_off); in intel_pps_readout_hw_state()
1402 seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1403 seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
1404 seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1405 seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1410 pp_div = intel_de_read(display, regs.pp_div); in intel_pps_readout_hw_state()
1418 seq->power_cycle = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0; in intel_pps_readout_hw_state()
1425 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_dump_state() local
1427 drm_dbg_kms(display->drm, in intel_pps_dump_state()
1429 state_name, seq->power_up, seq->backlight_on, in intel_pps_dump_state()
1430 seq->backlight_off, seq->power_down, seq->power_cycle); in intel_pps_dump_state()
1436 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_verify_state() local
1438 struct intel_pps_delays *sw = &intel_dp->pps.pps_delays; in intel_pps_verify_state()
1442 if (hw.power_up != sw->power_up || in intel_pps_verify_state()
1443 hw.backlight_on != sw->backlight_on || in intel_pps_verify_state()
1444 hw.backlight_off != sw->backlight_off || in intel_pps_verify_state()
1445 hw.power_down != sw->power_down || in intel_pps_verify_state()
1446 hw.power_cycle != sw->power_cycle) { in intel_pps_verify_state()
1447 drm_err(display->drm, "PPS state mismatch\n"); in intel_pps_verify_state()
1455 return delays->power_up || delays->backlight_on || delays->backlight_off || in pps_delays_valid()
1456 delays->power_down || delays->power_cycle; in pps_delays_valid()
1474 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_bios() local
1476 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_bios()
1478 if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays)) in pps_init_delays_bios()
1479 intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays); in pps_init_delays_bios()
1481 *bios = intel_dp->pps.bios_pps_delays; in pps_init_delays_bios()
1489 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_vbt() local
1490 struct intel_connector *connector = intel_dp->attached_connector; in pps_init_delays_vbt()
1492 *vbt = connector->panel.vbt.edp.pps; in pps_init_delays_vbt()
1498 * On Toshiba Satellite P50-C-18C system the VBT T12 delay in pps_init_delays_vbt()
1503 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) { in pps_init_delays_vbt()
1504 vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300)); in pps_init_delays_vbt()
1505 drm_dbg_kms(display->drm, in pps_init_delays_vbt()
1507 vbt->power_cycle); in pps_init_delays_vbt()
1516 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays_spec() local
1518 lockdep_assert_held(&display->pps.mutex); in pps_init_delays_spec()
1521 spec->power_up = msecs_to_pps_units(10 + 200); /* T1+T3 */ in pps_init_delays_spec()
1522 spec->backlight_on = msecs_to_pps_units(50); /* no limit for T8, use T7 instead */ in pps_init_delays_spec()
1523 spec->backlight_off = msecs_to_pps_units(50); /* no limit for T9, make it symmetric with T8 */ in pps_init_delays_spec()
1524 spec->power_down = msecs_to_pps_units(500); /* T10 */ in pps_init_delays_spec()
1525 spec->power_cycle = msecs_to_pps_units(10 + 500); /* T11+T12 */ in pps_init_delays_spec()
1532 struct intel_display *display = to_intel_display(intel_dp); in pps_init_delays() local
1534 *final = &intel_dp->pps.pps_delays; in pps_init_delays()
1536 lockdep_assert_held(&display->pps.mutex); in pps_init_delays()
1548 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ in pps_init_delays()
1558 intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up); in pps_init_delays()
1559 intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on); in pps_init_delays()
1560 intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off); in pps_init_delays()
1561 intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down); in pps_init_delays()
1562 intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle); in pps_init_delays()
1564 drm_dbg_kms(display->drm, in pps_init_delays()
1566 intel_dp->pps.panel_power_up_delay, in pps_init_delays()
1567 intel_dp->pps.panel_power_down_delay, in pps_init_delays()
1568 intel_dp->pps.panel_power_cycle_delay); in pps_init_delays()
1570 drm_dbg_kms(display->drm, "backlight on delay %d, off delay %d\n", in pps_init_delays()
1571 intel_dp->pps.backlight_on_delay, in pps_init_delays()
1572 intel_dp->pps.backlight_off_delay); in pps_init_delays()
1582 final->backlight_on = 1; in pps_init_delays()
1583 final->backlight_off = 1; in pps_init_delays()
1589 final->power_cycle = roundup(final->power_cycle, msecs_to_pps_units(100)); in pps_init_delays()
1594 struct intel_display *display = to_intel_display(intel_dp); in pps_init_registers() local
1595 struct drm_i915_private *dev_priv = to_i915(display->drm); in pps_init_registers()
1597 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; in pps_init_registers()
1599 enum port port = dp_to_dig_port(intel_dp)->base.port; in pps_init_registers()
1600 const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays; in pps_init_registers()
1602 lockdep_assert_held(&display->pps.mutex); in pps_init_registers()
1621 drm_WARN(display->drm, pp & PANEL_POWER_ON, in pps_init_registers()
1625 drm_dbg_kms(display->drm, in pps_init_registers()
1630 intel_de_write(display, regs.pp_ctrl, pp); in pps_init_registers()
1633 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) | in pps_init_registers()
1634 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on); in pps_init_registers()
1635 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) | in pps_init_registers()
1636 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down); in pps_init_registers()
1640 if (display->platform.valleyview || display->platform.cherryview) { in pps_init_registers()
1661 intel_de_write(display, regs.pp_on, pp_on); in pps_init_registers()
1662 intel_de_write(display, regs.pp_off, pp_off); in pps_init_registers()
1668 intel_de_write(display, regs.pp_div, in pps_init_registers()
1670 (100 * div) / 2 - 1) | in pps_init_registers()
1672 DIV_ROUND_UP(seq->power_cycle, 1000) + 1)); in pps_init_registers()
1674 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK, in pps_init_registers()
1676 DIV_ROUND_UP(seq->power_cycle, 1000) + 1)); in pps_init_registers()
1678 drm_dbg_kms(display->drm, in pps_init_registers()
1680 intel_de_read(display, regs.pp_on), in pps_init_registers()
1681 intel_de_read(display, regs.pp_off), in pps_init_registers()
1683 intel_de_read(display, regs.pp_div) : in pps_init_registers()
1684 (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); in pps_init_registers()
1689 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_encoder_reset() local
1700 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_encoder_reset()
1717 intel_dp->pps.initializing = true; in intel_pps_init()
1718 INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); in intel_pps_init()
1735 struct intel_display *display = to_intel_display(intel_dp); in pps_init_late() local
1736 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in pps_init_late()
1737 struct intel_connector *connector = intel_dp->attached_connector; in pps_init_late()
1739 if (display->platform.valleyview || display->platform.cherryview) in pps_init_late()
1742 if (intel_num_pps(display) < 2) in pps_init_late()
1745 drm_WARN(display->drm, in pps_init_late()
1746 connector->panel.vbt.backlight.controller >= 0 && in pps_init_late()
1747 intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller, in pps_init_late()
1749 encoder->base.base.id, encoder->base.name, in pps_init_late()
1750 intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller); in pps_init_late()
1752 if (connector->panel.vbt.backlight.controller >= 0) in pps_init_late()
1753 intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller; in pps_init_late()
1761 /* Reinit delays after per-panel info has been parsed from VBT */ in intel_pps_init_late()
1764 memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays)); in intel_pps_init_late()
1768 intel_dp->pps.initializing = false; in intel_pps_init_late()
1775 void intel_pps_unlock_regs_wa(struct intel_display *display) in intel_pps_unlock_regs_wa() argument
1780 if (!HAS_DISPLAY(display) || HAS_DDI(display)) in intel_pps_unlock_regs_wa()
1786 pps_num = intel_num_pps(display); in intel_pps_unlock_regs_wa()
1789 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa()
1793 void intel_pps_setup(struct intel_display *display) in intel_pps_setup() argument
1795 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pps_setup()
1797 if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton) in intel_pps_setup()
1798 display->pps.mmio_base = PCH_PPS_BASE; in intel_pps_setup()
1799 else if (display->platform.valleyview || display->platform.cherryview) in intel_pps_setup()
1800 display->pps.mmio_base = VLV_PPS_BASE; in intel_pps_setup()
1802 display->pps.mmio_base = PPS_BASE; in intel_pps_setup()
1807 struct intel_connector *connector = m->private; in intel_pps_show()
1810 if (connector->base.status != connector_status_connected) in intel_pps_show()
1811 return -ENODEV; in intel_pps_show()
1814 intel_dp->pps.panel_power_up_delay); in intel_pps_show()
1816 intel_dp->pps.panel_power_down_delay); in intel_pps_show()
1818 intel_dp->pps.panel_power_cycle_delay); in intel_pps_show()
1820 intel_dp->pps.backlight_on_delay); in intel_pps_show()
1822 intel_dp->pps.backlight_off_delay); in intel_pps_show()
1830 struct dentry *root = connector->base.debugfs_entry; in intel_pps_connector_debugfs_add()
1831 int connector_type = connector->base.connector_type; in intel_pps_connector_debugfs_add()
1838 void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) in assert_pps_unlocked() argument
1840 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_pps_unlocked()
1843 enum pipe panel_pipe = INVALID_PIPE; in assert_pps_unlocked()
1846 if (drm_WARN_ON(display->drm, HAS_DDI(display))) in assert_pps_unlocked()
1852 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
1853 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
1861 g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe); in assert_pps_unlocked()
1864 g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe); in assert_pps_unlocked()
1867 g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe); in assert_pps_unlocked()
1873 } else if (display->platform.valleyview || display->platform.cherryview) { in assert_pps_unlocked()
1874 /* presumably write lock depends on pipe, not port select */ in assert_pps_unlocked()
1875 pp_reg = PP_CONTROL(display, pipe); in assert_pps_unlocked()
1876 panel_pipe = pipe; in assert_pps_unlocked()
1880 pp_reg = PP_CONTROL(display, 0); in assert_pps_unlocked()
1881 port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) & in assert_pps_unlocked()
1884 drm_WARN_ON(display->drm, in assert_pps_unlocked()
1889 val = intel_de_read(display, pp_reg); in assert_pps_unlocked()
1894 INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked, in assert_pps_unlocked()
1895 "panel assertion failure, pipe %c regs locked\n", in assert_pps_unlocked()
1896 pipe_name(pipe)); in assert_pps_unlocked()